Semiconductor device

Abstract

The utility model provides a semiconductor device. The semiconductor device comprises a substrate; a plurality of lower electrodes on one side surface of the substrate; a support layer in direct contact with sidewalls of the plurality of lower electrodes, the support layer further including a plurality of openings and spacers; wherein part of the openings are connected with each other through the lower electrodes to form opening parts, the opening parts are arranged in multiple rows in a staggered mode in the first direction, and the opening parts in the same row are isolated from each other through interval parts. According to the semiconductor device, the spacing part is arranged between the adjacent opening parts in each row in the semiconductor device, the number of the openings is reduced, on the basis that the supporting layer provides support for the lower electrode of the semiconductor device, the spacing part enables the distribution of the openings to be more uniform under the condition that the stability of the supporting layer is not damaged, support is provided for the lower electrode, and the reliability of the semiconductor device is improved. And the stability of the semiconductor device is improved. The problem that the lower electrode of the semiconductor device is easy to collapse in the prior art is solved.

Description

Technical Field

[0001] The present application relates to the technical field of semiconductor devices, and in particular, to a semiconductor device. Background Art

[0002] As semiconductor components develop towards high density, the size of components in the unit area is continuously reduced.Semiconductor devices such as dynamic random access memory (DRAM) may require a certain capacitance level in each unit.Therefore, in order to avoid the capacitance reduction of capacitor elements, capacitor elements need a larger effective surface area.However, when capacitor elements are made into lower electrodes with high aspect ratios, the instability of capacitor elements may be caused.For example, they may collapse and contact adjacent other capacitor elements, thereby causing damage and leakage current.

[0003] In the prior art, in order to prevent the lower electrode from collapsing, a support layer is usually formed around the lower electrode to support the lower electrode. However, if only relying on the support layer may result in insufficient support strength, there is still a risk of the lower electrode collapsing. Utility Model Content

[0004] The present application provides a semiconductor device to solve the problem of easy collapse of the lower electrode of the semiconductor device in the related art.

[0005] According to one aspect of the present application, a semiconductor device is provided, comprising: a substrate; a plurality of lower electrodes located on one side surface of the substrate; a support layer directly contacting the side walls of the plurality of lower electrodes, the support layer further comprising a plurality of openings and spacers; wherein some of the openings are connected to each other through the lower electrodes to form openings, the openings are staggered and arranged into a plurality of rows along a first direction, and the openings in the same row are isolated from each other by the spacers.

[0006] Optionally, a hexagon is formed with the spacer as the center, and the six openings closest to the spacer are located at endpoints of the hexagon.

[0007] Optionally, the endpoints of the hexagon are located at the center of the opening.

[0008] Optionally, the distance from the center of the spacer to any endpoint of the hexagon is equal to the distance between any two adjacent endpoints of the hexagon.

[0009] Optionally, the hexagon is a hexagon that is approximately a regular hexagon.

[0010] Optionally, the openings in any two adjacent rows in the first direction are staggered.

[0011] Optionally, the opening portion consists of at least two openings.

[0012] Optionally, the semiconductor device further includes a dielectric layer, and the dielectric layer covers the lower electrode and the exposed surface of the support layer.

[0013] Optionally, the semiconductor device further includes an upper electrode layer, wherein the upper electrode covers the dielectric layer, and a portion of the upper electrode is located between any two adjacent lower electrodes.

[0014] Optionally, the shape of the lower electrode includes at least one of the following: cylindrical and columnar.

[0015] The technical solution of the present application provides a semiconductor device, comprising: a substrate, multiple lower electrodes, and a support layer, wherein the support layer directly contacts the sidewalls of the multiple lower electrodes. The support layer further comprises multiple openings and spacers, some of which are connected to each other through the lower electrodes to form openings. The openings are arranged in multiple rows staggered along a first direction, and the openings in a row are isolated from each other by the spacers. By providing spacers between adjacent openings in each row of the semiconductor device, the number of openings is reduced. On the basis of the support layer providing support for the lower electrode of the semiconductor device, the spacers make the distribution of the openings more uniform without destroying the stability of the support layer, providing support for the lower electrode and improving the stability of the semiconductor device. This solves the problem of the lower electrode of the semiconductor device being prone to collapse in the related art. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The accompanying drawings, which constitute part of this application, are intended to provide a further understanding of this application. The exemplary embodiments and descriptions of this application are intended to explain this application and do not constitute an improper limitation on this application. In the accompanying drawings:

[0017] Figure 1 This is a schematic diagram of a top view of a semiconductor device provided in the prior art;

[0018] Figure 2 is a schematic top view of a semiconductor device provided according to an embodiment of the present application;

[0019] Figure 3 is a schematic top view of another semiconductor device provided according to an embodiment of the present application;

[0020] Figure 4 1 is a schematic top view of another semiconductor device provided according to an embodiment of the present application;

[0021] Figure 5 is a schematic cross-sectional structural diagram of a semiconductor device provided according to an embodiment of the present application;

[0022] Figure 6 This is a schematic cross-sectional structure diagram of a base body after providing a substrate and forming a first sacrificial layer, a first supporting layer, a second sacrificial layer, and a second supporting layer on a base in a method for preparing a semiconductor device provided in an embodiment of the present application;

[0023] Figure 7 is Figure 6 A schematic cross-sectional structure diagram of the substrate after a first sacrificial layer, a first supporting layer, a second sacrificial layer and a lower electrode opening are formed in the second supporting layer;

[0024] Figure 8 yes Figure 7 Schematic diagram of the top view structure;

[0025] Figure 9 is Figure 7 A schematic cross-sectional structure diagram of the substrate after the lower electrode is formed in the lower electrode opening formed in the substrate;

[0026] Figure 10 yes Figure 9 Schematic diagram of the top view structure;

[0027] Figure 11 is Figure 9 A schematic diagram of the cross-sectional structure of the substrate after a preliminary opening is formed in the second supporting layer;

[0028] Figure 12 yes Figure 11 Schematic diagram of the top view structure;

[0029] Figure 13 is Figure 11 A schematic diagram of the cross-sectional structure of the substrate after openings are formed in the first sacrificial layer, the first supporting layer, the second sacrificial layer, and the second supporting layer;

[0030] Figure 14 yes Figure 13 Schematic diagram of the top view structure.

[0031] The above drawings include the following reference numerals:

[0032] 10. Substrate; 20. Lower electrode; 21. Lower electrode opening; 30. Support layer; 31. Opening; 310. Preparatory opening; 32. Spacer; 33. Opening; 34. First support layer; 35. Second support layer; 40. Dielectric layer; 50. Upper electrode; 60. Sacrificial layer; 61. First sacrificial layer; 62. Second sacrificial layer. DETAILED DESCRIPTION

[0033] It should be noted that, in the absence of conflict, the embodiments and features of the embodiments in this application can be combined with each other. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0034] In order to enable those skilled in the art to better understand the present invention, the following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments in the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of this application.

[0035] It should be noted that the terms "first", "second", etc. in the specification and claims of this application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the numbers used in this way can be interchanged where appropriate for the embodiments of the present application described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0036] like Figure 1 As shown, in the prior art, in order to prevent the lower electrode from collapsing, a support layer 30 is usually formed around the lower electrode to support the lower electrode 20, and an opening 31 is set between the three lower electrodes. This will cause each lower electrode 20 to lack a portion of supporting force. Even if the support layer 30 can provide a portion of supporting force, the stability of this semiconductor device is still relatively poor, and there is still a risk of the lower electrode collapsing.

[0037] Therefore, research on the above issues is conducted, such as Figures 2 to 5 As shown, a semiconductor device is provided in an embodiment of the present application, including: a substrate 10; a plurality of lower electrodes 20, located on one side surface of the above-mentioned substrate 10; a support layer 30, directly contacting the side walls of the above-mentioned plurality of lower electrodes 20, and the above-mentioned support layer 30 also includes a plurality of openings 31 and spacers 32; wherein, some of the above-mentioned openings 31 are connected to each other through the above-mentioned lower electrodes 20 to form openings 33, and the above-mentioned openings 33 are staggered and arranged into multiple rows along the first direction X, and the above-mentioned openings 33 in the same row are isolated from each other by the above-mentioned spacers 32.

[0038] By providing the above-mentioned spacing portions between the opening portions in each row consisting of a plurality of openings, the number of openings in the semiconductor device is reduced, a portion of the lower electrode is completely surrounded by the supporting layer, and the supporting force of the lower electrode is increased. Without destroying the stability of the supporting layer, the opening distribution is made more uniform to achieve an optimized process, and then the spacing portions cooperate with the supporting layer to enhance the stability of the entire semiconductor device.

[0039] In the above optional embodiment, the projection shape of the above opening on the side surface of the above substrate includes at least one of the following: ellipse and circle. The above substrate is a semiconductor substrate, and an active area and a peripheral area (not marked in the figure) are provided on the substrate, and the peripheral area is provided on the periphery of the active area. A plurality of node contacts (not shown in the figure) are also formed in the substrate, and the node contacts are electrically connected to the lower electrode. Of course, other device structures such as active patterns (not shown in the figure) and isolation structures (not shown in the figure) can also be formed in the substrate, and this application does not limit this. The material of the supporting layer includes an insulating material, which may include at least one of silicon oxynitride (SiON), silicon nitride (SiN), silicon carbon nitride (SiCN), silicon oxycarbon nitride (SiOCN) and silicon boron nitride (SiBN).

[0040] In some optional embodiments, such as Figures 2 to 4 As shown, a hexagon is formed with the partition 32 as the center, and the six openings closest to the partition 32 are located at the endpoints of the hexagon.

[0041] In the above optional implementation manner, if Figure 2 As shown, the opening portion 33 is composed of two openings 31, and there is a spacer 32 between each row of the openings 33. The spacer 32 and the openings 31 around the spacer 32 form a hexagon, wherein the center of the hexagon is located at the center of the spacer 32, and the endpoints of the hexagon are located at the centers of the surrounding openings 31. Figure 3 As shown, the opening portion 33 is composed of three openings 31, and there is a spacer 32 between each row of the openings 33. The spacer 32 and the openings 31 around the spacer 32 form a hexagon, wherein the center of the hexagon is located at the center of the spacer 32, and the endpoints of the hexagon are located at the centers of the surrounding openings 31. Figure 4 As shown, the openings 33 are composed of four openings 31. Each row of openings 33 is separated by a spacer 32. The spacers 32 and the openings 31 surrounding them form a hexagon, with the center of the hexagon located at the center of the spacer 32 and the endpoints of the hexagon located at the centers of the surrounding openings 31. The distribution of the spacers 32 and openings 33 improves the uniformity of the openings 31 in the semiconductor device and improves the stability of the device.

[0042] In some optional embodiments, such as Figures 2 to 4 As shown, the distance from the center of the spacer 32 to any endpoint of the hexagon is equal to the distance between any two adjacent endpoints of the hexagon.

[0043] In the above optional implementation manner, if Figures 2 to 4 As shown, the first spacing between the center of the spacer 32 and each endpoint of the hexagon is equal, the second spacing between any two adjacent endpoints of the hexagon is equal, and the first spacing is equal to the second spacing, that is, the hexagon is a regular hexagon. The hexagon can also be a hexagon that approximates a regular hexagon.

[0044] In some optional embodiments, such as Figures 2 to 4 As shown, the openings 31 in any two adjacent rows in the first direction X are staggered.

[0045] In the above optional implementation manner, if Figures 2 to 4 As shown, the openings 31 between adjacent rows are staggered, and the staggered openings 31 form the above-mentioned opening portion 33. The opening portions 33 between adjacent rows are also staggered. The staggered distribution can enhance the support effect.

[0046] In some optional embodiments, such as Figure 2 and Figure 4 As shown, the opening portion 33 is composed of at least two of the openings 31 .

[0047] In the above optional implementation manner, if Figure 2 As shown, the opening portion 33 is composed of two openings 31. Figure 3 As shown, the opening portion 33 is composed of three openings 31. Figure 4 As shown, the opening portion 33 is composed of four openings 31. The opening portion 33 may also be composed of five, six, or more openings 31. In the case of a relatively large semiconductor device, more openings 31 may be used to form the opening portion 33, thereby ensuring the stability of the larger device.

[0048] In the above optional implementation manner, if Figures 2 to 5 As shown, the plurality of lower electrodes 20 are spaced apart in multiple rows along the first direction X, with adjacent rows of the lower electrodes 20 being staggered. The spacing between adjacent rows of the lower electrodes 20 is smaller than the spacing between adjacent rows of the openings 31. Two rows of the lower electrodes 20 are spaced apart between any two adjacent rows of the openings 31. If the semiconductor device has high stability requirements, more rows of the lower electrodes 20 may be disposed between any two adjacent rows of the openings 31 to increase the distribution area of ​​the openings 31 and provide stronger support for the lower electrodes 20.

[0049] In some optional embodiments, such as Figure 5 As shown, the semiconductor device further includes a dielectric layer 40 , and the dielectric layer 40 covers the exposed surfaces of the lower electrode 20 and the support layer 30 .

[0050] In the above optional implementation manner, if Figure 5 As shown, dielectric layer 40 covers the surface of lower electrode 20 and the surfaces of first and second supporting layers 34 and 35. Dielectric layer 40 is an insulating layer for semiconductor devices and can be a high-k dielectric layer made of at least one of silicon oxide and silicon nitride. Dielectric layer 40 covers the surface of lower electrode 20 and support layer 30, i.e., dielectric layer 40 extends along the contours of lower electrode 20 and support layer 30.

[0051] In some optional embodiments, such as Figure 5 As shown, the semiconductor device further includes an upper electrode 50 . The upper electrode 50 covers the dielectric layer 40 , and a portion of the upper electrode 50 is located between any two adjacent lower electrodes 20 .

[0052] In the above optional implementation manner, if Figure 5 As shown, the upper electrode 50 covers the surface of the dielectric layer 40 and fills the lower electrodes 20 and between two adjacent lower electrodes 20. The upper electrode 50 achieves planarization of the semiconductor device. The material of the upper electrode 50 includes at least one of silicon doped with impurities, a metal material, a metal nitride, and a metal silicide. The lower electrode 20, the dielectric layer 40, and the upper electrode 50 are the main structures of the semiconductor device.

[0053] In some optional embodiments, such as Figure 5 As shown, the shape of the lower electrode 20 includes at least one of the following: a cylindrical shape and a columnar shape.

[0054] In the above optional implementation manner, if Figure 5 As shown, the support layer 30 is disposed around each lower electrode 20 and directly contacts the outer side of each lower electrode 20 to support each lower electrode 20. In other words, the lower electrode 20 passes through the first support layer 34 and the second support layer 35. The support layer 30 is disposed on the outer side of the cylindrical or columnar lower electrode 20 and contacts the outer side of the lower electrode 20. The extension direction of the support layer 30 is perpendicular to the extension direction of the lower electrode 20. The lower electrode 20 extends vertically in the semiconductor device, and the support layer 30 extends horizontally in the semiconductor device. The horizontally extending support layer 30 can effectively support the lower electrode 20, so that the lower electrode 20 does not collapse. The upper surface of the support layer 30 is flush with the top of the lower electrode 20, so as to planarize the semiconductor device.

[0055] In the above optional implementation manner, if Figures 2 to 5 As shown, the support layer 30 may include a first support layer 34 and a second support layer 35 . The second support layer 35 is located on a side of the first support layer 34 facing away from the substrate 10 .

[0056] The method for preparing the semiconductor device may include:

[0057] Step S1: Figure 6 As shown, a substrate 10 is provided.

[0058] Specifically, the substrate 10 can be a semiconductor substrate, on which an active region and a peripheral region (not labeled in the figure) are provided, with the peripheral region being provided outside the active region. A plurality of node contacts (not shown in the figure) are also formed in the substrate 10, and the node contacts are electrically connected to the bottom electrode. Of course, other device structures such as an active pattern (not shown in the figure) and an isolation structure (not shown in the figure) may also be formed in the substrate 10, and this application does not limit this.

[0059] Step S2: Figure 6 As shown, a first sacrificial layer 61 , a first supporting layer 34 , a second sacrificial layer 62 and a second supporting layer 35 are sequentially formed on the substrate 10 .

[0060] Specifically, the first sacrificial layer 61 serves to form a substrate for the subsequent support layer and lower electrode. Specifically, the first support layer 34 and the second support layer 35 include an insulating material, which may include at least one of silicon oxynitride (SiON), silicon nitride (SiN), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), and silicon boron nitride (SiBN). The first support layer 34 extends in a direction parallel to the direction of extension of one side surface of the substrate 10.

[0061] Step S3: Figure 7 and Figure 8 As shown, a plurality of lower electrode openings 21 are formed and spaced apart through the support layer 30 and the sacrificial layer 60 . The support layer 30 includes a first support layer 34 and a second support layer 35 , and the sacrificial layer 60 includes a first sacrificial layer 61 and a second sacrificial layer 62 .

[0062] Specifically, such as Figure 7 As shown, a mask etching method can be used to form multiple lower electrode openings 21 that penetrate the support layer 30 (including the first support layer 34 and the second support layer 35) and the sacrificial layer 60 (including the first sacrificial layer 61 and the second sacrificial layer 62) and are spaced apart. The bottom of the lower electrode openings 21 is the substrate 10. Figure 8 As shown, the multiple lower electrode openings 21 are arranged in an array in a top view, and the substrate 10 can be seen. The cross-sectional shape of each lower electrode opening 21 on the side surface parallel to the substrate 10 and close to the support layer 30 is circular.

[0063] Step S4: Figure 9 and Figure 10 As shown, a plurality of lower electrodes 20 are formed in the plurality of lower electrode openings.

[0064] Specifically, if Figure 9 As shown, the shape of the lower electrode 20 is a cylindrical or columnar structure with an opening facing upward. The material of the lower electrode 20 can be titanium nitride (TiN). A plurality of lower electrodes 20 are arranged in an array. Figure 10 As shown, in a top view, what is seen are the lower electrodes 20 arranged in an array in the support layer 30 .

[0065] Step S5: Figure 11 and Figure 12 As shown, a plurality of preliminary openings 310 are formed through the support layer 30 and are arranged at intervals.

[0066] Specifically, if Figure 11 and Figure 12 As shown, in order to subsequently remove the sacrificial layer 60 (including the first sacrificial layer 61 and the second sacrificial layer 62) and form a dielectric layer and an upper electrode on the surface of the lower electrode 20, it is necessary to form a preliminary opening 310 in the second supporting layer 35 to expose the second sacrificial layer 62 and provide a flow channel for the etching machine for the subsequent removal of the sacrificial layer 60. The preliminary openings 310 are formed by removing a portion of the second supporting layer 35. Each preliminary opening 310 contacts several lower electrodes 20. In other words, the preliminary opening 310 is located between two adjacent lower electrodes 20.

[0067] Step S6: Figure 13 and Figure 14 As shown, the sacrificial layer is removed.

[0068] Specifically, such as Figure 13 and Figure 14 As shown, through the above-mentioned preliminary opening, the sacrificial layer and a portion of the first supporting layer 34 located on the first sacrificial layer are removed by etching. Since the preliminary opening can expose a large area of ​​the sacrificial layer, it is beneficial for the entry of the etchant to improve the etching efficiency of the sacrificial layer and to the uniformity of the removal of the sacrificial layer.

[0069] Step S7: Figure 5 As shown, a dielectric layer 40 is formed to cover the surface of the lower electrode 20 and the surface of the support layer 30; an upper electrode 50 is formed to cover the surface of the dielectric layer 40; wherein, part of the upper electrode 50 is filled between two adjacent lower electrodes 20, part of the upper electrode 50 is filled in the dielectric layer 40, and part of the upper electrode 50 protrudes from the lower electrode 20, so as to flatten the surface of the semiconductor device.

[0070] It should be noted that Figures 9 to 14 All structures not mentioned in the description are Figures 5 to 8 The description is consistent with that in , so it will not be repeated here.

[0071] From the above description, it can be seen that the above embodiments of the present application achieve the following technical effects:

[0072] In the semiconductor device of the present invention, each row of openings comprises a plurality of openings, each having a spacer between them. The openings in adjacent rows are staggered, reducing the distribution of the openings and increasing the support force of the bottom electrode, thereby improving the stability of the semiconductor device. This solves the problem of the bottom electrode of semiconductor devices in the related art being prone to collapse.

[0073] It should also be noted that the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, commodity, or apparatus that includes a series of elements includes not only those elements but also other elements not explicitly listed, or includes elements inherent to such process, method, commodity, or apparatus. In the absence of further limitations, an element defined by the phrase "comprises a ..." does not exclude the presence of other identical elements in the process, method, commodity, or apparatus that includes the element.

[0074] The above are merely embodiments of the present application and are not intended to limit the present application. For those skilled in the art, the present application may have various changes and variations. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application should all be included within the scope of the claims of the present application.

Claims

1. A semiconductor device, characterized in that: include: substrate; A plurality of lower electrodes are located on one side surface of the substrate; a supporting layer directly contacting sidewalls of the plurality of lower electrodes, the supporting layer further comprising a plurality of openings and spacers; Parts of the openings are connected to each other through the lower electrode to form opening portions, and the opening portions are staggered and arranged into multiple rows along the first direction, and the opening portions in the same row are isolated from each other by the spacers.

2. The semiconductor device according to claim 1, wherein A hexagon is formed with the spacer as the center, and the six openings closest to the spacer are located at endpoints of the hexagon.

3. The semiconductor device according to claim 2, wherein The endpoints of the hexagon are located at the center of the opening.

4. The semiconductor device according to claim 2, wherein The distance from the center of the spacer to any endpoint of the hexagon is equal to the distance between any two adjacent endpoints of the hexagon.

5. The semiconductor device according to claim 2, wherein The hexagon is approximately a regular hexagon. The semiconductor device according to claim 1 , wherein: The openings in any two adjacent rows in the first direction are staggered.

7. The semiconductor device according to claim 1, wherein The opening portion consists of at least two openings.

8. The semiconductor device according to claim 1, wherein The semiconductor device further includes a dielectric layer, which covers the lower electrode and the exposed surface of the support layer.

9. The semiconductor device according to claim 8, wherein The semiconductor device further includes an upper electrode layer, wherein the upper electrode covers the dielectric layer, and a portion of the upper electrode is located between any two adjacent lower electrodes.

10. The semiconductor device according to claim 1, wherein The shape of the lower electrode includes at least one of the following: a cylindrical shape and a columnar shape.

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