Data processing system and data acceleration equipment

Abstract

The utility model provides a data processing system and data acceleration equipment. The data processing system comprises a to-be-accelerated server, data source equipment and the data acceleration equipment which are separately arranged, the data acceleration device is connected with the data source device and the to-be-accelerated server; the data source equipment is used for sending to-be-processed data to the data acceleration equipment; the data acceleration equipment is used for performing acceleration parallel processing on the received to-be-processed data to obtain processed data; the to-be-accelerated server is used for accessing or storing the processed data obtained by the data acceleration equipment, so that the data acceleration equipment is independent of the to-be-accelerated server, the heat dissipation requirement of the server is reduced, and the installation space of the server is increased.

Description

Technical Field

[0001] The present application relates to the field of data center technology, and in particular to a data processing system and a data acceleration device. Background Art

[0002] With the rapid development of data centers in recent years, communication and computing capabilities have become two key development directions in data center infrastructure. With the increase in network transmission bandwidth, data center computing resources are increasingly occupied by increasingly complex network, storage, security, and other infrastructure operations. Furthermore, with the advent of the post-Moore era, CPU computing power has reached a bottleneck. As a result, data centers are unable to provide more computing resources to customers, significantly reducing resource utilization and revenue.

[0003] Therefore, data centers generally accelerate computing resources through acceleration modules. Currently, the acceleration modules of data centers generally exist in the form of PCIE cards, which are installed on the PCIE standard slot of the rack server motherboard as a coprocessor of the host CPU. However, this method of inserting the PCIE card into the host motherboard places stringent requirements on the server's heat dissipation conditions and occupies installation space within the server. Utility Model Content

[0004] The purpose of the embodiments of the present application is to provide a data processing system and a data acceleration device to solve the problem that the acceleration module of the current data center server uses a PCIE card to be inserted into the host motherboard, which has strict requirements on the heat dissipation conditions of the server and occupies the installation space in the server.

[0005] In a first aspect, the utility model provides a data processing system, which includes a separately arranged server to be accelerated, a data source device, and a data acceleration device; the data acceleration device is respectively connected to the data source device and the server to be accelerated; the data source device is used to send data to be processed to the data acceleration device; the data acceleration device is used to accelerate and parallel process the received data to be processed to obtain processed data; the server to be accelerated is used to access or store the processed data obtained by the data acceleration device.

[0006] The data processing system designed above, this solution makes the data acceleration device independent of the server to be accelerated by designing separately set servers, data source devices and data acceleration devices, thereby solving the problem of stringent requirements on the heat dissipation conditions of the server and occupying the installation space in the server, reducing the heat dissipation requirements of the server and increasing the installation space of the server.

[0007] In an optional implementation manner of the first aspect, the server to be accelerated includes any one of a host server, a storage server, or a GPU server.

[0008] In an optional implementation of the first aspect, the data acceleration device includes a data processing component, a switching component, and a control component; the data source device is connected to the data processing component, the data processing component is connected to the server to be accelerated through the switching component, and the control component is connected to the data processing component and the switching component, respectively; the data processing component is used to perform parallel acceleration processing on the received data to be processed; the control component is used to send a first configuration signal to the data processing component and to send a second configuration signal to the switching component; wherein the first configuration signal is used to configure the data flow between the data processing component and the switching component, and the second configuration signal is used to configure the data flow between the switching component and the server to be accelerated.

[0009] In the above implementation mode, the data acceleration device designed by this solution can adopt different data flow configurations based on different application scenarios, so that the designed data acceleration device can not only serve as a node to assist the processor to be accelerated (host server) in computing, but also serve as an acceleration management node for storage servers or GPU servers, thereby improving the applicability of the data acceleration device. Furthermore, when deploying the data processing system, the acceleration nodes in different scenarios can be deployed using the acceleration device designed by this solution, thereby improving the deployment efficiency of the data processing system.

[0010] In an optional implementation of the first aspect, the switching component includes a PCIe switching chip and a server connection port; the PCIe switching chip includes a first switching port, a second switching port and a switching control port; the PCIe switching chip is electrically connected to the data processing component through the first connection port, the PCIe switching chip is connected to the server connection port through the second connection port, the server connection port is connected to the server to be accelerated, and the control component is connected to the PCIe switching chip through the switching control port; the control component is specifically used to send a second configuration signal to the PCIe switching chip through the switching control port.

[0011] In the above implementation mode, the present solution designs a switching component consisting of a PCIe switching chip and a server connection port, so that multiple devices can be connected to the server to be accelerated through a single PCIe bus, thereby expanding the connectivity of the system. In addition, more devices can be connected without adding physical connection lines, thereby improving the flexibility and scalability of the system.

[0012] In an optional implementation of the first aspect, the data processing component includes an FPGA chip and a configuration storage unit; the FPGA chip includes a first connection port, a second connection port, a third connection port and a configuration control port; the FPGA chip is connected to the first connection port of the PCIe switch chip through the first connection port, the second connection port of the FPGA chip is used to receive data to be processed, the FPGA chip is connected to the configuration storage unit through the configuration control port, the FPGA chip is connected to the control component through the third connection port, and the control component is connected to the configuration storage unit; the control component is used to send a first configuration signal to the configuration storage unit; the configuration storage unit is used to load the stored configuration file into the FPGA chip in response to the first configuration signal to configure the data flow direction of the first connection port of the FPGA chip.

[0013] In the above implementation mode, this solution realizes the composition and function of the data processing component through the FPGA chip and the configuration storage unit, thereby utilizing the parallel working mode of the FPGA chip to realize parallel accelerated processing of the data to be processed, thereby improving the speed and efficiency of data processing.

[0014] In an optional implementation of the first aspect, the configuration storage unit includes a configuration memory and a multiplexer; the configuration control port of the FPGA chip is connected to the configuration memory through the multiplexer, and the control component is connected to the configuration memory through the multiplexer; the control component is specifically used to send a first configuration signal to the multiplexer; the multiplexer is used to switch the configuration memory path of the FPGA chip to the control component in response to the first configuration signal; the configuration memory is specifically used to load the stored configuration file into the FPGA chip after the path switching is completed.

[0015] In the above implementation mode, this solution implements the online configuration of the firmware of the FPGA chip by configuring the memory and the multiplexer, thereby improving the efficiency of the FPGA configuration.

[0016] In an optional implementation of the first aspect, the data processing component also includes a network connection unit; the second connection port of the FPGA chip is connected to the data source device through the network connection unit; the network connection unit is used to receive the data to be processed sent by the data source device and transmit the data to be processed to the FPGA chip.

[0017] In the above implementation mode, the present solution designs the FPGA chip to be connected to the data source device through the network connection unit, thereby improving the data transmission efficiency sent by the data source device to the FPGA chip.

[0018] In an optional implementation of the first aspect, the control component includes a CPU and a network card; the CPU is connected to the switching control port of the PCIe switching chip, the CPU is connected to the third connection port of the FPGA chip, the CPU is connected to the configuration memory through a multiplexer, and the CPU is connected to the network card.

[0019] In an optional implementation of the first aspect, the data processing system also includes a management device; the management device is connected to the control component; the management device is used to send a configuration trigger signal to the control component; the control component is used to send a first configuration signal to the data processing component and a second configuration signal to the switching component in response to the configuration trigger signal.

[0020] In the above implementation mode, the management device sends a configuration trigger signal to enable the control component to send a corresponding configuration signal, thereby realizing the management of different configurations of the data acceleration device in different application scenarios, thereby improving the deployment efficiency of the data acceleration device.

[0021] In a second aspect, the present application provides a data acceleration device, which includes a data processing component, a switching component, and a control component; the data processing component is connected to the server to be accelerated through the switching component, and the control component is connected to the data processing component and the switching component respectively; the data processing component is used to accelerate and parallel process the received data to be processed; the control component is used to send a first configuration signal to the data processing component and a second configuration signal to the switching component; wherein the first configuration signal is used to configure the data flow between the data processing component and the switching component, and the second configuration signal is used to configure the data flow between the switching component and the server to be accelerated.

[0022] The data acceleration device designed above is independent of the server to be accelerated, thereby solving the problem of stringent heat dissipation requirements for the server and occupying the installation space within the server, reducing the heat dissipation requirements of the server and increasing the installation space of the server. In addition, the designed data acceleration device can adopt different data flow configurations based on different application scenarios, so that the designed data acceleration device can not only serve as a node to assist the processor to be accelerated (host server) in calculations, but also as an acceleration management node for the storage server or GPU server, thereby improving the applicability of the data acceleration device. Furthermore, when deploying the data processing system, the acceleration nodes in different scenarios can be deployed using the acceleration device designed in this solution, thereby improving the deployment efficiency of the data processing system.

[0023] The above description is only an overview of the technical solution of the present application. In order to more clearly understand the technical means of the present application, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiments of the present application. It should be understood that the following drawings only show some of the embodiments of the present application, and therefore should not be regarded as a limitation to the scope, and for those of ordinary skill in the art, other related drawings can also be obtained without creative labor on the basis of these drawings.

[0025] Figure 1 The first structural schematic diagram of the data processing system provided by the embodiments of the present application is shown in FIG. 1.

[0026] Figure 2 The second structural schematic diagram of the data processing system provided by the embodiments of the present application is shown in FIG. 2.

[0027] Figure 3 The third structural schematic diagram of the data processing system provided by the embodiments of the present application is shown in FIG. 3.

[0028] Figure 4 The fourth structural schematic diagram of the data processing system provided by the embodiments of the present application is shown in FIG. 4.

[0029] Figure 5 The fifth structural schematic diagram of the data processing system provided by the embodiments of the present application is shown in FIG. 5.

[0030] Figure 6 The sixth structural schematic diagram of the data processing system provided by the embodiments of the present application is shown in FIG. 6.

[0031] Figure 7 The seventh structural schematic diagram of the data processing system provided by the embodiments of the present application is shown in FIG. 7.

[0032] Figure 8 The first example diagram of the data processing system provided by the embodiments of the present application is shown in FIG. 8.

[0033] Figure 9 The second example diagram of the data processing system provided by the embodiments of the present application is shown in FIG. 9.

[0034] Figure 10 The third example diagram of the data processing system provided by the embodiments of the present application is shown in FIG. 10.

[0035] Figure 11 The structural schematic diagram of the data acceleration device provided by the embodiments of the present application is shown in FIG. 11.

[0036] Icons: 10-Server to be accelerated; 20-Data source device; 30-Data acceleration device; 310-Data processing component; 3110-FPGA chip; 3120-Configuration storage unit; 31210-Configuration memory; 31220-Multiplexer; 3130-Network connection unit; 320-Switching component; 3210-PCIe switching chip; 3220-Server connection port; 330-Control component; 3310-Network card; 40-Management device. DETAILED DESCRIPTION

[0037] The following embodiments of the technical solution of the present application will be described in detail with reference to the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solution of the present application and are therefore only examples and are not intended to limit the scope of protection of the present application.

[0038] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this application belongs; the terms used herein are only for the purpose of describing specific embodiments and are not intended to limit this application; the terms "including" and "having" and any variations thereof in the specification and claims of this application and the above-mentioned figure descriptions are intended to cover non-exclusive inclusions.

[0039] In the description of the embodiments of this application, the technical terms "first" and "second" are used only to distinguish different objects and should not be understood to indicate or imply relative importance or implicitly specify the quantity, specific order, or primary and secondary relationship of the indicated technical features. In the description of the embodiments of this application, the meaning of "plurality" is more than two, unless otherwise clearly and specifically defined.

[0040] References herein to "embodiments" mean that a particular feature, structure, or characteristic described in connection with the embodiments may be included in at least one embodiment of the present application. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor does it constitute an independent or alternative embodiment that is mutually exclusive of other embodiments. It is understood, both explicitly and implicitly, by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0041] In the description of the embodiments of this application, the term "and / or" is simply a description of the association relationship between associated objects, indicating that three relationships can exist. For example, A and / or B can represent the following three situations: A exists alone, A and B exist simultaneously, and B exists alone. In addition, the character " / " in this document generally indicates that the associated objects are in an "or" relationship.

[0042] In the description of the embodiments of the present application, the term "multiple" refers to more than two (including two). Similarly, "multiple groups" refers to more than two groups (including two groups), and "multiple pieces" refers to more than two pieces (including two pieces).

[0043] In the description of the embodiments of the present application, the technical terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing the embodiments of the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the embodiments of the present application.

[0044] In the description of the embodiments of the present application, unless otherwise expressly specified or limited, technical terms such as "installed," "connected," "connected," and "fixed" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integration; mechanical connections or electrical connections; direct connections or indirect connections through an intermediate medium; internal connections between two components or interactions between two components. Those skilled in the art can understand the specific meanings of the above terms in the embodiments of the present application based on specific circumstances.

[0045] With the rapid development of data centers in recent years, communication and computing capabilities have become two key development directions in data center infrastructure. With the increase in network transmission bandwidth, data center computing resources are increasingly occupied by increasingly complex network, storage, security, and other infrastructure operations. Furthermore, with the advent of the post-Moore era, CPU computing power has reached a bottleneck. As a result, data centers are unable to provide more computing resources to customers, significantly reducing resource utilization and revenue.

[0046] Therefore, data centers generally accelerate computing resources through acceleration modules. Currently, the acceleration modules of data centers generally exist in the form of PCIE cards, which are installed on the PCIE standard slot of the motherboard of the rack server as a coprocessor of the host CPU. However, this method of inserting the PCIE card into the host motherboard has the problem of strict requirements on the heat dissipation conditions of the server and occupies the installation space in the server.

[0047] Based on the above problems, the present application designs a data processing system and a data acceleration device. By designing a separately set server to be accelerated, a data source device and a data acceleration device, the data acceleration device is independent of the server to be accelerated, thereby solving the problem of stringent heat dissipation requirements for the server and occupying the installation space in the server, reducing the heat dissipation requirements of the server and increasing the installation space of the server. At the same time, the data acceleration device designed in this solution can adopt different data flow configurations based on different application scenarios, so that the designed data acceleration device can not only serve as a node to assist the processor to be accelerated (host server) in calculations, but also as an acceleration management node for a storage server or GPU server, thereby improving the applicability of the data acceleration device. Furthermore, when deploying the data processing system, the acceleration nodes in different scenarios can be deployed using the acceleration device designed in this solution, thereby improving the deployment efficiency of the data processing system.

[0048] Based on the above ideas, this application first provides a data processing system, which can also be called a data center, whose function is to transmit, accelerate, display, calculate, and store data information functions on the Internet network infrastructure, such as Figure 1 As shown, the data processing system includes a server to be accelerated 10, a data source device 20, and a data acceleration device 30. In this solution, the server to be accelerated 10, the data source device 20, and the data acceleration device 30 are separately set up, that is, the data acceleration device 30 is an independent device, which is independent of the server to be accelerated 10.

[0049] The server to be accelerated 10 represents a server device in a data center that performs computations or stores data information. For example, the server to be accelerated 10 can be any of a host server, a storage server, and a GPU server. A host server represents a server device in a data center that participates in computing data information; a GPU server also represents a server device in a data center that participates in computing data information. Specifically, a GPU server can participate in complex computations such as deep learning, machine learning, image processing, and big data processing; and a storage server represents a server device in a data center that stores data information.

[0050] The data source device 20 represents a device on the network of the data processing system that is responsible for data transmission. It can transmit data information that needs to be accelerated to the data acceleration device 30. The data acceleration device represents a device that accelerates and parallelizes the data information transmitted by the data source device 20. It can assist the server 10 to be accelerated in data calculation and processing, and can also process the data information transmitted by the data source device 20 and store it in the server 10 to be accelerated.

[0051] When the data processing system of the above design is performing data processing, the data source device 20 can send the data to be processed to the data acceleration device 30. The data acceleration device 30 performs accelerated parallel processing on the data to be processed to obtain the processed data. The server to be accelerated 10 can then access or store the data processed by the data acceleration device 30. For example, to improve the efficiency of data calculation, while the server to be accelerated 10 is performing data calculation, the data source device 20 can transmit a portion of the data to be calculated to the data acceleration device 30, so that the data acceleration device 30 and the server to be accelerated 10 perform data calculation simultaneously, thereby improving the data calculation efficiency. For another example, to improve the efficiency of data storage, the data source device 20 can transmit the data to be stored to the data acceleration device 30. The data acceleration device 30 can perform accelerated parallel processing on the data to be stored, and then store the processed data in the server to be accelerated 10, thereby improving storage efficiency.

[0052] The data processing system designed above, by designing a separately set server to be accelerated, a data source device and a data acceleration device, makes the data acceleration device independent of the server to be accelerated, thereby solving the problem of strict requirements on the heat dissipation conditions of the server and occupying the installation space in the server, reducing the heat dissipation requirements of the server and increasing the installation space of the server.

[0053] In an optional implementation of this embodiment, the server 10 to be accelerated described above can be any one of a host server, a storage server, and a GPU server. As a possible implementation, this solution can use a data acceleration device 30 designed as follows, so that the designed data acceleration device can be adapted to scenarios where the server 10 to be accelerated is a variety of different types of servers.

[0054] Specifically, if Figure 2 As shown, the data acceleration device 30 designed in this solution may include a data processing component 310, a switching component 320 and a control component 330. The data source device 20 is connected to the data processing component 310, the data processing component 310 is connected to the server to be accelerated 10 through the switching component 320, and the control component 330 is connected to the data processing component 310 and the switching component 320 respectively.

[0055] In the data acceleration device 30 designed as described above, the data processing component 310 can receive the data to be processed transmitted by the data source device 20 and perform parallel accelerated processing on the received data to be processed; the control component 330 can send a first configuration signal to the data processing component 310, and the first configuration signal is used to configure the data flow between the data processing component 310 and the switching component 320; the control component 330 is also used to send a second configuration signal to the switching component 320, and the second configuration signal is used to configure the data flow between the switching component 320 and the server 10 to be accelerated.

[0056] Based on the data acceleration device 30 designed above, this solution configures the data flow between the data processing component 310 and the switching component 320, and between the switching component 320 and the server 10 to be accelerated, through configuration signals sent by the control component 330. This makes the designed data acceleration device 30 adaptable to scenarios where the server 10 to be accelerated is a variety of different types of servers.

[0057] For example, if the server to be accelerated 10 is the host server, the first and second configuration signals in this solution configure the data flow as follows: the server to be accelerated 10 is the upstream flow, the switching component 320 is the upstream flow, and the data processing component 310 is the downstream flow. This allows the data processing component 310 to access the processed data obtained by the downstream data processing component 310 through the upstream switching component 320.

[0058] For another example, if the server to be accelerated 10 is a storage server, the first and second configuration signals in this solution configure the data flow as follows: data processing component 310 as the upstream flow, switching component 320 as the downstream flow, and the server to be accelerated as the lowest downstream flow. This way, after data processing component 310 receives processed data, it can transmit the processed data to server 10 for storage via downstream switching component 320.

[0059] In the above implementation mode, the data acceleration device designed by this solution can adopt different data flow configurations based on different application scenarios, so that the designed data acceleration device can not only serve as a node to assist the processor to be accelerated (host server) in computing, but also serve as an acceleration management node for storage servers or GPU servers, thereby improving the applicability of the data acceleration device. Furthermore, when deploying the data processing system, the acceleration nodes in different scenarios can be deployed using the acceleration device designed by this solution, thereby improving the deployment efficiency of the data processing system.

[0060] In an optional implementation of this embodiment, as a possible implementation, the switching component 320 designed in this solution can be specifically implemented by the following design, such as Figure 3 As shown, the switching component 320 includes: a PCIe switching chip 3210 and a server connection port 3220, the PCIe switching chip 3210 includes a first switching port DP, a second switching port UP and a switching control port MG. Figure 3 As can be seen, the PCIe switch chip 3210 is electrically connected to the data processing component 310 through the first connection port DP, the PCIe switch chip 3210 is connected to the server connection port 3220 through the second connection port UP, the server connection port 3220 is connected to the server to be accelerated 10, and the control component 330 is connected to the PCIe switch chip 3210 through the switch control port MG.

[0061] In the above embodiment, the control component 330 can send a second configuration signal to the PCIe switch chip 3210 via the switch control port MG. The PCIe switch chip 3210 configures its own firmware based on the second configuration signal. For example, the PCIe switch chip 3210 can configure the data flow direction of its first connection port DP and second connection port UP. For another example, the PCIe switch chip 3210 can configure its own operating mode. The PCIe switch chip 3210 of this embodiment can specifically be a PCIe Switch chip, but other types of PCIe switch chips can also be used. It only needs to be able to configure the data flow direction of its own connection port based on the configuration signal. The server connection port 3220 can specifically be a Mini SAS HD connection port, but other types of connection ports can also be used, such as a Mini SAS port.

[0062] In the above implementation mode, the present solution designs a switching component consisting of a PCIe switching chip and a server connection port, so that multiple devices can be connected to the server to be accelerated through a single PCIe bus, thereby expanding the connectivity of the system. In addition, more devices can be connected without adding physical connection lines, thereby improving the flexibility and scalability of the system.

[0063] In an optional implementation of this embodiment, if Figure 4As shown, the data processing component 310 designed in this scheme may specifically include an FPGA chip 3110 and a configuration storage unit 3120. The FPGA chip 3110 includes a first connection port ED, a second connection port NIC, a third connection port EP and a configuration control port SPI; the FPGA chip 3110 is connected to the first connection port DP of the PCIe switch chip 3210 through the first connection port ED, the second connection port NIC of the FPGA chip 3110 is connected to the data source device 20, the FPGA chip 3110 is connected to the configuration storage unit 3120 through the configuration control port SPI, the FPGA chip 3110 is connected to the control component 330 through the third connection port EP, and the control component 330 is connected to the configuration storage unit 3120.

[0064] In the implementation of the above-mentioned design, the control component 330 can send a first configuration signal to the configuration storage unit 3120. In response to the first configuration signal, the configuration storage unit 3120 loads the stored configuration file into the FPGA chip 3110, thereby configuring the firmware of the FPGA chip 3110. For example, the data flow direction of the first connection port ED of the FPGA chip 3110 can be configured.

[0065] In the above implementation mode, this solution realizes the composition and function of the data processing component through the FPGA chip and the configuration storage unit, thereby utilizing the parallel working mode of the FPGA chip to realize the parallel accelerated processing of the data to be processed, thereby improving the speed and efficiency of data processing.

[0066] Specifically, if Figure 5 As shown, the configuration storage unit 3120 designed in this scheme may include a configuration memory 31210 and a multiplexer 31220. The configuration control port SPI of the FPGA chip 3110 is connected to the configuration memory 31210 through the multiplexer 31220, and the control component 330 is connected to the configuration memory 31210 through the multiplexer 31220.

[0067] In the implementation mode of the above-mentioned design, the control component 330 can specifically send a first configuration signal to the multiplexer 31220; the multiplexer 31220 switches the path of the configuration memory 31210 of the FPGA chip to the control component 330 in response to the first configuration signal; after the path switching is completed, the configuration memory 31210 loads the stored configuration file into the FPGA chip 3110, thereby realizing the configuration of the FPGA chip firmware.

[0068] In the above implementation mode, this solution implements the online configuration of the firmware of the FPGA chip by configuring the memory and the multiplexer, thereby improving the efficiency of the FPGA configuration.

[0069] In an optional implementation of this embodiment, ifFigure 6 As shown, the data processing component 310 designed in this solution may further include a network connection unit 3130. The second connection port NIC of the FPGA chip 3110 is connected to the data source device 20 via the network connection unit 3130. In this way, the FPGA chip 3110 can receive the to-be-processed data transmitted by the data source device 20 via the network connection unit 3130. Specifically, the network connection unit 3130 designed in this solution may adopt any type of current network interface, such as a QSFP56 optical module or other types of optical fiber interfaces.

[0070] In the above implementation mode, the present solution designs the FPGA chip to be connected to the data source device through the network connection unit, thereby improving the data transmission efficiency sent by the data source device to the FPGA chip.

[0071] In an optional implementation of this embodiment, if Figure 7 As shown, the control component 330 designed in this scheme may include a CPU and a network card 3310; the CPU is connected to the switching control port MG of the PCIe switching chip 3210, the CPU is connected to the third connection port EP of the FPGA chip 3110, the CPU is connected to the configuration memory 31210 through the multiplexer 31220, and the CPU is connected to the network card 3310.

[0072] The CPU designed in this solution can be implemented using a general-purpose processor core, such as an ARM or X86 core, and specifically a high-performance X86 CPU. The network card 3310 designed in this solution can specifically use an I210 network card to implement a Gigabit Ethernet port, thereby improving data transmission efficiency.

[0073] In an optional implementation of this embodiment, if Figure 7 As shown, the data processing system designed in this solution may also include a management device 40, which is connected to the control component 330. Specifically, the management device 40 may be connected to the CPU of the control component 330 via a network card 3310.

[0074] In the implementation of the above design, the management device 40 can send a configuration trigger signal to the control component 330. In response to the configuration trigger signal, the control component 330 sends a first configuration signal to the data processing component 310 and a second configuration signal to the switch component 320. Different configuration trigger signals can cause the control component to send different configuration signals. For example, assuming the configuration trigger signal is signal N00 corresponding to the coprocessor scenario, in this case, the control component 330 sends a first configuration signal N1 to the data processing component 310 and a second configuration signal N2 to the switch component 320, so that the server to be accelerated 10 is the most upstream flow, the switch component 320 is the upstream flow, and the data processing component 310 is the downstream flow. Assuming the configuration trigger signal is signal N01 corresponding to the storage acceleration node scenario, the control component 330 sends a first configuration signal N3 to the data processing component 310 and a second configuration signal N4 to the switch component 320, so that the data processing component 310 is the upstream flow, the switch component 320 is the downstream flow, and the server to be accelerated is the most downstream flow. In this way, different configuration signals corresponding to different trigger signals can achieve management configuration for different scenarios. It should be noted here that the correspondence between the trigger signal of each scenario and the corresponding configuration signal can be stored in the control component in advance. The control component only needs to compare the trigger signal with the information in the register to issue the corresponding configuration signal.

[0075] In the above implementation mode, the management device sends a configuration trigger signal to enable the control component to send a corresponding configuration signal, thereby realizing the management of different configurations of the data acceleration device in different application scenarios, thereby improving the deployment efficiency of the data acceleration device.

[0076] This solution uses the following examples to specifically illustrate the above solution. Before that, it should be noted that the following examples are only for facilitating the understanding of this solution, and the content of the examples cannot be used as a limitation of this solution. The examples are as follows:

[0077] like Figure 8 As shown, the control component 330 designed in this solution specifically adopts an X86 CPU, and the network card 3310 adopts an I210 network card. The X86 CPU is connected to the management device 40 through the network card 3310.

[0078] The designed data processing component 310 adopts an FPGA chip, a multiplexer MUX and a configuration memory SPIFlash. The designed switching component 320 adopts a PICE Switch chip. The PICE Switch chip includes 7 interfaces, 6 of which are configured as PICE X16. The first switching port of the PICE Switch chip includes two PICE X16 interfaces. The first connection port of the FPGA chip includes two PCIE X16 interfaces. The first switching port of the PICE Switch chip is connected to the first connection port of the FPGA chip. The second switching interface of the PICE Switch chip includes 4 PICE X16 interfaces, which are respectively connected to the miniSAS interface and connected to the server to be accelerated 10. The switching configuration port MG of the PICE Switch chip is connected to the CPU.

[0079] The second connection port of the FPGA chip includes two network interfaces, namely NIC0 and NIC1. The two network interfaces NIC0 and NIC1 are respectively connected to the QSFP56 optical module and then connected to the data source device 20; the third connection port EP of the FPGA chip is a PCIE X8 interface. The third connection port EP is connected to the CPU, the configuration control port SPI of the FPGA chip is connected to the multiplexer MUX, the SPI interface of the CPU is also connected to the multiplexer MUX, and the multiplexer MUX is connected to the configuration memory SPIFlash.

[0080] The structure of the above example is as follows Figure 9As shown, in the case where the server 10 to be accelerated connected by the four miniSAS interfaces is a host server, that is, the data acceleration device is a coprocessor scenario, the management device 40 can send a configuration trigger signal N00 to the CPU, and the CPU sends a first configuration signal N1 to the MUX based on the configuration trigger signal N00, controls the select signal of the MUX to cut the path of the configuration memory SPI Flash to the CPU, and then configures the memory SPI Flash to load the stored configuration file into the FGPA chip, so that the FPGA chip is connected to the first connection ports ED0 and ED1 of the PCIE Switch chip and is configured as a downstream slave device. The CPU also sends a second configuration signal N2 to the PCIE Switch chip through the switching configuration port MG of the PICE Switch chip to configure the PCIE Switch chip to fabric mode. In fabric mode, the first switching port and the second switching port of the PCIE Switch chip can access each other, the two first switching ports DP0 and DP1 connected to the FPGA chip are configured as downstream, and the four interfaces connected to the miniSAS HD connector are configured as upstream. In this way, the upstream interface of the PCIE Switch chip is connected to four host servers HOST, and the two downstream interfaces are connected to the FPGA chip, so that the four host servers can access each other, and can also access the FPGA chip through any downstream interface, and then access the data processed by the FPGA chip and communicate with the external network.

[0081] The structure of the above example is as follows Figure 10As shown, in the case where the server 10 to be accelerated connected to the four miniSAS interfaces is a storage server, that is, the data acceleration device serves as a management acceleration node scenario of the storage system, the management device 40 can issue a configuration trigger signal N01 to the CPU. Based on the configuration trigger signal N01, the CPU sends a first configuration signal N3 to the MUX, controls the select signal of the MUX to cut the path of the configuration memory SPI Flash to the CPU, and then configures the memory SPI Flash to load the stored configuration file into the FGPA chip, so that the FPGA chip is connected to the two first connection ports RC0 and RC1 of the PCIE Switch chip and is configured as an upstream master device. The CPU also sends a second configuration signal N4 to the PCIE Switch chip through the switching configuration port MG of the PICE Switch chip to configure the PCIE Switch chip to base mode. In base mode, the two first switching ports of the PCIE switch chip connected to the FPGA chip are in upstream mode, which are UP0 and UP1 respectively, and the four interfaces connected to the miniSAS HD connector are configured as downstream, which are DP0, DP1, DP2 and DP3 respectively. In this way, the two upstream interfaces of the PCI E Switch chip are connected to the FPGA chip to provide sufficient access bandwidth, and the four downstream interfaces are connected to the storage server, so that the data processed by the FPGA chip can be stored in the storage server.

[0082] This application also provides a data acceleration device, such as Figure 11 As shown, the data acceleration device includes the data processing component 310, the switching component 320 and the control component 330 described above. The specific structure, connection relationship and function of the data acceleration device have been described above and will not be repeated here.

[0083] The data acceleration device designed above is independent of the server to be accelerated, thereby solving the problem of stringent heat dissipation requirements for the server and occupying the installation space within the server, reducing the heat dissipation requirements of the server and increasing the installation space of the server. In addition, the designed data acceleration device can adopt different data flow configurations based on different application scenarios, so that the designed data acceleration device can not only serve as a node to assist the processor to be accelerated (host server) in calculations, but also as an acceleration management node for the storage server or GPU server, thereby improving the applicability of the data acceleration device. Furthermore, when deploying the data processing system, the acceleration nodes in different scenarios can be deployed using the acceleration device designed in this solution, thereby improving the deployment efficiency of the data processing system.

[0084] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some or all of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present application, and they should all be included in the scope of the claims and specification of the present application. In particular, as long as there is no structural conflict, the various technical features mentioned in the various embodiments can be combined in any way. The present application is not limited to the specific embodiments disclosed herein, but includes all technical solutions that fall within the scope of the claims.

Claims

1. A data processing system, characterized in that: The data processing system includes a server to be accelerated, a data source device, and a data acceleration device that are separately arranged; the data acceleration device is connected to the data source device and the server to be accelerated respectively; The data source device is used to send the data to be processed to the data acceleration device; The data acceleration device is used to accelerate and parallelize the received data to be processed to obtain processed data; The server to be accelerated is used to access or store the processed data obtained by the data acceleration device.

2. The data processing system according to claim 1, wherein: The server to be accelerated includes any one of a host server, a storage server or a GPU server.

3. The data processing system according to claim 1, wherein: The data acceleration device includes a data processing component, a switching component, and a control component; the data source device is connected to the data processing component, the data processing component is connected to the server to be accelerated through the switching component, and the control component is connected to the data processing component and the switching component respectively; The data processing component is used to perform parallel accelerated processing on the received data to be processed; The control component is used to send a first configuration signal to the data processing component and a second configuration signal to the switching component; wherein the first configuration signal is used to configure the data flow between the data processing component and the switching component, and the second configuration signal is used to configure the data flow between the switching component and the server to be accelerated.

4. The data processing system according to claim 3, wherein: The switching component includes a PCIe switching chip and a server connection port; The PCIe switch chip includes a first switch port, a second switch port and a switch control port; The PCIe switch chip is electrically connected to the data processing component via a first connection port, the PCIe switch chip is connected to the server connection port via a second connection port, the server connection port is connected to the server to be accelerated, and the control component is connected to the PCIe switch chip via the switch control port; The control component is specifically configured to send the second configuration signal to the PCIe switch chip through the switch control port.

5. The data processing system according to claim 4, wherein: The data processing component includes an FPGA chip and a configuration storage unit; The FPGA chip includes a first connection port, a second connection port, a third connection port, and a configuration control port; the FPGA chip is connected to the first connection port of the PCIe switch chip via the first connection port, the second connection port of the FPGA chip is connected to the data source device, the FPGA chip is connected to the configuration storage unit via the configuration control port, the FPGA chip is connected to the control component via the third connection port, and the control component is connected to the configuration storage unit; The control component is configured to send a first configuration signal to the configuration storage unit; The configuration storage unit is used to load the stored configuration file into the FPGA chip in response to the first configuration signal, so as to configure the data flow direction of the first port of the FPGA chip.

6. The data processing system according to claim 5, characterized in that The configuration storage unit includes a configuration memory and a multiplexer; The configuration control port of the FPGA chip is connected to the configuration memory through the multiplexer, and the control component is connected to the configuration memory through the multiplexer; The control component is specifically configured to send the first configuration signal to the multiplexer; The multiplexer is configured to switch a configuration memory path of the FPGA chip to the control component in response to the first configuration signal; The configuration memory is used to load the stored configuration file into the FPGA chip after the path switching is completed.

7. The data processing system according to claim 5, wherein: The data processing component further includes a network connection unit; the second connection port of the FPGA chip is connected to the data source device via the network connection unit; The network connection unit is used to receive the data to be processed sent by the data source device and transmit the data to be processed to the FPGA chip.

8. The data processing system according to claim 6, wherein: The control component includes a CPU and a network card; The CPU is connected to the switching control port of the PCIe switching chip, the CPU is connected to the third connection port of the FPGA chip, the CPU is connected to the configuration memory through the multiplexer, and the CPU is connected to the network card.

9. The data processing system according to claim 3, wherein: The data processing system further includes a management device; the management device is connected to the control component; The management device is used to send a configuration trigger signal to the control component; The control component is configured to send a first configuration signal to the data processing component and a second configuration signal to the switching component in response to the configuration trigger signal.

10. A data acceleration device, characterized in that: The data acceleration device includes a data processing component, a switching component, and a control component; the data processing component is connected to the server to be accelerated through the switching component, and the control component is connected to the data processing component and the switching component respectively; The data processing component is used to accelerate and parallelize the received data to be processed; The control component is used to send a first configuration signal to the data processing component and a second configuration signal to the switching component; wherein the first configuration signal is used to configure the data flow between the data processing component and the switching component, and the second configuration signal is used to configure the data flow between the switching component and the server to be accelerated.

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