Semiconductor device

Abstract

The utility model relates to a semiconductor device which comprises a semiconductor substrate, a plurality of gate structures are formed on the semiconductor substrate, the semiconductor device further comprises a dielectric layer covering the gate structures and the semiconductor substrate, and contact holes are formed in the dielectric layer and located between the adjacent gate structures. The contact hole comprises an upper section, a middle section and a lower section which are sequentially arranged from top to bottom, and the average width of the lower section is larger than the average width of the middle section and smaller than the average width of the upper section. Thus, by enlarging the width of the lower section, the cross sectional area of the conductive plug of the lower section can be increased, the bottom contact area can be increased, the resistance value of the conductive plug formed in the contact hole is small, and the performance of the whole semiconductor device is improved.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of semiconductor, in particular, to a semiconductor device. BACKGROUND

[0002] At present, in order to realize the conduction between different metal layers of a semiconductor device, a groove is usually formed in a dielectric layer between two metal layers and filled with conductive material (such as tungsten) to form a contact hole (CT) structure for conducting the two metal layers. The contact hole process leads out various electrodes of various devices on a substrate to the dielectric layer, and uses multi-layer metal interconnection to lead out the electrodes of an integrated circuit, so as to facilitate subsequent packaging. The formation quality of the above semiconductor device greatly affects the performance of the circuit. If the formation quality of the contact hole is poor, the overall resistance value of the circuit will rise, and in severe cases, the device will not work normally.

[0003] In the related art, the bottom contact area of the contact hole is small, which leads to a high overall resistance value of the circuit, and thus affects the yield of the device to some extent. CONTENT OF THE UTILITY MODEL

[0004] The purpose of the present disclosure is to provide a semiconductor device to at least partially solve the problems existing in the related art.

[0005] In order to achieve the above purpose, the present disclosure provides a semiconductor device, comprising a semiconductor substrate, a plurality of gate structures are formed on the semiconductor substrate, the semiconductor device further comprises a dielectric layer covering the gate structures and the semiconductor substrate, a contact hole is formed between adjacent gate structures on the dielectric layer, the contact hole comprises an upper section, a middle section and a lower section arranged in order from top to bottom, wherein the average width of the lower section is greater than the average width of the middle section and less than the average width of the upper section.

[0006] Optionally, the width of the lower section gradually increases from top to bottom.

[0007] Optionally, the sidewall of the lower section is configured in an arc shape.

[0008] Optionally, the sidewall of the lower section is arranged in an inclined manner.

[0009] Optionally, the sidewall of the middle section is arranged in an inclined manner, and the width of the middle section gradually decreases from top to bottom.

[0010] Optionally, the sidewall of the upper section is arranged in an inclined manner, and the width of the upper section gradually decreases from top to bottom, and the slope of the sidewall of the upper section is less than or equal to the slope of the sidewall of the middle section.

[0011] Optionally, the sidewall of the lower section is arranged in an inclined manner, and the slope of the sidewall of the lower section is smaller than the slope of the sidewall of the middle section and larger than the slope of the sidewall of the upper section.

[0012] Optionally, the upper section, the middle section and the lower section have the same depth.

[0013] Optionally, the sidewall of the gate structure forms at least one sidewall.

[0014] Optionally, the thickness of the sidewall gradually increases from top to bottom.

[0015] By the above technical solution, by expanding the width of the lower section, the cross-sectional area of the conductive plug in the lower section can be increased, the bottom contact area can be increased, and thus the resistance of the conductive plug formed in the contact hole is small, and the performance of the entire semiconductor device is improved.

[0016] Other features and advantages of the present disclosure will be described in detail in the following detailed description. BRIEF DESCRIPTION OF DRAWINGS

[0017] The accompanying drawings are included to provide a further understanding of the present disclosure and constitute a part of the specification, and are used together with the following detailed description to explain the present disclosure, but do not constitute a limitation of the present disclosure. In the drawings:

[0018] Figure 1 is a structural schematic diagram of a contact hole in the prior art;

[0019] Figure 2 is a structural schematic diagram of a contact hole provided by an exemplary embodiment of the present disclosure;

[0020] Figure 3 is a structural schematic diagram of a semiconductor device provided by an exemplary embodiment of the present disclosure.

[0021] REFERENCE NUMERALS

[0022] 1 - semiconductor substrate; 2 - gate structure; 201 - gate body; 202 - gate metal silicide layer; 21 - sidewall; 3 - dielectric layer; 4 - contact hole; 41 - upper section; 42 - middle section; 43 - lower section DETAILED DESCRIPTION

[0023] The detailed description of the specific embodiments of the present disclosure will be described below in conjunction with the accompanying drawings. It should be understood that the specific embodiments described herein are only used to illustrate and explain the present disclosure, and are not used to limit the present disclosure.

[0024] In the present disclosure, the orientation words "upper", "middle", "lower" are defined based on the actual direction of use of the relevant components, unless otherwise stated. "Inner", "outer" are relative to the contour of the respective component itself. In the present disclosure, the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements.

[0025] In the related art, as shown in Figure 1 The contact hole presents an upper wide and lower narrow structure, which will make the bottom contact area of the contact hole smaller, resulting in the overall resistance of the circuit being too high, which will affect the yield of the semiconductor device to some extent.

[0026] Referring to Figure 3 The present disclosure provides a semiconductor device, which can include a semiconductor substrate 1, the material of the semiconductor substrate 1 can be monocrystalline silicon, polycrystalline silicon, silicon-on-insulator or germanium-silicon compound, etc. A plurality of gate structures 2 are formed on the semiconductor substrate 1, the gate structure 2 can include a gate body 201 and a gate metal silicide layer 202 on the gate body 201 to improve the electrical connection performance between the gate structure 2 and the conductive structure. The material of the gate 201 can be polycrystalline silicon, which can be formed by a chemical vapor deposition process or a physical vapor deposition process, wherein polycrystalline silicon is a kind of semiconductor material, which has the characteristics of very high conductivity and stability, and is easy to manufacture and finished. Therefore, polycrystalline silicon is widely used as a gate material in semiconductor devices. The semiconductor device can also include a dielectric layer 3 covering the gate structure 2 and the semiconductor substrate 1, a contact hole 4 is formed between adjacent gate structures 2 on the dielectric layer 3, and the contact hole 4 is formed by etching the dielectric layer 3. The metal in the contact hole 4 is filled to form a conductive plug, and the material of the conductive plug can be tungsten, copper, etc. The contact hole 4 can include an upper segment 41, a middle segment 42 and a lower segment 43 arranged in order from top to bottom, wherein the average width of the lower segment 43 is greater than the average width of the middle segment 42 and less than the average width of the upper segment 41.

[0027] Through the above technical solution, by expanding the width of the lower segment, the cross-sectional area of the lower segment conductive plug can be increased, the bottom contact area is increased, so that the conductive plug formed in the contact hole has a smaller resistance, and the performance of the entire semiconductor device is improved.

[0028] In some embodiments, referring to Figure 2, the lower section 43 can gradually increase in width from top to bottom. Such arrangement increases the width of the bottom end of the lower section 43, which facilitates the filling of metal and increases the bottom contact area, reduces the resistance, and improves the performance of the semiconductor device. In addition, the gradual increase in width of the lower section 43 from top to bottom makes the connection between the lower section 43 and the middle section 42 have a smooth transition, avoiding the sudden large-scale expansion of the width of the lower section 43 near the middle section 42, which is prone to form voids during the filling of metal, resulting in a decrease in yield.

[0029] As an exemplary embodiment of the present disclosure, referring to Figure 2 , the side wall of the lower section 43 can be arc-shaped, which makes the transition between the lower section 43 and the middle section 42 smoother, facilitating the filling of metal and improving product yield.

[0030] As another exemplary embodiment of the present disclosure, the side wall of the lower section 43 can be arranged in an inclined manner, i.e., the side wall of the lower section 43 is arranged in a straight line. The present disclosure does not make specific limitations on the structural form of the lower section 43, as long as its average width is greater than that of the middle section 42.

[0031] As an exemplary embodiment of the present disclosure, referring to Figure 2 , the side wall of the middle section 42 can be arranged in an inclined manner, and the width of the middle section 42 gradually decreases from top to bottom. Such arrangement facilitates the filling of metal, and the bottom end of the middle section 42 is close to the upper part of the side wall 21 of the gate structure 2, so the bottom end of the middle section 42 should not be too wide to avoid interference with the upper part of the side wall 21, affecting the etching process. If the middle section 42 is made too wide, the alignment window of photolithography becomes smaller, because photolithography needs to accurately expose the contact hole between the two adjacent gate structures 2. When the width of the middle section 42 increases, the deviation of photolithography needs to be controlled more accurately, and the process requirement is high. Moreover, if the gate structure 2 is made larger, the distance between the two gate structures 2 will be smaller, and at this time, the middle section 42 of the contact hole 4 has no space to increase. Therefore, the width of the middle section 42 needs to be appropriate and should not be too wide. In other embodiments, the side wall of the middle section 42 can also be arranged in a straight line vertically.

[0032] Further, referring to Figure 2 , the side wall of the upper section 41 can be arranged in an inclined manner, and the width of the upper section 41 gradually decreases from top to bottom. The slope of the side wall of the upper section 41 is less than or equal to the slope of the side wall of the middle section 42. Such arrangement can expand the top opening of the upper section 41, which is beneficial for the filling of metal.

[0033] Further, the side wall of the lower section 43 can be arranged in an inclined manner, and the slope of the side wall of the lower section 43 is less than the slope of the side wall of the middle section 42 and greater than the slope of the side wall of the upper section 41. Appropriately expanding the width of the lower section 43 is beneficial for reducing the resistance of metal, but the width of the lower section 43 cannot be expanded indefinitely to avoid affecting the two gate structures 2 on both sides.

[0034] In some embodiments, referring to Figure 2 The depth of the upper section 41, the middle section 42 and the lower section 43 can be the same. The present disclosure does not limit the depth of the upper section 41, the middle section 42 and the lower section 43, which can be adjusted according to actual needs.

[0035] According to an exemplary embodiment of the present disclosure, referring to Figure 3 The side of the gate structure 2 can form at least one side wall 21. Specifically, the side wall 21 can cover the gate structure 2 and the top of the semiconductor substrate 1. The side wall 21 can be a single-layer structure or a multi-layer stacked structure. In the embodiments of the present disclosure, the side wall 21 is a double-layer stacked structure, which can include a silicon oxide layer and a silicon nitride layer covering the silicon oxide layer. As the size of semiconductor devices continues to shrink, hot carrier effects become an important factor restricting the reliability and performance of devices. By forming a side wall 21 on both sides of the gate structure 2, hot carriers can be effectively prevented from directly entering the gate structure 2 or the semiconductor substrate 1, thereby improving the reliability and performance of the device, while also reducing power consumption and noise.

[0036] Further, the thickness of the side wall 21 can gradually increase from top to bottom. In the prior art, the resistance is usually reduced by increasing the middle section 42 and then increasing the lower section 43, that is, the contact hole 4 is widened as a whole, but due to the structure of the side wall 21 being thicker at the bottom and narrower at the top, widening the middle section 42 can easily interfere with the thinner side wall 21 at the top during etching and cannot be etched, while the bottom end of the side wall 21 is thicker, so even if interference occurs during etching, it will not be affected. Therefore, without changing the width of the middle section 42, the width of the lower section 43 can be increased to achieve the effect of reducing resistance.

[0037] The preferred embodiments of the present disclosure are described in detail above with reference to the accompanying drawings, but the present disclosure is not limited to the specific details in the above-described embodiments. Within the technical concept of the present disclosure, various simple modifications can be made to the technical solutions of the present disclosure, and these simple modifications all belong to the protection scope of the present disclosure.

[0038] In addition, it should be noted that each specific technical feature described in the above specific embodiments can be combined in any appropriate manner without contradiction. In order to avoid unnecessary repetition, the present disclosure will not further describe various possible combinations.

[0039] In addition, various different embodiments of the present disclosure can also be combined in any appropriate manner, as long as they do not deviate from the idea of the present disclosure, and they should also be considered as disclosed by the present disclosure.

Claims

1. A semiconductor device, characterized in that: The invention comprises a semiconductor substrate on which a plurality of gate structures are formed, and the semiconductor device further comprises a dielectric layer covering the gate structures and the semiconductor substrate, wherein contact holes are formed on the dielectric layer between adjacent gate structures, and the contact holes comprise an upper section, a middle section, and a lower section arranged in sequence from top to bottom, wherein the average width of the lower section is greater than the average width of the middle section and less than the average width of the upper section.

2. The semiconductor device according to claim 1, wherein The width of the lower section gradually increases from top to bottom.

3. The semiconductor device according to claim 2, wherein The side wall of the lower section is configured in an arc shape.

4. The semiconductor device according to claim 2, wherein The side walls of the lower section are arranged in an inclined manner.

5. The semiconductor device according to claim 1, wherein The side walls of the middle section are arranged obliquely, and the width of the middle section gradually decreases from top to bottom.

6. The semiconductor device according to claim 5, wherein The sidewalls of the upper section are arranged obliquely, and the width of the upper section gradually decreases from top to bottom. The slope of the sidewalls of the upper section is less than or equal to the slope of the sidewalls of the middle section.

7. The semiconductor device according to claim 6, wherein: The sidewall of the lower section is arranged in an inclined manner, and the slope of the sidewall of the lower section is smaller than the slope of the sidewall of the middle section, and larger than the slope of the sidewall of the upper section.

8. The semiconductor device according to claim 1, wherein The upper section, the middle section and the lower section have the same depth.

9. The semiconductor device according to any one of claims 1 to 8, wherein: At least one layer of sidewall spacer is formed on the side surface of the gate structure.

10. The semiconductor device according to claim 9, wherein The thickness of the side wall increases gradually from top to bottom.

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