Semiconductor device

Abstract

The embodiment of the utility model provides a semiconductor device which comprises a semiconductor substrate and a substrate through hole. The semiconductor substrate includes a first side and a second side opposite the first side. The substrate via includes a first portion and a second portion stacked over and connected to the first portion, the first portion extending through a first side of the semiconductor substrate, the second portion extending through a second side of the semiconductor substrate, and a high aspect ratio of the first portion is greater than an aspect ratio of the second portion, the first and second portions of the through-substrate vias may each have a lower aspect ratio, so that defects associated with through-substrate vias having high aspect ratios may be eliminated, thereby improving electrical performance and reliability of the semiconductor device.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to a semiconductor device, and more particularly, to a semiconductor device having a substrate via. BACKGROUND

[0002] The semiconductor industry has experienced rapid growth due to the continual improvement in the integration density of various electronic components. To a large extent, the improvement in integration density has come from the continual reduction in the size of the features that are integrated onto a given region. However, there are physical limitations to the density that can be achieved in two-dimensional integrated circuit formation. As semiconductor technology continues to advance, 3D packaging structures have emerged as an effective alternative to further reduce the physical size of chips. A through substrate via (TSV) that penetrates a substrate to electrically interconnect features on opposite sides of the substrate is one of the techniques to implement 3D packaging structures. There is a continuing effort to develop new mechanisms to form semiconductor structures having TSVs with improved electrical performance. SUMMARY

[0003] Embodiments of the present application provide a semiconductor device including a semiconductor substrate and a substrate via, the semiconductor substrate including a first side and a second side opposite the first side, the substrate via including a first portion and a second portion stacked on and connected to the first portion, the first portion extending through the first side of the semiconductor substrate, the second portion extending through the second side of the semiconductor substrate, and a depth-to-width ratio of the first portion being greater than a depth-to-width ratio of the second portion.

[0004] Embodiments of the present application provide a semiconductor device including a first package die, the first package die including a semiconductor substrate and a substrate via penetrating the semiconductor substrate, the substrate via including a first portion and a second portion stacked on and connected to the first portion, a portion of a seed layer of the substrate via at an interface of the first portion and the second portion being thicker than another portion of the seed layer lined on an inner sidewall of the semiconductor substrate.

[0005] Based on the above, the semiconductor device includes a substrate via designed to have a stepped profile, the stepped profile of the substrate via being formed by a first portion that is narrower and a second portion that is wider. In comparison to a conventional substrate via having a high depth-to-width ratio, the first portion and the second portion of the substrate via can each have a lower depth-to-width ratio. As a result, defects associated with a substrate via having a high depth-to-width ratio (e.g., ring-like defects, striations, poor step coverage, voids, charge damage on a guard ring, and / or the like) can be eliminated, thereby improving the electrical performance and reliability of the semiconductor device.

[0006] In order to make the above features and advantages of the embodiments of the present application more obvious and easy to understand, the following specific embodiments are described in detail below, and the detailed description is made with reference to the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0007] Figures 1A-1G schematic cross-sectional views of intermediate steps during a process for forming a first semiconductor die are shown.

[0008] Figure 1H is a schematic top view showing a backside metal, a second portion of a TSV, and a boundary of a first portion of the TSV, according to some embodiments.

[0009] Figures 2A-2F schematic cross-sectional views or intermediate steps during a process for forming a semiconductor package are shown, according to some embodiments.

[0010] Figures 3A-3F schematic cross-sectional views of intermediate steps during a process for forming another semiconductor package are shown, according to some embodiments.

[0011] Figure 4 and Figure 5 schematic cross-sectional views of different semiconductor structures with TSVs are shown, according to some embodiments.

[0012] REFERENCE NUMERALS

[0013] 10, 20, 30: semiconductor package; 10S: singulated sidewall; 40: semiconductor device; 40F: bonding interface; 51, 51': first temporary carrier; 52: release layer; 53, 53': second temporary carrier; 110, 110', 311: first redistribution structure; 110S, 130S, 131S, 132S, 140S, 150S, 170S, 1331S, 1370S, 1371S: sidewall; 110a, 302a: first side; 110b, 302b: second side; 111, 3111: first dielectric layer; 112, 112t, 112', 3112: first conductive pattern; 112v': bottommost via; 113, 1332: conductive pad; 120: conductive pillar / TMV; 120a, 140a, 170a, 1331a, 1332a, 1352s, 1370a, 1371a, 1372a: surface; 130, 130': first semiconductor die; 130-1, 130-2, 130-3, 130-4, 130-5, 130-6: semiconductor wafer; 130a: front surface; 130r, 160r: back surface; 131, 131-1, 131-2: semiconductor substrate; 131S1, 131S2: inner sidewall; 131S3: inner surface; 131a: front side; 131b: back side; 132: interconnect structure; 134: first conductive contact; 134': die bump; 135: substrate via / TSV; 135E: via collar; 135F: interface; 136: guard ring; 140: first encapsulation; 150, 312: second redistribution structure; 151, 3121: second dielectric layer; 152, 3122: second conductive pattern; 152t: topmost second conductive pattern; 160, 160A, 160B: second semiconductor die; 164: second conductive contact / conductive contact; 166: underfill; 170: second encapsulation / encapsulation; 180: conductive terminal; 190: third semiconductor die; 192: third conductive contact; 301: interposer; 302: circuit substrate; 364: conductive contact; 374: external terminal; 430-1: first level; 430-2: second level; 431: redistribution structure; 1301: device level; 1321: interconnect dielectric layer; 1322: interconnect trace; 1331, 1331', 4311: dielectric layer; 1351, 1351-1: first portion; 1351A, 1351A', 1352A: dielectric liner; 1351AH: horizontal portion; 1351B, 1352B, 1372B: seed layer; 1351B1, 1352B1, 1372B1: first sublayer; 1351B2, 1352B2, 1372B2: second sublayer; 1351C, 1352C: conductive material layer; 1351W, VPW2: bottommost width; 1352: second portion;1352U: upper portion; 1370: isolation layer; 1371: backside dielectric layer; 1372: backside metal layer; 1372C: conductive material; 3111b: bottommost first dielectric layer; 3112b: bottommost first conductive pattern; 3112t: topmost first conductive pattern; 4312: conductive pattern; 4312p: bottommost conductive pad; D1, D2, D3, E1: maximum lateral dimension; H1: first height; H2: second height; H3: total height; THK1: first thickness; THK2: second thickness; THS1: total thickness; THS2: thickness; VP1, VP2: opening. DETAILED DESCRIPTION

[0014] The following disclosure provides different embodiments or examples for implementing various features of the present disclosure. Specific examples of structures and arrangements are presented in order to provide a thorough description of the present disclosure. Of course, these are merely examples and are in no way limiting of the scope of this disclosure. For example, in the following description, a first feature formed "on" or "above" a second feature can include embodiments where the first feature is formed directly on the second feature or where the first feature is formed indirectly on the second feature with intervening features being present between the first feature and the second feature. Additionally, the present disclosure can be repeated in various examples using the same or similar reference numerals for structure and / or elements having the same or similar features. Such repetition is for the purpose of simplification and clarity and does not serve as a limitation of the various embodiments and / or configurations described herein.

[0015] Also for ease of explanation, spatially relative terms such as "beneath", "below", "lower", "above", "upper" and the like can be used herein for describing the orientation of one component or feature to another component or feature, as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0016] Embodiments are described in terms of specific structures and methods for preventing defects due to forming TSVs with high aspect ratios using stepped TSV structures. The embodiments described herein are not intended to be limited to the embodiments described, and embodiments can be implemented with any suitable methods and structures, such as integrated fanout (InFO) packages, package-on-package (PoP), chip-on-wafer-on-substrate (CoWoS) packages, system-on-integrated-circuit (SoIC) structures, etc. All such embodiments are within the scope of embodiments.

[0017] According to some embodiments, Figures 1A-1G schematic cross-sectional views of intermediate steps during a process for forming a first semiconductor die are shown, and Figure 1H is a schematic top view showing backside metal, a second portion of a TSV, and a boundary of a first portion of the TSV. Reference is made to Figure 1A A semiconductor wafer 130-1 is provided. Note that semiconductor wafer 130-1 can include different die regions that will be singulated to form multiple first semiconductor dies in subsequent processes, but for the sake of simplicity, Figures 1A-1G only a single die region is shown. In some embodiments, semiconductor wafer 130-1 includes a semiconductor substrate 131-1, such as doped or undoped silicon, or an active layer of a semiconductor-on-insulator (SOI) substrate. Semiconductor substrate 131-1 can include other semiconductor materials, such as germanium, compound semiconductors (including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide), alloy semiconductors (including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP), or combinations thereof. Other substrates can be used, such as multilayer or graded substrates. Semiconductor substrate 131-1 includes a front side 131a and a backside 131b opposite each other.

[0018] In some embodiments, semiconductor wafer 130-1 includes a device layer 1301 formed in / on a front side 131a of a semiconductor substrate 131-1. For example, device layer 1301 includes various active devices (e.g., transistors) and / or passive devices (e.g., capacitors, resistors, inductors), etc. that can be used to produce the structural and functional requirements desired by the design of semiconductor wafer 130-1. Device layer 1301 including active devices and / or passive devices can be formed by front-end-of-line (FEOL) and can be referred to as a FEOL layer. In some embodiments, active devices and / or passive devices are covered by an inter-layer dielectric (ILD) layer, where the ILD layer can include one or more layers formed of dielectric materials such as Phospho-Silicate Glass (PSG), Boro-Silicate Glass (BSG), Boron-Doped Phospho-Silicate Glass (BPSG), undoped Silicate Glass (USG), the like, or combinations thereof. In some embodiments, semiconductor wafer 130-1 serves as an intermediary. Alternatively, semiconductor wafer 130-1 does not have active and / or passive devices and omits device layer 1301.

[0019] With continued reference to Figure 1A , semiconductor wafer 130-1 can include an interconnect structure 132 that interconnects devices of device layer 1301 to form an integrated circuit. For example, interconnect structure 132 is formed by back-end-of-line (BEOL) and can be referred to as a BEOL structure. Interconnect structure 132 can include interconnect dielectric layers 1321 and interconnect traces 1322 formed in interconnect dielectric layers 1321. Interconnect dielectric layers 1321 can be formed of low-k dielectric materials or any suitable dielectric materials. In some embodiments, interconnect dielectric layers 1321 are referred to as inter-metal dielectric (IMD) layers. Interconnect traces 1322 can include wires, conductive pads, and vias, and can be formed of copper, alloys, and / or the like. Wires and conductive pads of the same level can be collectively referred to as a conductive layer, and conductive layers can be interconnected by vias. The number of interconnect dielectric layers and the number of conductive layers shown here are examples only and the present disclosure is not limited thereto.

[0020] In some embodiments, semiconductor wafer 130-1 includes a dielectric layer 1331 formed on interconnect dielectric layer 1321 and partially exposing at least a portion of a topmost portion of interconnect traces 1322. In some embodiments, dielectric layer 1331 is formed of a non-low-k dielectric material, such as undoped silicate glass (USG), silicon nitride, silicon oxide, silicon oxynitride (SiON), silicon oxycarbide (SiOC), silicon carbide (SiC), or the like, combinations thereof, and multilayers thereof. In some embodiments, semiconductor wafer 130-1 includes conductive pads (such as copper bump pads or the like) 1332 formed in dielectric layer 1331 and landing on interconnect traces 1322. Conductive pads 1332 can be electrically coupled to devices of device layer 1301 through interconnect traces 1322. In some embodiments, semiconductor wafer 130-1 includes die bumps 134’ formed on conductive pads 1332 in a one-to-one correspondence. Die bumps 134’ can include one or more electrically conductive materials, such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, alloys, the like, or combinations thereof. In some embodiments, die bumps 134’ are micro bumps (such as solder bumps). In some embodiments, die bumps 134’ include ball grid array (BGA) connections, solder balls, metal pillars, controlled collapse chip connection (C4) bumps, electroless nickel-electroless palladium-immersion gold (ENEPIG) bumps, and the like.

[0021] With continued reference to Figure 1A Semiconductor wafer 130-1 includes one or more first portions 1351-1 of TSVs 135 formed in via openings VP1 of semiconductor substrate 131-1 and extending into interconnect structure 132. Via openings VP1 can be formed by, for example, etching or any suitable removal process. Depending on the etching recipe, respective via openings VP1 can have substantially vertical sidewalls or a tapered profile in cross-section. For example, respective via openings VP1 have a tapered profile from interconnect traces 1322 to semiconductor substrate 131-1, as shown by the dashed lines. In some embodiments, an upper portion of respective first portions 1351-1 of TSVs 135 is laterally covered by interconnect dielectric layer 1321 and can be physically and electrically connected to one of interconnect traces 1322. A lower portion of respective first portions 1351-1 of TSVs 135 can be buried in semiconductor substrate 131-1 at this stage.

[0022] A respective first portion 1351-1 of the TSV 135 can include a dielectric liner 1351A' lining an inner sidewall 131S1 of the semiconductor substrate 131-1, a seed layer 1351B conformally disposed on the dielectric liner 1351A', and a conductive material layer 1351C disposed on the seed layer 1351B. The dielectric liner 1351A' can be formed by, for example, atomic layer deposition (ALD), chemical vapor deposition (CVD), plasma enhance chemical vapor deposition (PECVD), or any acceptable deposition process as a conformal layer lining the via opening VP1 of the semiconductor substrate 131-1. The dielectric liner 1351A' can be a single layer or can be a composite layer including multiple sub-layers and different materials. The dielectric liner 1351A' can include a dielectric material with good moisture barrier capability and / or can include a dielectric material with lower leakage current. In some embodiments, the dielectric liner 1351A' includes silicon oxide, silicon oxynitride, silicon nitride, silicon carbide, silicon oxycarbide, combinations thereof, and / or the like. The seed layer 1351B can be a single layer (e.g., formed of copper) or can include multiple sub-layers (e.g., a first sub-layer 1351B1 formed on the dielectric liner 1351A' and a second sub-layer 1351B2 formed on the first sub-layer 1351B1). For example, the first sub-layer 1351B1 is a conductive barrier layer formed of (or including) TiN, Ti, or the like, and the second sub-layer 1351B2 is a copper layer. The seed layer 1351B can be formed by physical vapor deposition (PVD) or any acceptable deposition process. The conductive material layer 1351C can include a metallic material such as copper, copper alloy, or the like, and can be formed by electrochemical plating (ECP), electroless plating, or the like.

[0023] Still referring to Figure 1Asemiconductor wafer 130-1 includes one or more guard rings 136 embedded in the interconnect dielectric layer 1321 and surrounding a first portion 1351-1 of the TSV 135. The guard rings 136 can be separated from the corresponding TSV 135 by the interconnect dielectric layer 1321. The guard rings 136 can be formed of copper, alloys, and / or the like. In the cross-sectional view, the respective guard rings 136 can have a substantially vertical inner sidewall, but the outer sidewall has a non-uniform profile (e.g., a stepped profile, a tapered profile, a zigzag profile, or other suitable profile). In some embodiments, the interconnect traces 1322 physically and / or electrically connect the guard rings 136 to the semiconductor substrate 131-1 and / or the device layer 1301, e.g., to a doped region in / on the semiconductor substrate 131-1. In some embodiments, the guard rings 136 are electrically connected to a voltage and / or to ground. The guard rings 136 can protect the TSV, improve TSV performance, improve TSV structural stability, shield, and / or reduce TSV-induced noise, or a combination thereof.

[0024] Referring to Figure 1B and referring to Figure 1A semiconductor wafer 130-1 can be placed on the first temporary carrier 51. For example, the material of the first temporary carrier 51 includes glass, silicon, metal, ceramic, combinations thereof, multilayers thereof, or the like. In some embodiments, the first temporary carrier 51 is provided with a release layer 52. For example, the release layer 52 includes a light-to-heat-conversion (LTHC) release coating that reduces or loses its tackiness when exposed to a radiation source, such as ultraviolet light or laser. In some embodiments, the release layer 52 includes any acceptable adhesive material. For example, the die bumps 134' are disposed on the first temporary carrier 51 and embedded in the release layer 52 for securing and protection. In some embodiments, a backside 131b of the semiconductor substrate 131-1 is subjected to a thinning process, such as grinding, chemical mechanical polishing, etching, combinations thereof, or the like, to form a semiconductor substrate 131-2 of a semiconductor wafer 130-2 having a reduced thickness. For example, a first thickness THK1 of the semiconductor substrate 131-1 is reduced to a second thickness THK2. The thinning process can facilitate a reduction in etch depth of the semiconductor substrate when forming the via opening VP2 (see Figure 1C ). Alternatively, the backside thinning process is omitted.

[0025] Referring to Figure 1C and referring to Figure 1BA portion of the removable semiconductor substrate 131-2 can be removed to form a semiconductor wafer 130-3 including the semiconductor substrate 131 with one or more via openings VP2, where the via openings VP2 can expose the first portions 1351 of the TSVs 135 in an accessible manner. A bottommost width VPW2 of the respective via openings VP2 can be greater than a bottommost width 1351W of the corresponding first portions 1351. Formation of the via openings VP2 can include forming photoresist (not shown) with openings on the backside 131b of the semiconductor substrate 131-2, etching (or in some embodiments, laser drilling) the semiconductor substrate 131-2 according to the openings of the photoresist until the first portions 1351 are revealed / formed, and removing the photoresist by ashing, stripping, and / or the like. Depending on the etching recipe, the respective via openings VP2 can have substantially vertical sidewalls or a tapered profile (as shown by the dashed lines) in cross-section. For example, the width of the respective via openings VP2 can gradually decrease from the backside 131b of the semiconductor substrate 131 to the first portions 1351.

[0026] In some embodiments, when the via openings VP2 are formed, at least the horizontal portion 1351AH of the dielectric liner 1351A’ is removed to expose the seed layer 1351B. In some other embodiments, when the via openings VP2 are formed, the horizontal portion 1351AH of the dielectric liner 1351A’ and at least a portion of the seed layer 1351B (e.g., a horizontal portion of the first sublayer 1351B1 or a horizontal portion of the first and second sublayers 1351B1 and 1351B2) are removed to expose an underlying layer (e.g., the second sublayer 1351B2 or the conductive material layer 1351C). After the via openings VP2 are formed, a substantially vertical portion of the dielectric liner 1351A’ remains to form the dielectric liner 1351A of the first portions 1351 of the TSVs 135.

[0027] Referring to Figure 1D and referring to Figure 1CA second portion 1352 of the TSV 135 can be formed in the via opening VP2 to form the semiconductor wafer 130-4 including the TSV 135 having a stepped (or staged) profile. The corresponding second portion 1352 can include a dielectric liner 1352A lining the inner sidewall 131S2 of the semiconductor substrate 131 and overlying the inner surface 131S3 of the semiconductor substrate 131, a seed layer 1352B formed on the dielectric liner 1352A and under the first portion 1351, and a conductive material layer 1352C formed on the seed layer 1352B and filling the via opening VP2. The dielectric liner 1352A can be exposed in a touchable manner to the corresponding first portion 1351. The dielectric liner 1352A can or can not extend from the inner surface 131S3 of the semiconductor substrate 131 to cover the dielectric liner 1351A. The dielectric liner 1352A can be a single layer or a composite layer including multiple sub-layers of different materials. The material and formation process of the dielectric liner 1352A can be similar to those of the dielectric liner 1351A. The seed layer 1352B can be a single layer (e.g., formed of copper) or can include multiple sub-layers (e.g., a first sub-layer 1352B1 formed on the dielectric liner 1352A and the first portion 1351 and a second sub-layer 1352B2 formed on the first sub-layer 1352B1). The material and formation process of the seed layer 1352B can be similar to those of the seed layer 1351B. The material and formation process of the conductive material layer 1352C can be similar to those of the conductive material layer 1351C.

[0028] The formation of the corresponding second portion 1352 can include conformally forming a dielectric material liner in the via opening VP2 by, e.g., ALD, CVD, or the like, partially removing a horizontal portion of the dielectric material liner to form the dielectric liner 1352A exposing the underlying first portion 1351 by, e.g., etching, or the like, where the inner surface 131S3 of the semiconductor substrate 131 can remain covered by the dielectric liner 1352A such that the dielectric liner 1352A can spatially separate the conductive material to be subsequently formed and the semiconductor substrate 131, forming the seed layer 1352B on the dielectric liner 1352A and the first portion 1351, forming the conductive material layer 1352C on the seed layer 1352B, performing an anneal process, and selectively performing a planarization process (e.g., CMP, etching, grinding, a combination thereof, or the like) to remove excess material on the backside 131b of the semiconductor substrate 131. In some other embodiments, when the dielectric material liner is formed only on the inner sidewall 131S2 of the semiconductor substrate 131, the step of removing the horizontal portion of the dielectric material liner is omitted.

[0029] The dielectric liner 1351A of the first portion 1351 can be laterally offset and discontinuous from the dielectric liner 1352A of the second portion 1352. The first sublayer 1352B1 of the second portion 1352 can be physically connected to the first sublayer 1351B1 of the first portion 1351 at the interface 135F between the first portion 1351 and the second portion 1352. The total thickness THS1 of the horizontal portion of the seed layer (1351B and 1352B) at the interface 135F can be greater than the thickness THS2 of the substantially vertical portion of each seed layer (1351B and 1352B). In some embodiments, the horizontal portion of the first sublayer 1352B1 of the seed layer 1352B of the second portion 1352 is in physical and electrical contact with the horizontal portion of the first sublayer 1351B1 of the seed layer 1351B of the first portion 1351. The lateral dimension of the horizontal portion of the first sublayer 1352B1 is greater than the lateral dimension of the horizontal portion of the first sublayer 1351B1, and the first sublayer 1352B1 can be in direct contact with the dielectric liner 1351A and the semiconductor substrate 131 of the first portion 1351. The conductive material layer 1352C of the second portion 1352 can be separated from the conductive material layer 1351C of the first portion 1351 by the seed layer (1351B and 1352B).

[0030] In some embodiments, as a result of the annealing process, the conductive material layer 1352C can have a portion that protrudes, and a planarization process can be performed to remove the portion of the conductive material layer 1352C. In some embodiments, the semiconductor substrate 131 is slightly recessed (e.g., by etching or the like) such that the corresponding upper portion 1352U of the second portion 1352 of the TSV 135 protrudes from the backside 131b of the semiconductor substrate 131. In some embodiments, the first portion 1351 and / or the second portion 1352 can have a tapered profile as indicated by the dashed lines. The tapering direction of the first portion 1351 can be opposite to the tapering direction of the second portion 1352. For example, the first portion 1351 tapers from the interconnect structure 132 to the second portion 1352. The second portion 1352 can taper from the backside 131b of the semiconductor substrate 131 to the first portion 1351.

[0031] Referring to Figure 1E and referring to Figure 1Dsemiconductor wafer 130-5 including the isolation layer 1370, where the isolation layer 1370 can surround the exposed portion of the second portion 1352 of the TSV 135. The material of the isolation layer 1370 can be or include silicon oxide, silicon nitride, and / or the like. In some embodiments, the isolation layer 1370 is a low temperature nitride layer. In some embodiments, after depositing the isolation material layer on the backside 131b of the semiconductor substrate 131, a planarization process (e.g., CMP, etching, grinding, a combination thereof, or the like) can be performed on the isolation material layer to form the isolation layer 1370 laterally covering the respective upper portion 1352U of the second portion 1352 of the TSV 135. For example, the surface 1370a of the isolation layer 1370 is substantially planar (or coplanar) with the surface 1352s of the second portion 1352 of the TSV 135 within a process variation range.

[0032] Referring to Figure 1F and referring to Figure 1E The backside dielectric layer 1371 and the backside metal layer 1372 can be formed on the isolation layer 1370 and the TSV 135 to form the semiconductor wafer 130-6. In some embodiments, the surface 1371a of the backside dielectric layer 1371 is substantially planar (or coplanar) with the surface 1372a of the backside metal layer 1372 within a process variation range. The backside dielectric layer 1371 can be formed of polyimide (PI), polybenzoxazole (PBO), benzocyclobutene (BCB), or other suitable dielectric material. The backside metal layer 1372 can be laterally covered by at least the backside dielectric layer 1371 and can be in physical and electrical contact with the second portion 1352 of the TSV 135. The backside metal layer 1372 can be or include a conductive pad (and / or other conductive feature) electrically coupled to the TSV 135.

[0033] The backside metal layer 1372 can include a seed layer 1372B overlying the isolation layer 1370 of the respective TSV 135 and a conductive material 1372C overlying the seed layer 1372B. The seed layer 1372B can be a single layer (e.g., formed of copper) or can include multiple sub-layers (e.g., a first sub-layer 1372B1 and a second sub-layer 1372B2 formed on the first sub-layer 1372B1). For example, the first sub-layer 1372B1 is a conductive barrier layer formed of (or including) TiN, Ti, or the like, and the second sub-layer 1372B2 is a copper layer. The first sub-layer 1372B1 can be in physical contact with the dielectric liner 1352A, the seed layer 1352B, and the conductive material layer 1352C of the second portion 1352.

[0034] Referring to Figure 1G and referring to Figure 1F The second temporary carrier 53 can be bonded to the backside dielectric layer 1371 and the backside metal layer 1372. In some embodiments, the second temporary carrier 53 is similar to the first temporary carrier 51. In some other embodiments, the second temporary carrier 53 can be or include a tape, a film, and / or the like. A release layer (not shown) is selectively disposed on the second temporary carrier 53, and the backside dielectric layer 1371 and the backside metal layer 1372 can be bonded to the second temporary carrier 53 through the release layer. In some embodiments, the first temporary carrier 51 and the release layer 52 are removed from the die bump 134'. In some cases where the release layer 52 includes an LTHC layer, an appropriate light illumination can be employed to weaken the bond of the LTHC layer so that the first temporary carrier 51 can be separated from the remaining structure. Alternatively, when the release layer 52 is an adhesive layer, an appropriate solvent can be used to dissolve the release layer 52. In some other embodiments, the first temporary carrier 51 and the release layer 52 are removed by stripping, peeling, etching, a combination thereof, or the like. After the first temporary carrier 51 and the release layer 52 are removed, the die bump 134' can be exposed in a touchable manner. A cleaning process is selectively performed on the die bump 134'.

[0035] In some embodiments, a singulation process is performed by sawing and / or laser cutting along the dicing lanes (not shown) to form a plurality of first semiconductor dies 130 supported by the second temporary carrier 53. For example, a respective first semiconductor die 130 includes singulated sidewalls 130S including sidewalls 1371S of the backside dielectric layer 1371, sidewalls 1370S of the isolation layer 1370, sidewalls 131S of the semiconductor substrate 131, sidewalls 132S of the interconnect structure 132, and sidewalls 1331S of the dielectric layer 1331. The respective first semiconductor die 130 includes a TSV 135 that extends through the semiconductor substrate 131. Each TSV 135 can include first and second portions (1351 and 1352) having different maximum lateral dimensions (D1 and D2) and the via openings for accommodating the first and second portions (1351 and 1352) can be formed by two etches. In some embodiments, a first height H1 of the first portion 1351 is substantially equal to a second height H2 of the second portion 1352 along a thickness direction of the first semiconductor die 130. Alternatively, the first height H1 is greater (or smaller) than the second height H2. The ratio of the first height H1 to the second height H2 can be in a range from about 1 to about 3, inclusive. In some embodiments, a total height H3 (i.e., a sum of the first height H1 and the second height H2) is in a range from about 25 pm to about 150 pm, inclusive.

[0036] Referring to Figure 1H and referring to Figure 1G The second portion 1352 and the first portion 1351 of the TSV 135 and / or the backside metal layer 1372 (e.g., conductive pad) can include a substantially circular top-down shape. In a top-down view, the second portion 1352 and the first portion 1351 can be substantially concentric within a process variation range. The concentrically aligned second portion 1352 and the first portion 1351 can reduce / eliminate overlay offset issues, as misalignment can cause overlay issues that lead to device failure and / or electrical leakage. But other top-down shapes (e.g., oval, rectangular, square, polygon, combinations thereof, etc.) can be used in other embodiments.

[0037] The backside metal layer 1372 (e.g., conductive pad) can include a maximum lateral dimension D3 (e.g., diameter or width) that is larger than a maximum lateral dimension (e.g., D2) of the underlying TSV 135. In some embodiments, in a top-down view, a boundary of the corresponding TSV 135 is completely within a boundary of the backside metal layer 1372 (e.g., conductive pad). For example, the second portion 1352 of the corresponding TSV 135 is wider than the first portion 1351 of the corresponding TSV 135. For example, the second portion 1352 includes a maximum lateral dimension D2 (e.g., diameter or width) that is larger than a maximum lateral dimension D1 of the first portion 1351. A boundary of the second portion 1352 of the corresponding TSV 135 can be completely within a boundary of the corresponding first portion 1351. In some embodiments, the maximum lateral dimension D2 of the second portion 1352 is substantially equal to the maximum lateral dimension D1 of the first portion 1351. A boundary of the second portion 1352 of the corresponding TSV 135 can be substantially overlapping with a boundary of the corresponding first portion 1351. In some embodiments, a ratio of the maximum lateral dimension D2 of the second portion 1352 to the maximum lateral dimension D1 of the first portion 1351 is in a range from about 1 to 1.5, inclusive.

[0038] In a top view, a via enclosure 135E may be disposed between a first portion 1351 and a second portion 1352 and defined by the boundary of the first and second portions (1351 and 1352). In some embodiments, the maximum lateral dimension E1 of the via enclosure 135E is non-zero. In alternative embodiments, where the second portion 1352 substantially overlaps the first portion 1351, the maximum lateral dimension E1 of the via enclosure 135E is substantially equal to zero. In some embodiments, the aspect ratio (H1 / D1) of the first portion 1351 is greater than (or substantially equal to) the aspect ratio (H2 / D2) of the second portion 1352. For example, the aspect ratio (H1 / D1) of the first portion 1351 is within a range between approximately 5.8 and approximately 8.7, inclusive. The aspect ratio (H2 / D2) of the second portion 1352 may be within a range between approximately 1.9 and approximately 5.8, inclusive. In some embodiments, the ratio of (H1 / D1) to (H2 / D2) is in a range from about 1 to about 4.6, inclusive.

[0039] It should be understood that for TSVs with high aspect ratios, filling material into the via openings becomes challenging. For example, voids may form in the via openings during TSV formation. Additionally, for TSVs with high aspect ratios, some squeeze-out or diffusion issues associated with the conductive material may occur due to insufficient sidewall coverage of the dielectric liner. Other defects associated with TSVs with high aspect ratios (e.g., ring defects, striations, charge damage on guard rings, and / or the like) may occur and result in yield loss. By forming the via openings for the TSVs 135 (e.g., VP1 and VP2) in two separate etching processes, each of the first portion 1351 of the TSV 135 in the via opening VP1 and the second portion 1352 of the TSV 135 in the via opening VP2 can have a reduced aspect ratio (compared to a via opening formed by a single etch). In this way, defects associated with the high aspect ratio of the TSVs can be reduced or eliminated, thereby improving the electrical performance and reliability of the first semiconductor die 130.

[0040] Figures 2A-2F Schematic cross-sectional views of intermediate steps during a process for forming a semiconductor package according to some embodiments are shown. Unless otherwise noted, the materials and formation methods in these embodiments are substantially the same as those in Figures 1A-1H Like components in the illustrated embodiments are identified by like reference numerals.

[0041] Reference Figure 2A , the first redistribution structure 110 may be formed on the first temporary carrier 51 '. The first temporary carrier 51 ' may be similar to Figure 1BA first temporary carrier 51 is described in the middle. In some embodiments, a release layer (not shown; can be similar to the release layer 52) is disposed on the first temporary carrier 51', and a first redistribution structure 110 can be formed on the release layer. In some embodiments, the first redistribution structure 110 includes one or more first dielectric layers 111 and one or more first conductive patterns 112 formed in / on the first dielectric layers 111. The material of the first dielectric layers 111 can include electrically insulating materials, such as polymers (e.g., PI, PBO, BCB, etc.) or any suitable dielectric material. The first conductive patterns 112 can include vias, conductive pads, and conductive lines collectively referred to as redistribution. The first conductive patterns 112 can be formed of conductive materials, such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, alloys, the like, combinations thereof, etc. In some embodiments, a bottommost via 112v of the first conductive patterns 112 can be formed above the first temporary carrier 51' for further electrical connection. It is noted that the number of the first dielectric layers 111 and the first conductive patterns 112 can be selected as desired, and the disclosure is not limited in this regard.

[0042] In some embodiments, the conductive pillars 120 are disposed on the first redistribution structure 110 and can be electrically connected to the first conductive patterns 112t. As an example, a photoresist (not shown) is formed on and patterned on the first redistribution structure 110 for forming the conductive pillars 120, where the pattern of the photoresist corresponds to the conductive pillars 120. The patterning process forms openings through the photoresist to expose at least a portion (e.g., a via or a conductive pad) of the topmost first conductive pattern 112t at the second side 110b of the first redistribution structure 110. One or more conductive materials (e.g., copper, titanium, tungsten, aluminum, alloys, and / or the like) can be formed in the openings of the photoresist. The photoresist can then be removed. The remaining portions of the conductive materials on the first redistribution structure 110 form the conductive pillars 120. In alternative embodiments, the conductive pillars 120 are pre-formed and placed on the first redistribution structure 110.

[0043] Referring to Figure 2B and referring to Figure 2A and Figure 1GOne or more first semiconductor dies 130 can be disposed on and electrically coupled to the first redistribution structure 110. The conductive pillars 120 can surround respective first semiconductor dies 130. In some embodiments, the respective first semiconductor dies 130 are picked up and placed on the first redistribution structure 110 while the second temporary carrier 53 serves as a structural support during the pick-and-place process. In some embodiments, die bumps 134' of the respective first semiconductor dies 130 are disposed on the topmost first conductive patterns 112t, and one or more reflow operations can be performed to reflow the die bumps 134' to form first conductive contacts 134. For example, a thermal operation is performed to melt the solder material of the die bumps 134' and create generally circular solder contacts. The respective first semiconductor dies 130 can be electrically coupled to the first redistribution structure 110 through the first conductive contacts 134. An underfill (shown in dashed lines) can be formed on the first redistribution structure 110 to laterally surround the first conductive contacts 134 for protection. Depending on the amount of underfill material applied, a portion of the underfill can climb up to cover at least a lower portion of the sidewalls 130S of the first semiconductor dies 130. Alternatively, the underfill is omitted so that the underfill does not cover the sidewalls 130S of the first semiconductor dies 130. Figure 2B shown in dashed lines to indicate that it can or can not be present.

[0044] Referring to Figure 2C and referring to Figure 2B A first encapsulant 140 can be formed on the first redistribution structure 110 to laterally cover the conductive pillars 120 and the respective first semiconductor dies 130 (and the underfill, if present). The first encapsulant 140 can be or include a molding compound, a molded underfill, an epoxy, or the like, and can be applied by compression molding, transfer molding, or the like. In some embodiments, the first encapsulant 140 is formed by forming a layer of encapsulation material on the first redistribution structure 110 to bury the conductive pillars 120 and the respective first semiconductor dies 130, curing the encapsulation material, and selectively performing a planarization process (e.g., CMP, grinding, etching, combinations thereof, or the like) on the encapsulation material to level the encapsulation material with the respective first semiconductor dies 130 and the conductive pillars 120.

[0045] In some embodiments, the second temporary carrier 53 is removed during (or after) the planarization process to expose the backside dielectric layer 1371 and the backside metal layer 1372 in a touchable manner. For example, the surface 140a of the first encapsulant 140 is substantially flush (or coplanar) with the surface 120a of the conductive pillar 120 and the back surface 130r of the respective first semiconductor die 130 within a process variation range. The back surface 130r of the respective first semiconductor die 130 can include a surface 1371a of the backside dielectric layer 1371 and a surface 1372a of the backside metal layer 1372. In some embodiments without forming an underfill, the first encapsulant 140 can be a molded underfill that extends into a gap between the respective first semiconductor die 130 and the first redistribution structure 110 to surround the first conductive contacts 134. In some embodiments, the conductive pillar 120 through the first encapsulant 140 (e.g., a molded layer) can be referred to as a through molding via (TMV) or a through interlayer via (TIV).

[0046] Referring to Figure 2D and referring to Figure 2C A second redistribution structure 150 can be formed on the first encapsulant 140, the TMV 120, and the respective first semiconductor die 130. In some embodiments, the second redistribution structure 150 includes one or more second dielectric layers 151 and one or more second conductive patterns 152 formed in / on the second dielectric layers 151 to electrically couple to the TMV 120 and the first semiconductor die 130. The material of the second dielectric layers 151 can be similar to the first dielectric layers 111 of the first redistribution structure 110, and the material of the second conductive patterns 152 can be similar to the first conductive patterns 112 of the first redistribution structure 110. The second conductive patterns 152 can include vias, conductive pads, and conductive lines collectively referred to as redistribution. In some embodiments, the first redistribution structure 110 connected to the first semiconductor die 130 through the first conductive contacts 134 is referred to as a front-side redistribution structure, and the second redistribution structure 150 connected to the backside of the first semiconductor die 130 is referred to as a backside redistribution structure.

[0047] In some embodiments, the bottommost via 152v of the second conductive pattern 152 formed in the opening of the bottommost second dielectric layer can land directly on the TMV 120 and the backside metal layer 1372 (e.g., a conductive pad). The tapering direction of the vias in the second re-routed structure 150 can be the same as the tapering direction of the vias in the first re-routed structure 110. For example, the vias in the second re-routed structure 150 taper in a direction toward the TMV 120 and the first semiconductor die 130, and the vias in the first re-routed structure 110 taper in a direction away from the TMV 120 and the first semiconductor die 130. It is noted that the number of the second dielectric layers 151 and the second conductive patterns 152 can be selected as desired, and the disclosure is not limited in this regard.

[0048] With continued reference to Figure 2DOne or more second semiconductor dies 160 can be disposed on and electrically coupled to the second redistribution structure 150. The second semiconductor dies 160 can be electrically coupled to the TMV 120 and the first semiconductor die 130 through the second conductive patterns 152 of the second redistribution structure 150. Respective second semiconductor dies 160 (e.g., 160A / 160B) can be or include a logic die (e.g., a central processing unit (CPU), a graphics processing unit (GPU), a system-on-a-chip (SoC), an application processor (AP), a microcontroller, etc.), a memory die (e.g., a high bandwidth memory (HBM) die, a hybrid memory cube (HMC) die, a dynamic random access memory (DRAM) die, a static random access memory (SRAM) die, etc.), a power management die (e.g., a power management integrated circuit (PMIC) die), a radio frequency (RF) die, a sensor die, a micro-electro-mechanical-system (MEMS) die, a signal processing die (e.g., a digital signal processing (DSP) die), a front-end die (e.g., an analog front-end (AFE) die), a voltage regulation die, a combination thereof, and / or the like. The second semiconductor dies (160A and 160B) can be the same kind of die or can be different kinds of dies. In an embodiment, the second semiconductor die 160A is a logic die and the second semiconductor die 160B is a memory die.

[0049] In some embodiments, a respective second semiconductor die 160 is coupled to a topmost second conductive pattern 152t (e.g., a conductive pad or UBM pad) of the second redistribution structure 150 by a second conductive contact 164. The second conductive contact 164 can be formed of a conductive material such as solder, copper, aluminum, gold, nickel, silver, the like, or a combination thereof. In some embodiments, the second conductive contact 164 is a solder contact. In some embodiments, an underfill 166 is formed in a gap between the second redistribution structure 150 and the second semiconductor die 160 to surround the second conductive contact 164. In some embodiments, the underfill 166 extends continuously between two adjacent second semiconductor dies (e.g., 160A). In some embodiments, the underfill 166 includes separate portions, and each of the portions of the underfill 166 surrounds any of the second semiconductor dies 160. In some embodiments, the underfill 166 covers the topmost second conductive pattern 152 under the second conductive contact 164. The underfill 166 can be formed by a capillary flow process after the second semiconductor die 160 is attached, or can be formed by an appropriate deposition method before the second semiconductor die 160 is attached. A curing process can be performed to cure the underfill material to form the underfill 166. Alternatively, the underfill 166 can be omitted.

[0050] Still referring to Figure 2D , a second encapsulation 170 can be formed on the second redistribution structure 150 to at least laterally cover the second semiconductor die 160 and the underfill 166. The material and formation process of the second encapsulation 170 can be similar to the first encapsulation 140 described in Figure 2C , and thus the detailed description of the second encapsulation 170 is not repeated here. In some embodiments where the underfill 166 is omitted, the second encapsulation 170 can be a molded underfill that fills the space filled by the underfill 166. The back surface 160r of a respective second semiconductor die (160A and / or 160B) can or can not be exposed by the second encapsulation 170 in a touchable manner. For example, a planarization process is performed to level the surface 170a of the second encapsulation 170 and the back surface 160r of the one or more second semiconductor dies 160. The back surface of a second semiconductor die (e.g., 160B) can or can not be covered by the second encapsulation 170.

[0051] Referring to Figure 2E and to Figure 2DThe first temporary carrier 51' can be detached from the first redistribution structure 110. In some embodiments where the first temporary carrier 51' has a LTHC layer (not shown) thereon, detachment of the first temporary carrier 51' includes projecting light (e.g., laser or UV light) at the release layer (if present) such that the release layer decomposes under the heat of the light to remove the first temporary carrier 51' and the release layer. In some embodiments where the first temporary carrier 51' has an adhesive layer (not shown) thereon, an appropriate solvent can be used to dissolve the adhesive layer. In some embodiments, the first temporary carrier 51' is removed by peeling, detaching, etching, a combination thereof, or the like. In some embodiments, a second temporary carrier 53' is attached to the second encapsulant 170 (and the second semiconductor die 160 if the back surface 160r is exposed by the second encapsulant 170). The second temporary carrier 53' can be similar to the first temporary carrier 51'. In some embodiments, the second temporary carrier 53' has a release layer (not shown) thereon to facilitate peeling of the second temporary carrier 53' from the resulting structure in subsequent processes. Alternatively, the release layer can be omitted. In some embodiments, after the first temporary carrier 51' is removed, the second side 110b of the first redistribution structure 110 can be exposed in an accessible manner, and a conductive pad (e.g., a UBM pad) 113 can be formed on the first dielectric layer 111 to physically and electrically contact the bottommost via 112v of the first conductive pattern 112 for further electrical connection.

[0052] Referring to Figure 2F and referring to Figure 2E The second temporary carrier 53' can be detached from the overlying structure. Detachment of the second temporary carrier 53' can be similar to Figure 2EThe removal process of the first temporary carrier 51' described in the middle. In some embodiments, a conductive terminal 180 can be formed on the conductive pad 113 of the first redistribution structure 110. The detachment process of the second temporary carrier 53' can be performed before the formation of the conductive terminal 180. Alternatively, the detachment process of the second temporary carrier 53' is performed after the formation of the conductive terminal 180. The conductive terminal 180 can include one or more conductive materials, such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, alloys, the like, or combinations thereof. In some embodiments, the conductive terminal 180 includes a BGA connection, a solder ball, a metal pillar, a C4 bump, a micro bump, an ENEPIG bump, or the like. One or more third semiconductor dies 190 can be mounted on the conductive pad 113 of the first redistribution structure 110 by a third conductive joint 192, such as a solder joint. The third semiconductor die 190 can be or include an integrated passive device (IPD), a surface mount device (SMD), or other suitable packaging components. Alternatively, the third semiconductor die 190 can be omitted.

[0053] In some embodiments, the resulting structure is formed in a wafer-level manner, and a singulation process (e.g., laser cutting, sawing, and / or the like) can be performed along a dicing lane (not shown) to separate the resulting structure into individual semiconductor packages 10. The semiconductor package 10 can include singulated sidewalls 10S that include sidewalls 170S of the second encapsulation 170, sidewalls 150S of the second redistribution structure 150, sidewalls 140S of the first encapsulation 140, and sidewalls 110S of the first redistribution structure 110. The semiconductor package 10 includes the first semiconductor die 130 with the TSV 135, and the TSV 135 can provide a vertical and electrical connection between the upper second redistribution structure 150 and the lower first redistribution structure 110, where the second redistribution structure 150 and the first redistribution structure 110 are disposed on opposite sides of the first semiconductor die 130. By configuring the TSV 135 in the first semiconductor die 130, additional routing can be eliminated and signal paths between opposite sides of the first semiconductor die 130 can be shortened. The respective TSV 135 can be designed to have a stepped profile formed by a first portion 1351 and a second portion 1352 that is wider than the first portion 1351. The first portion 1351 and the second portion 1352 of the TSV 135 can each have a lower aspect ratio compared to a conventional TSV having a high aspect ratio. As a result, defects associated with TSVs having a high aspect ratio can be eliminated, thereby improving the electrical performance and reliability of the semiconductor package 10.

[0054] Figures 3A-3Fschematic cross-sectional views of intermediate steps during a process for forming another semiconductor package are shown. Unless otherwise noted, the materials and formation methods in these embodiments are substantially the same as those described above in connection with Figures 1G-2F Like elements in the illustrated embodiments are identified with like reference numerals.

[0055] Referring to Figure 3A and to Figure 1G and Figure 2A , conductive pillars 120 can be formed over first temporary carrier 51’ and one or more first semiconductor dies 130’ can be disposed over first temporary carrier 51’. First semiconductor dies 130’ can be supported by second temporary carrier 53. In some embodiments, second temporary carrier 53 is replaced by a die attach film. In some embodiments, a release layer is provided on first temporary carrier 51’, conductive pillars 120 are formed on the release layer, and first semiconductor dies 130’ are disposed over the release layer with second temporary carrier 53 inserted vertically therebetween. The formation process and materials of conductive pillars 120 can be similar to those described in Figure 2A . First semiconductor dies 130’ can be similar to those described in Figure 1G , except that conductive pads 1332 are embedded in dielectric layer 1331’ for protection at this stage.

[0056] Referring to Figure 3B and to Figure 3A and Figure 2C , first encapsulation 140 can be formed over first temporary carrier 51’ to laterally cover at least conductive pillars 120, first semiconductor dies 130’, and second temporary carrier 53. The formation process and materials of first encapsulation 140 can be similar to those described in Figure 2C . During (or after) a planarization process, a portion of dielectric layer 1331’ is removed to expose conductive pads 1332 in an accessible manner for further electrical connections. For example, surface 140a of first encapsulation 140 and surface 120a of conductive pillars 120 are substantially planar (or coplanar) with front surface 130a of first semiconductor dies 130’ within a process variation range. Front surface 130a of first semiconductor dies 130’ can include surface 1331a of dielectric layer 1331 and surface 1332a of conductive pads 1332. Conductive pillars 120 that run through first encapsulation 140 can be referred to as TMVs.

[0057] Referring to Figure 3C and to Figure 3BA first redistribution structure 110' including a first dielectric layer 111 and a first conductive pattern 112' can be formed on the first encapsulant 140, the TMV 120, and the first semiconductor die 130'. The first redistribution structure 110' can be similar to the first redistribution structure 110 described in Figure 2A The described first redistribution structure 110', with the difference between them including the bottommost via 112v' at the second side 110b of the first conductive pattern 112' in physical and electrical contact with the surface 120a of the TMV 120 and the surface 1332a of the conductive pad 1332.

[0058] Referring to Figure 3D and to Figure 3C and Figure 2E , the first temporary carrier 51' can be detached from the overlying structures to expose the first encapsulant 140, the TMV 120, and the second temporary carrier 53. The detachment of the first temporary carrier 51' can be similar to the process described in Figure 2E . The second temporary carrier 53 can then be removed by any suitable process (e.g., grinding, etching, CMP, peeling, combinations thereof, or the like). After the removal of the second temporary carrier 53, the backside dielectric layer 1371 and the backside metal layer 1372 can be revealed in a touchable manner. For example, the surface 140a of the first encapsulant 140 is substantially flush (or coplanar) with the surface 120a of the TMV 120 and the back surface 130r of the first semiconductor die 130 (e.g., including the surface 1371a of the backside dielectric layer 1371 and the surface 1372a of the backside metal layer 1372) within a process variation range. In some embodiments, the second temporary carrier 53' is attached to the first side 110a of the first redistribution structure 110'. The attachment of the second temporary carrier 53' can be similar to the process described in Figure 2E . The backside dielectric layer 1371 and the backside metal layer 1372 can be formed on the first encapsulant 140, the TMV 120, and the first semiconductor die 130' by any suitable process (e.g., PVD, CVD, ALD, combinations thereof, or the like). The backside dielectric layer 1371 and the backside metal layer 1372 can be formed by a process similar to the process described in

[0059] Referring to Figure 3E and to Figure 3D and Figure 2D , a second redistribution structure 150 including a second dielectric layer 151 and a second conductive pattern 152 can be formed on the first encapsulant 140, the TMV 120, and the first semiconductor die 130'. The second redistribution structure 150 can be similar to the first redistribution structure 110' described in Figure 2D . A second semiconductor die 160 (e.g., 160A, 160B) can be mounted on the second redistribution structure 150 and electrically coupled to the second conductive pattern 152 by a second conductive contact 164. The coupling of the second semiconductor die 160 can be similar to the coupling of the first semiconductor die 130' described in Figure 2DThe underfill 166 can be selectively formed to at least surround the second conductive contacts 164. A second encapsulant 170 can be formed on the second redistribution structure 150 to cover the second semiconductor die 160 and the underfill 166 (if present). The formation processes and materials of the underfill 166 and the second encapsulant 170 can be similar to those described in Figure 2D

[0060] Referring to Figure 3F and referring to Figure 3E and Figure 2F The second temporary carrier 53’ can be detached from the overlying structures to expose the first side 110a of the first redistribution structure 110’ in an accessible manner. The detachment of the second temporary carrier 53’ can be similar to the processes described in Figure 2F A conductive pad 113 can be selectively formed on the first redistribution structure 110’. In some embodiments, a conductive terminal 180 can be formed on the conductive pad 113 of the first redistribution structure 110’. One or more third semiconductor dies 190 can be mounted on the conductive pad 113 of the first redistribution structure 110’ by third conductive contacts 192 (e.g., solder contacts). The conductive pad 113, the conductive terminal 180, and the third semiconductor dies 190 can be similar to the conductive pad 113, the conductive terminal 180, and the third semiconductor dies 190 described in Figure 2E and Figure 2F

[0061] In some embodiments, the resulting structure is formed in a wafer-level manner, and then a singulation process (e.g., laser cutting, sawing, and / or the like) can be performed along a dicing lane (not shown) to separate the resulting structure into individual semiconductor packages 20. The semiconductor package 20 and Figure 2F The difference between the semiconductor package 10 shown in FIGS. 1A-1C and the semiconductor package 20 shown in FIGS. 2A-2C includes that the tapering direction of the vias in the second redistribution structure 150 is different from the tapering direction of the vias in the first redistribution structure 110’. For example, the vias in the second redistribution structure 150 taper in a direction from the second semiconductor die 160 to the TMV 120 and the first semiconductor die 130’, and the vias in the first redistribution structure 110’ taper in a direction from the conductive terminal 180 to the TMV 120 and the first semiconductor die 130’. The interface between the first semiconductor die 130’ and the first redistribution structure 110’ of the semiconductor package 20 can not have a solder material.

[0062] Figure 4 and Figure 5 ​​Schematic cross-sectional views of different semiconductor structures with TSVs are shown in accordance with some embodiments. Unless otherwise noted, the materials and formation methods in these embodiments are substantially the same as the similar components denoted by similar reference numbers in the previous embodiments.

[0063] Reference is made to Figure 4 Semiconductor package 30 includes an interposer 301 and interposer 301 can include a TSV 135 that penetrates semiconductor substrate 131. Interposer 301 can include a first redistribution structure 311 disposed on a backside 131b of semiconductor substrate 131. For example, first redistribution structure 311 includes a first dielectric layer 3111 and a first conductive pattern 3112 formed in / on first dielectric layer 3111. In some embodiments, a bottommost first dielectric layer 3111b is similar to backside dielectric layer 1371, and a bottommost first conductive pattern 3112b directly connected to a second portion 1352 of TSV 135 is similar to backside metal layer 1372 as described in Figure 1F In some embodiments, interposer 301 includes a second redistribution structure 312 disposed on a frontside 131a of semiconductor substrate 131. In some embodiments, second redistribution structure 312 includes a second dielectric layer 3121 and a second conductive pattern (e.g., a conductive pad) 3122 formed in second dielectric layer 3121 and directly connected to a first portion 1351 of TSV 135. The number of first and second dielectric layers (3111 and 3121) and the number of first and second conductive patterns (3112 and 3122) can be selected as desired, without limitation.

[0064] In some embodiments, one or more semiconductor dies 160 can be disposed on first redistribution structure 311 and electrically coupled to first redistribution structure 311. For example, semiconductor die 160 is coupled to a topmost first conductive pattern 3112t (e.g., a conductive pad or a UBM pad) of first redistribution structure 311 through a conductive joint 164 (e.g., a solder joint). An underfill 166 can optionally be formed to surround at least conductive joint 164. An encapsulant 170 can be formed on first redistribution structure 311 to cover semiconductor die 160 and underfill 166 (if present). In some embodiments, second conductive pattern 3122 of second redistribution structure 312 is coupled to a first side 302a of circuit substrate 302 through a conductive joint 364 (e.g., a solder joint). Circuit substrate 302 can be any suitable package substrate, such as a printed circuit board (PCB), an organic substrate, a ceramic substrate, a motherboard, or the like.

[0065] Continuing to refer to Figure 4In some embodiments, the external terminals 374 include BGA connections, solder balls, metal pillars, C4 bumps, micro bumps, ENEPIG bumps, or the like. The size and pitch of the external terminals 374 can be larger than the size and pitch of the conductive contacts 364. The size and pitch of the conductive contacts 364 can be larger than the size and pitch of the conductive contacts 164. In some embodiments, the semiconductor package 30 is referred to as a three-dimensional integrated circuit (3DIC) package or a chip-on-wafer-on-substrate (CoWoS) package. The semiconductor package 30 includes the interposer 301 with the TSVs 135, and the TSVs 135 can provide vertical and electrical connections between the overlying first redistribution structure 311 and the underlying second redistribution structure 312. The TSVs 135 can be designed to have a first portion 1351 and a second portion 1352 formed by separate two etching processes. The first portion 1351 of the TSV 135 and the second portion 1352 of the TSV 135 can each have a reduced aspect ratio (compared to a via opening formed by a single etching). In this way, defects associated with high aspect ratio of the TSVs can be reduced or eliminated, thereby improving the electrical performance and reliability of the semiconductor package 30.

[0066] Referring to Figure 5 The semiconductor device 40 includes a first tier 430-1 and a second tier 430-2 stacked on and electrically coupled to the first tier 430-1. The first tier 430-1 can be similar to the first semiconductor die 130 described in Figure 1G For example, the redistribution structure 431 includes a dielectric layer 4311 and a conductive pattern 4312 formed in / on the dielectric layer 4311. In some embodiments, a topmost via 4312v of the conductive pattern 4312 can land on the conductive pad 1332, and the die bump 134’ can land on a bottommost conductive pad 4312p of the conductive pattern 4312. In alternative embodiments, the redistribution structure 431 is omitted.

[0067] The second tier 430-2 can be similar to the first semiconductor die 130 described in Figure 1BThe conductive pads 1332 are substantially aligned with and directly bonded to bonding surfaces (e.g., conductive pads) of a backside metal layer 1372, and the dielectric layers 1331 are directly bonded to a backside dielectric layer 1371. For the first tier 430-1, the bonding surfaces of the backside metal layer 1372 and the bonding surfaces of the backside dielectric layer 1371 can be substantially planar (or coplanar) within a process variation range. The backside metal layer 1372 and the backside dielectric layer 1371 can be collectively referred to as a first bonding layer. Similarly, for the second tier 430-2, the bonding surfaces of the conductive pads 1332 and the bonding surfaces of the dielectric layers 1331 can be substantially planar (or coplanar) within a process variation range. The conductive pads 1332 and the dielectric layers 1331 can be collectively referred to as a second bonding layer. The bonding interface 40F between the first tier 430-1 and the second tier 430-2 can be substantially planar and can include metal-to-metal bonds and dielectric-to-dielectric bonds (and, in some embodiments, dielectric-to-metal bonds).

[0068] It is noted that, Figure 5 The two-tier semiconductor device 40 is merely an example, and more tiers can be stacked on the second tier 430-2 as desired, without limitation. For example, the TSVs in the second tier 430-2 can include a second portion (not shown) formed on the first portion, and a bonding layer including the backside metal layer 1372 and the backside dielectric layer 1371 can be formed on the second portion of the TSVs and the semiconductor substrate for bonding additional tiers thereon. The semiconductor device 40 includes TSVs 135 designed to have a stepped profile formed by a narrower first portion 1351 and a wider second portion 1352. The first portion 1351 and the second portion 1352 of the TSVs 135 can each have a lower aspect ratio compared to conventional TSVs having a high aspect ratio. As a result, defects associated with TSVs having a high aspect ratio (e.g., ring-like defects, striations, poor step coverage, voids, charge damage on guard rings, and / or the like) can be eliminated, thereby improving the electrical performance and reliability of the semiconductor device 40.

[0069] Other features and processes can also be included. For example, test structures can be included to facilitate verification testing of 3D packages or 3DIC devices. The test structures can include, for example, test pads formed on a redistribution layer or a substrate that allow for testing of 3D packages or 3DICs, use of probes and / or probe cards, etc. Verification testing can be performed on intermediate structures as well as final structures. In addition, the structures and methods disclosed herein can be used in conjunction with intermediate verification testing methods of known good dies to increase yield and reduce cost.

[0070] According to some embodiments, an apparatus includes a semiconductor die. The semiconductor die includes a semiconductor substrate and a TSV. The semiconductor substrate includes a first side and a second side opposite the first side. The TSV includes a first portion and a second portion stacked on and connected to the first portion, the first portion extending through the first side of the semiconductor substrate, the second portion extending through the second side of the semiconductor substrate, and a depth-to-width ratio of the first portion is greater than a depth-to-width ratio of the second portion.

[0071] In some embodiments, the substrate via includes a seed layer, and a portion of the seed layer at an interface of the first portion and the second portion is thicker than another portion of the seed layer lined on an inner sidewall of the semiconductor substrate. In some embodiments, each of the first portion and the second portion of the substrate via includes a seed layer and a layer of conductive material disposed on the seed layer, and the layer of conductive material of the first portion is separated from the layer of conductive material of the second portion by the seed layer of the first portion and the second portion. In some embodiments, a maximum lateral dimension of the second portion of the substrate via is greater than a maximum lateral dimension of the first portion of the substrate via. In some embodiments, a maximum height of the first portion of the substrate via is greater than or substantially equal to a maximum height of the second portion of the substrate via. In some embodiments, the first portion of the substrate via includes a first dielectric liner, and the second portion of the substrate via includes a second dielectric liner laterally offset from the first dielectric liner. In some embodiments, the apparatus further includes an interconnect structure under the first side of the semiconductor substrate, wherein a portion of the first portion of the substrate via extending through the first side of the semiconductor substrate extends further into a dielectric layer of the interconnect structure to contact an interconnect trace of the interconnect structure. In some embodiments, the apparatus further includes a dielectric layer overlying the second side of the semiconductor substrate and a conductive pad covered by the dielectric layer and connected to the second portion of the substrate via, wherein a surface of the dielectric layer away from the second side of the semiconductor substrate is substantially planar with a surface of the conductive pad away from the second portion of the substrate via. In some embodiments, a maximum lateral dimension of the conductive pad of the substrate via is greater than the maximum lateral dimension of the second portion of the substrate via. In some embodiments, the semiconductor substrate, the substrate via, the dielectric layer, and the conductive pad are included in a semiconductor die, and the apparatus further includes a re-distribution structure disposed on and electrically coupled to the semiconductor die, wherein a re-distribution of the re-distribution structure is in physical and electrical contact with the conductive pad.

[0072] According to some alternative embodiments, an apparatus includes a first package die, and the first package die includes a semiconductor substrate and a TSV through the semiconductor substrate. The TSV includes a first portion and a second portion stacked on the first portion and connected to the first portion, a portion of a seed layer of the TSV at an interface of the first and second portions is thicker than another portion of the seed layer lined on an inner sidewall of the semiconductor substrate.

[0073] In some embodiments, an aspect ratio of the first portion of the substrate via is greater than or substantially equal to an aspect ratio of the second portion of the substrate via. In some embodiments, the apparatus further includes a second package die stacked on the first package die and a first redistribution structure interposed between and electrically coupled to the first package die and the second package die. In some embodiments, the apparatus further includes a second redistribution structure electrically coupled to the first package die by a solder joint, wherein the first redistribution structure and the second redistribution structure are disposed at opposite sides of the first package die.

[0074] According to some alternative embodiments, a method of manufacturing an apparatus includes forming a semiconductor die. Forming the semiconductor die includes forming a first portion of a TSV in a semiconductor substrate, wherein the first portion of the TSV extends from a first side of the semiconductor substrate into the semiconductor substrate, and forming a second portion of the TSV in the semiconductor substrate, wherein the second portion of the TSV extends into the semiconductor substrate to land on the first portion from a second side of the semiconductor substrate opposite the first side, and an aspect ratio of the first portion is greater than an aspect ratio of the second portion.

[0075] In some embodiments, the first portion of the substrate via includes a first dielectric liner and a first seed layer conformally formed on the first dielectric liner, and forming the second portion of the substrate via includes forming a via opening in the semiconductor substrate from the second side of the semiconductor substrate, wherein after forming the via opening, a bottom portion of the first dielectric liner is removed such that the via opening exposes a bottom portion of the first seed layer, and a second seed layer is formed in the via opening, wherein a bottom portion of the second seed layer is in direct contact with the bottom portion of the first seed layer. In some embodiments, forming the via opening in the semiconductor substrate includes etching the semiconductor substrate to form the via opening that is wide enough to expose a portion of the semiconductor substrate that surrounds the first portion of the substrate via. In some embodiments, forming the semiconductor die further includes forming a dielectric layer over the second side of the semiconductor substrate and forming a conductive pad over the second side of the semiconductor substrate and directly connected to the second portion of the substrate via, wherein a surface of the dielectric layer distal to the second side of the semiconductor substrate is substantially planar with a surface of the conductive pad distal to the second portion of the substrate via. In some embodiments, forming the semiconductor die further includes thinning the semiconductor substrate from the second side prior to forming the second portion of the substrate via. In some embodiments, the method further includes coupling the semiconductor die to a redistribution structure through a solder joint, wherein the first portion of the substrate via is closer to the redistribution structure than the second portion of the substrate via.

[0076] Finally, it should be noted that the above-described embodiments are merely intended to illustrate the technical solutions of the present application, but not to limit the present application; even though the above-described embodiments of the present application have been described in detail, those skilled in the art should understand that the technical solutions recorded in the above-described embodiments can still be modified, or some or all of the technical features can be replaced equivalently; and these modifications or replacements do not cause the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A semiconductor device, characterized in that: include: a semiconductor substrate comprising a first side and a second side opposite to the first side; as well as A through-substrate via includes a first portion and a second portion stacked on and connected to the first portion, wherein the first portion extends through the first side of the semiconductor substrate, the second portion extends through the second side of the semiconductor substrate, and an aspect ratio of the first portion is greater than an aspect ratio of the second portion.

2. The semiconductor device according to claim 1, wherein The through-substrate via includes a seed layer, and a portion of the seed layer at an interface between the first portion and the second portion is thicker than another portion of the seed layer lining an inner sidewall of the semiconductor substrate.

3. The semiconductor device according to claim 1, wherein Each of the first and second portions of the through-substrate hole includes a seed layer and a conductive material layer disposed on the seed layer, and the conductive material layer of the first portion is separated from the conductive material layer of the second portion by the seed layers of the first and second portions.

4. The semiconductor device according to claim 1, wherein The maximum lateral dimension of the second portion of the through-substrate hole is greater than the maximum lateral dimension of the first portion of the through-substrate hole.

5. The semiconductor device according to claim 1, wherein The maximum height of the first portion of the through-substrate hole is greater than or substantially equal to the maximum height of the second portion of the through-substrate hole.

6. The semiconductor device according to claim 1, wherein The first portion of the through-substrate via includes a first dielectric liner, and the second portion of the through-substrate via includes a second dielectric liner laterally offset from the first dielectric liner.

7. The semiconductor device according to claim 1, wherein Also includes: a dielectric layer overlying the second side of the semiconductor substrate; as well as A conductive pad is covered by the dielectric layer and connected to the second portion of the through-substrate via, wherein a surface of the dielectric layer away from the second side of the semiconductor substrate is substantially flush with a surface of the conductive pad away from the second portion of the through-substrate via.

8. A semiconductor device, characterized in that: include: A first encapsulated die comprising: semiconductor substrates; as well as A through-substrate via penetrates the semiconductor substrate, the through-substrate via comprising a first portion and a second portion stacked on and connected to the first portion, wherein a portion of a seed layer of the through-substrate via at an interface between the first portion and the second portion is thicker than another portion of the seed layer lining an inner sidewall of the semiconductor substrate.

9. The semiconductor device according to claim 8, wherein The aspect ratio of the first portion of the through-substrate via is greater than or substantially equal to the aspect ratio of the second portion of the through-substrate via.

10. The semiconductor device according to claim 8, wherein Also includes: a second encapsulated die stacked on top of the first encapsulated die; as well as A first redistribution structure is interposed between the first encapsulated die and the second encapsulated die and is electrically coupled to the first encapsulated die and the second encapsulated die.

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