Packaging substrate, semiconductor device and electronic equipment
By arranging a flat plate on the surface of the first RDL layer of the packaging substrate, the problem of poor contact caused by the uneven surface of the packaging substrate is solved, reliable electrical connection between the semiconductor element and the RDL layer is achieved, and product quality is improved.
Patent Information
- Application Number
- CN202422796592.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-15
- Publication Date
- 2025-10-21
- Estimated Expiration
- 2034-11-15
AI Technical Summary
The outermost surface of the existing packaging substrate is uneven, resulting in poor or no contact between the chip and the pins.
A flat plate is arranged on the surface of the first RDL layer of the package substrate away from the core layer. The surface of the flat plate is a flat plane, and the conductive through-holes are electrically connected to the first RDL layer. The semiconductor element is electrically connected to the first RDL layer through the conductive through-holes.
This ensures that the electrical connection between the semiconductor element and the first RDL layer is reliable and stable, thereby improving the quality and reliability of the product.
Smart Images
Figure CN223462225U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application belongs to the technical field of semiconductor devices, and particularly relates to a packaging substrate, a semiconductor device and an electronic device. BACKGROUND
[0002] The intelligence of electronic products cannot be separated from the support of chips. Chips are mainly responsible for executing instructions of specific programs and controlling operation of part or all functions of single products.
[0003] A chip is a highly integrated and miniaturized element that includes circuits (mainly including semiconductor devices and various components). The chip has many connection pins that are densely distributed on the surface of the chip and used for coupling with a PCB circuit. Since the pins of the chip are too dense to be directly coupled with the lines of the PCB circuit, a packaging substrate is needed to realize electrical connection between the chip and the PCB circuit.
[0004] The packaging substrate can be fixedly installed on a PCB board. The packaging substrate is provided with pins corresponding to the pins of the chip to be coupled with the chip. Meanwhile, the side of the packaging substrate close to the PCB board has relatively sparse pins to be electrically connected with the lines on the PCB board.
[0005] The existing packaging substrate is composed of a glass substrate and an RDL (Redistribution Layer) layer. The RDL layer is made of a plurality of insulating layers and line layers one by one. Each insulating layer is provided with a line layer, so that the metal lines gradually converge to the center to form pins corresponding to the pins of the chip. However, the above-mentioned method of setting the insulating layers one by one, plus the line layer on each insulating layer, causes the surface of the outermost insulating layer to be uneven. When the chip is installed and connected, the pins of the chip may not be in good contact with the pins or even cannot be in contact with the pins. SUMMARY
[0006] The embodiment of the present application provides a packaging substrate, which aims to solve the problem that the uneven surface of the outermost layer of the existing packaging substrate leads to poor contact or even no contact when connected with a chip.
[0007] The embodiment of the present application is implemented in the following manner. A packaging substrate is provided, which comprises:
[0008] a core layer;
[0009] a first RDL layer formed on the core layer, the first RDL layer having a first surface away from the core layer;
[0010] The flat plate is arranged on the first surface, and the flat plate has a conductive through hole penetrating the flat plate, the conductive through hole is electrically connected to the first RDL layer on one side of the first RDL layer, and the other side is used for connecting the semiconductor element, and the flat plate has a surface parallel to the plane where the core layer is located.
[0011] Further, the thickness of the flat plate ranges from 10 to 100 microns.
[0012] Further, the side of the flat plate away from the first RDL layer is provided with a groove, the conductive through hole is arranged in the groove, and the groove is used for placing the semiconductor element.
[0013] Further, the surface area of the flat plate is smaller than the surface area of the core layer.
[0014] Further, the flat plate is bonded to the first surface through the bonding layer.
[0015] Further, the filling layer is filled between the flat plate and the first RDL layer.
[0016] Further, the core layer includes a glass substrate and a core through hole.
[0017] The first RDL layer is arranged on the first side of the glass substrate, and the core through hole penetrates the glass substrate and is electrically connected to the first RDL layer.
[0018] Further, the second RDL layer and the mother plate are further included.
[0019] The second RDL layer is arranged on the second side of the glass substrate, the second side is opposite to the first side, and the core through hole is electrically connected to the second RDL layer.
[0020] The second RDL layer has a second surface away from the glass substrate, and the mother plate is arranged on the second surface and is electrically connected to the second RDL layer.
[0021] In a third aspect, the application also provides a semiconductor device including the packaging substrate as described above.
[0022] In a third aspect, the application also provides an electronic device including the semiconductor device as described above.
[0023] The beneficial effects of the present application: the packaging substrate provided by the present application includes a core layer, a first RDL layer and a flat plate, the first RDL layer is formed on the core layer, the first RDL layer has a first surface away from the core layer, the flat plate is arranged on the first surface, the flat plate has a conductive via hole penetrating through the flat plate, the conductive via hole is electrically connected to the first RDL layer on one side of the first RDL layer, and the other side is used to connect a semiconductor element, and the surface of the flat plate is parallel to the plane where the core layer is located. By arranging a flat plate on the first surface of the first RDL layer away from the core layer, the surface of the flat plate is a flat plane, and the plane where the core layer is located is parallel, so that the semiconductor element can be better mounted on the flat plate, and the semiconductor element is electrically connected to the first RDL layer through the conductive via hole of the flat plate, so that the electrical connection between the semiconductor element and the first RDL layer is reliable and stable, and the product quality is guaranteed. BRIEF DESCRIPTION OF DRAWINGS
[0024] Figure 1 is a structural schematic diagram of an embodiment of the packaging substrate provided by the present application connected with a chip;
[0025] Figure 2 is a structural schematic diagram of an embodiment of the packaging substrate provided by the present application connected with a chip;
[0026] Figure 3 is a structural schematic diagram of another embodiment of the packaging substrate provided by the present application connected with a chip;
[0027] Figure 4 is Figure 3 is an enlarged schematic diagram of part A in FIG. 8.
[0028] BRIEF DESCRIPTION OF DRAWINGS 110-core layer, 111-core via hole, 120-first RDL layer, 121-insulating layer, 122-circuit layer, 130-flat plate, 131-conductive via hole, 132-groove, 140-semiconductor element, 150-second RDL layer, 160-motherboard. DETAILED DESCRIPTION
[0029] In order to make the purpose, technical scheme and advantages of the present application more clear, the present application is further described in detail below in combination with the drawings and embodiments. The examples of the embodiments are shown in the drawings, wherein the same or similar reference numerals represent the same or similar elements or elements having the same or similar functions throughout. The embodiments described below by referring to the drawings are exemplary and are only used to explain the present application, and cannot be understood as limiting the present application. In addition, it should be understood that the specific embodiments described herein are only used to explain the present application and do not limit the present application.
[0030] In the description of the application, it should be understood that the terms "length", "width", "upper", "lower", "left", "right", "horizontal", "top", "bottom", and the like are intended to indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the purpose of facilitating the description of the application and simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation to the application.
[0031] In addition, the terms "first", "second" are only for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the technical features indicated. Therefore, the features defined with "first", "second" can explicitly or implicitly include one or more features. In the description of the application, the meaning of "a plurality of" is two or more, unless otherwise explicitly specified and limited.
[0032] In the description of the application, it should be noted that unless otherwise explicitly specified and limited, the terms "mounting", "connecting", "connection" should be understood in a broad sense, for example, it can be fixedly connected, or it can be detachably connected, or integrally connected; it can be mechanically connected, or electrically connected or can communicate with each other; it can be directly connected, or indirectly connected through an intermediate medium, or the communication between two elements or the interaction between two elements. For those skilled in the art, the specific meaning of the above terms in the application can be understood according to the specific circumstances.
[0033] In the present application, unless otherwise explicitly specified and limited, the "upper" or "lower" of the first feature to the second feature can include the direct contact of the first and second features, or the indirect contact of the first and second features through another feature between them. Moreover, the "upper", "above" and "above" of the first feature to the second feature include the vertical direction of the first feature above and oblique above the second feature, or only indicate that the horizontal height of the first feature is higher than that of the second feature. The "below", "below" and "below" of the first feature to the second feature include the vertical direction of the first feature below and oblique below the second feature, or only indicate that the horizontal height of the first feature is less than that of the second feature.
[0034] The following disclosure provides many different embodiments, or examples, for implementing different structures of the present application. For purposes of simplicity and clarity, the description is directed to specific examples of components and arrangements. Of course, it is to be understood that in the broader sense, the application can be implemented with different structures and / or used in different ways without departing from the application. In the following description, numerous specific details are discussed to provide a thorough understanding of the present application. However, it will be clear to those skilled in the art that the present application can be practiced without such specific details. In other instances, well-known methods have not been described in detail in order to avoid obscuring the present application. Additionally, the present application provides examples of various specific processes and materials. However, one skilled in the art will recognize that other processes and / or materials can be used without departing from the present application.
[0035] The package substrate provided by the present application includes a core layer, a first RDL layer and a flat plate, the first RDL layer is formed on the core layer, the first RDL layer has a first surface away from the core layer, the flat plate is arranged on the first surface, the flat plate has a conductive via hole penetrating through the flat plate, the conductive via hole is electrically connected to the first RDL layer on one side and is used for connecting a semiconductor element on the other side, and the surface of the flat plate is parallel to the plane where the core layer is located. By arranging a flat plate on the first surface of the first RDL layer away from the core layer, the surface of the flat plate is a flat plane and the plane where the core layer is located is parallel, so that the semiconductor element can be better mounted on the flat plate and electrically connected to the first RDL layer through the conductive via hole of the flat plate, so that the electrical connection between the semiconductor element and the first RDL layer is reliable and stable, and the product quality is guaranteed.
[0036] As shown in Figures 1 to 4 An embodiment of the present application provides a package substrate, which includes:
[0037] a core layer 110;
[0038] a first RDL layer 120 formed on the core layer 110, the first RDL layer 120 has a first surface away from the core layer 110;
[0039] a flat plate 130 arranged on the first surface, the flat plate 130 has a conductive via hole 131 penetrating through the flat plate 130, the conductive via hole 131 is electrically connected to the first RDL layer 120 on one side and is used for connecting a semiconductor element 140 on the other side, and the surface of the flat plate 130 is parallel to the plane where the core layer 110 is located.
[0040] In implementation, the core layer 110 is used as a support body of the package substrate to arrange the first RDL layer 120 on the core layer 110, wherein the first RDL layer 120 is made by stacking a plurality of insulating layers 121 and a plurality of circuit layers 122 one by one upward along the core layer 110.
[0041] Exemplarily, the first conductive layer can be formed on the core layer 110, and after a photolithography exposure process or the like, the first conductive layer becomes the first layer of circuit layer 122, and then the first layer of insulating layer 121 is formed on the first layer of circuit layer 122, and the first layer of insulating layer 121 is windowed to expose some connection points on the first layer of circuit layer 122. Then, the second layer of circuit layer 122 is formed on the first layer of insulating layer 121, and the second layer of circuit layer 122 covers the window on the first layer of insulating layer 121 to form a conductive column electrically connected with the connection points on the first layer of circuit layer 122.
[0042] The above operation is repeated, and the connection points exposed by the windowing of the nth layer of insulating layer 121 between the (n+1)th layer of circuit layer 122 of the next layer and the nth layer of circuit layer 122 of the previous layer are electrically connected. Since the conductive column of each layer will move towards the middle, compared with the first layer of circuit layer 122, the last layer of circuit layer 122 will be more dense, that is, the circuit layer 122 on the first surface will be more dense.
[0043] In some embodiments, the core layer 110 is provided with a conductive layer (not shown in the figure), which is used to connect with an external circuit, for example, the packaging substrate can be mounted on a PCB (Printed Circuit Board), so that the conductive layer is electrically connected with the circuit on the PCB, and the first layer of circuit layer 122 is electrically connected with the conductive layer, realizing the electrical connection between the semiconductor element 140 and the PCB.
[0044] As a possible implementation, the core layer 110 includes a glass substrate and a core via hole 111, the first RDL layer 120 is arranged on the first side of the glass substrate, the core via hole 111 penetrates the glass substrate, one end of the core via hole 111 is electrically connected with the first RDL layer 120, and the other end of the core via hole 111 is used to be electrically connected with the PCB, thereby realizing the electrical connection between the semiconductor element 140 and the PCB.
[0045] It should be noted that the above packaging substrate mounted on the PCB is an example of one embodiment of the application, and is not a specific limitation of the application. In other embodiments, the packaging substrate can also be connected with other components or elements, for example, electrically connected with an FPC (Flexible Printed Circuit), without specific limitation.
[0046] The surface of the flat plate 130 is parallel to the plane where the core layer 110 is located. Exemplarily, the side of the flat plate 130 away from the first RDL layer 120 is parallel to the plane where the core layer 110 is located, that is, the side of the flat plate 130 away from the first RDL layer 120 is a flat surface, so as to facilitate the mounting and fixing of the semiconductor element 140 on the flat plate 130.
[0047] In some embodiments, the plane where the core layer 110 is refers to the side of the core layer 110 close to the first RDL layer 120 or the side of the core layer 110 away from the first RDL layer 120, which is not described herein.
[0048] Optionally, the thickness of the flat plate 130 ranges from 10 to 100 microns, for example, the thickness of the flat plate 130 is 11 microns, 12 microns, 13 microns, 15 microns, 20 microns, 25 microns, 30 microns, 35 microns, 40 microns, 45 microns, 50 microns, 60 microns, 70 microns, 80 microns, 90 microns, or any value within the range of 10 to 100 microns, which is not specifically limited.
[0049] The flat plate 130 is provided with a plurality of conductive vias 131, which penetrate the flat plate 130 and are electrically connected to the last layer of the circuit layer 122. Since the last layer of the circuit layer 122 is relatively dense, the conductive vias 131 are also relatively dense. The dense conductive vias 131 can be electrically connected to the dense pins of the semiconductor element 140, thereby realizing the electrical connection between the semiconductor element 140 and the external circuit.
[0050] The packaging substrate provided by the present application comprises a core layer 110, a first RDL layer 120, and a flat plate 130. The first RDL layer 120 is formed on the core layer 110. The first RDL layer 120 has a first surface away from the core layer 110. The flat plate 130 is arranged on the first surface. The flat plate 130 has conductive vias 131 penetrating the flat plate 130. The conductive vias 131 are electrically connected to the first RDL layer 120 on one side and are used to connect the semiconductor element 140 on the other side. The surface of the flat plate 130 is parallel to the plane where the core layer 110 is. By arranging a flat plate 130 on the first surface of the first RDL layer 120 away from the core layer 110, the surface of the flat plate 130 is a flat plane, and the plane where the core layer 110 is is parallel. Therefore, the semiconductor element 140 can be better mounted on the flat plate 130 and electrically connected to the first RDL layer 120 through the conductive vias 131 of the flat plate 130. The electrical connection between the semiconductor element 140 and the first RDL layer 120 is reliable and stable, thereby ensuring the product quality.
[0051] In some embodiments, the flat plate 130 is provided with a groove 132 on the side away from the first RDL layer 120. The conductive vias 131 are arranged in the groove 132. The groove 132 is used to place the semiconductor element 140. The semiconductor element 140 can be embedded in the groove 132. That is, the groove 132 is arranged to position the semiconductor element 140. Therefore, the pins of the semiconductor element 140 can be accurately connected to the conductive vias 131 one by one, thereby facilitating the installation.
[0052] In some embodiments, the area at the conductive via 131 is generally small, for example, when the flat plate 130 is provided with a groove 132 on the side far away from the first RDL layer 120, the area of the bottom of the groove 132 is small, that is, only the position where the semiconductor element 140 needs to be placed is provided with the flat plate 130, and the flat plate 130 can be designed to have a surface area smaller than that of the core layer 110, thereby reducing the use amount of the flat plate 130 and controlling the cost.
[0053] Further, a bonding layer is further included, and the flat plate 130 is bonded to the first surface through the bonding layer.
[0054] In implementation, the flat plate 130 can be an ultra-thin glass or other flat plate, and the bonding between the ultra-thin glass and the first RDL layer 120 is poor, so a bonding layer can be formed by applying glue, etc., to bond the first RDL layer 120 and the flat layer through the bonding layer.
[0055] Further, the first RDL layer 120 is made of a plurality of insulating layers 121 and a plurality of circuit layers 122 layer by layer, which will cause the surface of the insulating layer 121 of the last layer to be uneven, and a filling layer can be provided to fill the gap between the flat plate 130 and the first RDL layer 120, so as to fill the gap between the flat plate 130 and the first RDL layer 120 with air, water vapor, etc.
[0056] Further, a second RDL layer 150 and a mother board 160 are further included.
[0057] The second RDL layer 150 is arranged on the second side of the glass substrate, the second side is opposite to the first side, and the core via 111 is electrically connected to the second RDL layer 150.
[0058] The second RDL layer 150 has a second surface away from the glass substrate, and the mother board 160 is arranged on the second surface and is electrically connected to the second RDL layer 150.
[0059] In implementation, the second RDL layer 150 is also made of a plurality of insulating layers 121 and a plurality of circuit layers 122 layer by layer, specifically, the structure and principle of the second RDL layer 150 can refer to the above-mentioned first RDL layer 120, and the circuit layers 122 of both the first RDL layer 120 and the second RDL layer 150 gradually converge to the middle from the second surface to the first surface.
[0060] The glass substrate has opposite first and second surfaces, wherein the first RDL layer 120 is arranged on the first surface of the glass substrate, and the second RDL layer 150 is arranged on the second surface of the glass substrate, that is, the glass substrate is sandwiched between the first RDL layer 120 and the second RDL layer 150.
[0061] The glass substrate has a plurality of core through holes 111 which pass through the glass substrate. Exemplarily, the packaging substrate further comprises a conductive pillar array composed of a plurality of conductive pillars, the plurality of conductive pillars of the conductive pillar array are arranged in the core through holes 111 of the glass substrate one by one, the first end of the conductive pillar is electrically connected with the circuit layer 122 of the last layer in the second RDL layer 150, and the second end of the conductive pillar is electrically connected with the circuit layer 122 of the first layer in the first RDL layer 120. Since the circuit layers 122 will gradually converge to the middle, that is, the circuit layers 122 of the first surface will be more dense compared with the circuit layers 122 of the second surface, therefore, the area surrounded by the projection of the circuit layers 122 of the second surface on the first surface is greater than the area surrounded by the projection of the circuit layers 122 of the first surface on the first surface, then the packaging substrate can be electrically connected with the circuit of the PCB board through the circuit layers 122 of the second surface, and electrically connected with the semiconductor element 140 such as a chip through the circuit layers 122 of the first surface.
[0062] In some embodiments, a semiconductor device is also provided, comprising the packaging substrate as described above.
[0063] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the structure and implementation principle of the semiconductor device described above can refer to the corresponding structure and implementation principle in the foregoing embodiments, which will not be described here.
[0064] The packaging substrate provided in the present application comprises a core layer 110, a first RDL layer 120 and a flat plate 130, the first RDL layer 120 is formed on the core layer 110, the first RDL layer 120 has a first surface away from the core layer 110, the flat plate 130 is arranged on the first surface, the flat plate 130 has a conductive through hole 131 passing through the flat plate 130, the conductive through hole 131 is electrically connected with the first RDL layer 120 on one side relative to the first RDL layer 120, and the other side is used for connecting a semiconductor element 140, and the surface of the flat plate 130 is parallel to the plane where the core layer 110 is located. By arranging a flat plate 130 on the first surface of the first RDL layer 120 away from the core layer 110, the surface of the flat plate 130 is a flat plane and the plane where the core layer 110 is located is parallel, so that the semiconductor element 140 can be better mounted on the flat plate 130 and electrically connected with the first RDL layer 120 through the conductive through hole 131 of the flat plate 130, so that the electrical connection between the semiconductor element 140 and the first RDL layer 120 is reliable and stable, and the product quality is guaranteed.
[0065] In some embodiments, an electronic device is also provided, comprising the semiconductor device as described above.
[0066] In implementation, the electronic device includes but is not limited to a chip and further has an electrical device such as a communication device, a smart device, a power supply or a related device for automotive electronic device, medical device, household appliance, etc.
[0067] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the structure and implementation principle of the electronic device described above can refer to the corresponding structure and implementation principle in the foregoing embodiments, which will not be repeated here.
[0068] The packaging substrate provided in the application comprises a core layer 110, a first RDL layer 120 and a flat plate 130, the first RDL layer 120 is formed on the core layer 110, the first RDL layer 120 has a first surface away from the core layer 110, the flat plate 130 is arranged on the first surface, the flat plate 130 has a conductive via hole 131 penetrating through the flat plate 130, the conductive via hole 131 is electrically connected to the first RDL layer 120 on one side relative to the first RDL layer 120, and the other side is used for connecting a semiconductor element 140, and the flat plate 130 has a surface parallel to the plane where the core layer 110 is located. By arranging a flat plate 130 on the first surface of the first RDL layer 120 away from the core layer 110, the surface of the flat plate 130 is a flat plane and the plane where the core layer 110 is located is parallel, so that the semiconductor element 140 can be better mounted on the flat plate 130 and electrically connected to the first RDL layer 120 through the conductive via hole 131 of the flat plate 130, so that the electrical connection between the semiconductor element 140 and the first RDL layer 120 is reliable and stable, and the product quality is guaranteed.
[0069] The above is only a preferred embodiment of the application and is not used to limit the application, and any modification, equivalent replacement and improvement made within the spirit and principle of the application shall be included in the protection scope of the application.
Claims
1. A package substrate, characterized by, The package substrate comprises: a core layer; a first RDL layer formed on the core layer, the first RDL layer having a first surface away from the core layer; a flat plate provided on the first surface, the flat plate having a conductive via hole penetrating through the flat plate, the conductive via hole being electrically connected to the first RDL layer on one side and being used for connecting a semiconductor element on the other side, the flat plate having a surface parallel to the plane of the core layer.
2. The package substrate of claim 1, wherein, The thickness of the flat plate ranges from 10 to 100 microns.
3. The package substrate of claim 1, wherein, The flat plate has a groove on the side away from the first RDL layer, the conductive via hole being provided in the groove, the groove being used for placing the semiconductor element.
4. The package substrate of claim 1, wherein, The surface area of the flat plate is smaller than that of the core layer.
5. The package substrate of claim 1, wherein, A bonding layer is further provided, the flat plate being bonded to the first surface through the bonding layer.
6. The package substrate of claim 1, wherein, A filling layer is further provided, the filling layer being filled between the flat plate and the first RDL layer.
7. The package substrate of claim 1, wherein, The core layer comprises a glass substrate and a core via hole; The first RDL layer is provided on the first side of the glass substrate, the core via hole being electrically connected to the first RDL layer through the glass substrate.
8. The package substrate of claim 7, wherein, A second RDL layer and a mother plate are further provided; The second RDL layer is provided on the second side of the glass substrate, the second side being opposite to the first side, the core via hole being electrically connected to the second RDL layer; The second RDL layer has a second surface away from the glass substrate, the mother plate being provided on the second surface and being electrically connected to the second RDL layer.
9. A semiconductor device, characterized by comprising: The semiconductor device comprises the package substrate as claimed in any one of claims 1 to 8.
10. An electronic device, comprising: The semiconductor device comprises the package substrate as claimed in claim 9.