Schottky diode

Abstract

The utility model discloses a Schottky diode, and relates to the technical field of semiconductors. The semiconductor device comprises a semiconductor substrate, a first doped region, a second doped region and a third doped region, the semiconductor substrate comprises a first surface region, the first doped region extends into the semiconductor substrate from the first surface region, and the first doped region is obtained by doping aluminum ions with a first doping concentration. The second doped region extends from the first surface region to the semiconductor substrate, and the first doped region and the second doped region are arranged in a staggered manner along the first direction of the first surface region. The second doped region is obtained by doping aluminum ions with a second doping concentration, and the first doping concentration is greater than the second doping concentration. The third doped region extends into the semiconductor substrate from the first surface region and is obtained by doping aluminum ions with the first doping concentration, and the area of the third doped region is larger than that of the first doped region. Therefore, the reverse voltage withstanding performance of the diode is improved, and the forward conduction voltage drop is reduced.

Description

TECHNICAL FIELD

[0001] The utility model relates to the field of semiconductor technology especially relates to a Schottky diode. BACKGROUND

[0002] In the field of high-voltage and high-power applications, Schottky barrier diodes have lower on-state loss due to lower forward voltage drop, and as unipolar devices, they have no minority carrier storage and reverse recovery phenomenon, and have higher switching frequency. However, the Schottky barrier height of the Schottky barrier diode is low, the reverse leakage current is large, the withstand voltage is poor, and the surge resistance is poor. In order to reduce the reverse leakage current and improve the withstand voltage and surge resistance, a P+ (aluminum ion doped with a first doping concentration) doped region is introduced to form a depletion region to shield the electric field of the Schottky region during reverse voltage, thereby reducing the reverse leakage current and improving the withstand voltage. For example, silicon carbide junction barrier Schottky diodes (SiC JBS) and silicon carbide hybrid PiN / Schottky diodes (SiC MPS).

[0003] The SiC MPS diode is a bipolar device, which is in a unipolar working mode under low forward bias voltage, and the voltage drop at this time is the forward unipolar conduction voltage drop of the device. When the forward bias voltage rises, the P+ region in the diode is turned on, and the device enters a bipolar working mode, injecting minority carrier holes into the drift layer, triggering conductivity modulation, and reducing the on-resistance. Under high forward bias voltage, in order to make the diode enter the bipolar working mode more quickly, the node voltage value of the unipolar-bipolar transition, i.e. the forward bipolar conduction voltage drop, needs to be reduced. However, the current common methods of increasing the area ratio of the P+ region, increasing the P+ region junction depth, and using different Schottky metal materials to control the metal work function to increase the Schottky barrier height will all result in an increase in the on-voltage drop and on-state loss of the Schottky barrier diode under low forward bias voltage. SUMMARY

[0004] In view of the problems of increased on-voltage drop and on-state loss of the Schottky diode under low forward bias voltage, the utility model is proposed to provide a Schottky diode that overcomes the above problems or at least partially solves the above problems.

[0005] Based on the first aspect of the utility model, a Schottky diode is provided, which comprises:

[0006] a semiconductor substrate, the semiconductor substrate comprising a first surface region;

[0007] at least one first doped region, the first doped region extending from the first surface region into the semiconductor substrate, wherein the first doped region is doped with aluminum ions with a first doping concentration;

[0008] at least two second doped regions, the second doped regions extending from the first surface region into the semiconductor substrate, and the first doped regions and the second doped regions being staggered along a first direction of the first surface region, the second doped regions being doped with aluminum ions at a second doping concentration, and a junction depth of the second doped regions gradually decreasing from a center away from the first surface region to a center close to the first surface region in the first direction, wherein the first doping concentration is greater than the second doping concentration;

[0009] at least two third doped regions, the third doped regions extending from the first surface region into the semiconductor substrate, wherein the third doped regions are doped with aluminum ions at a first doping concentration, and an area of the third doped regions is greater than an area of the first doped regions.

[0010] An optional utility model content, the third doped regions are distributed on both sides of the first surface region along the first direction.

[0011] An optional utility model content, along the first direction of the first surface region, the third doped regions are in contact with the second doped regions, and the second doped regions are in contact with the first doped regions.

[0012] An optional utility model content, the second doped regions are spaced along a second direction of the first surface region, wherein the first direction and the second direction are perpendicular to each other.

[0013] An optional utility model content, a distribution interval of the second doped regions along the second direction of the first surface region is between 3 μm and 12 μm.

[0014] An optional utility model content, the junction depth of the first doped regions is greater than the junction depth of the second doped regions.

[0015] An optional utility model content, a first width of the first doped regions in the first direction is between 1 μm and 3 μm.

[0016] An optional utility model content, a third width of the third doped regions in the first direction is between 10 μm and 20 μm.

[0017] An optional utility model content, the first doping concentration corresponding to the first doped regions and the third doped regions is between 1 × 10 18 cm -3 and 1 × 10 20 cm -3 .

[0018] An optional utility model content, the second doping concentration corresponding to the second doping area is between 8*10 16 cm -3 ~ 2*10 17 cm -3 .

[0019] An optional utility model content, the first surface area is provided with at least two.

[0020] Compared with the prior art, the utility model includes semiconductor substrate, first doping area, second doping area and third doping area, the semiconductor substrate includes first surface area, the first doping area extends from the first surface area into the semiconductor substrate, wherein the first doping area is doped by aluminum ions with a first doping concentration. The second doping area extends from the first surface area to the semiconductor substrate, and the first doping area and the second doping area are staggered along the first direction of the first surface area, the second doping area is doped by aluminum ions with a second doping concentration, and the junction depth of the second doping area gradually decreases from the center away from the first surface area to the center close to the first surface area in the first direction, and the first doping concentration is greater than the second doping concentration. The third doping area extends from the first surface area to the semiconductor substrate, the third doping area is doped by aluminum ions with a first doping concentration, and the area of the third doping area is greater than the area of the first doping area. Therefore, the reverse voltage resistance performance of the diode can be improved and the forward conduction voltage drop can be reduced. The different junction depths of the second doping area can realize continuous adjustment of the Schottky barrier height. The Schottky barrier height of the second doping area with smaller junction depth is lower, and the interval distribution of the second doping area can ensure the forward conduction characteristics of the diode. The second doping area with larger junction depth can increase the Schottky barrier height, reduce the forward bipolar conduction voltage drop of the diode, and reduce the on-state loss.

[0021] The above description is only a summary of the technical scheme of the utility model, in order to more clearly understand the technical means of the utility model, which can be implemented according to the content of the specification, and in order to make the above and other purposes, characteristics and advantages of the utility model more obvious and easy to understand, the following specific embodiments of the utility model are described. BRIEF DESCRIPTION OF DRAWINGS

[0022] By reading the detailed description of the preferred embodiments below, various other advantages and benefits will become apparent to those of ordinary skill in the art. The drawings are for the purpose of illustrating the preferred embodiments only and are not to be considered as limiting of the utility model. Moreover, the same reference numerals are used throughout the several drawings to designate the same or similar parts.

[0023] In the drawings:

[0024] Figure 1 is a structure schematic view of a Schottky diode provided by an embodiment of the present application;

[0025] Figure 2 is Figure 1 a cross-sectional structure schematic view of A-A in the structure schematic view of the Schottky diode;

[0026] Figure 3 is Figure 1 a cross-sectional structure schematic view of B-B in the structure schematic view of the Schottky diode;

[0027] Figure 4 is a cross-sectional structure schematic view of another Schottky diode provided by an embodiment of the present application;

[0028] Figure 5 is a step flow schematic view of a manufacturing method of a Schottky diode provided by an embodiment of the present application;

[0029] Figure 6 is a structure schematic view of a semiconductor substrate provided by an embodiment of the present application;

[0030] Figure 7 is a first partial structure schematic view of a Schottky diode provided by an embodiment of the present application;

[0031] Figure 8 is a second partial structure schematic view of a Schottky diode provided by an embodiment of the present application;

[0032] Figure 9 is a third partial structure schematic view of a Schottky diode provided by an embodiment of the present application;

[0033] Reference signs: 1, semiconductor substrate; 11, drift layer; 12, buffer layer; 13, substrate layer; 101, first surface region; 2, first doped region; 3, second doped region; 4, third doped region; 5, anode ohmic metal contact layer; 6, anode metal layer; 7, anode Schottky metal contact region; 8, cathode metal layer. DETAILED DESCRIPTION

[0034] Exemplary embodiments of the present application will be described herein below with reference to the accompanying drawings. Although exemplary embodiments of the present application are shown in the drawings, it is understood that the present application can be implemented in various forms and should not be limited by the embodiments set forth herein. Rather, these embodiments are provided so that this application will be thoroughly and completely understood, and so that the scope of the present application will be completely conveyed to those skilled in the art.

[0035] In the field of high-voltage and high-power applications, Schottky barrier diodes have lower on-state loss due to lower forward voltage drop, and as unipolar devices, they have no minority carrier storage and reverse recovery phenomenon, and have higher switching frequency. However, the Schottky barrier height is low, the reverse leakage current is large, the withstand voltage is poor, and the surge resistance is poor. In order to reduce the reverse leakage current and improve the withstand voltage and surge resistance, a P+(first doping concentration of aluminum ions) doped region is introduced to form a depletion region to shield the electric field of the Schottky region during reverse voltage, thereby reducing the reverse leakage current and improving the withstand voltage. For example, silicon carbide junction barrier Schottky diodes (SiC JBS) and silicon carbide hybrid PiN / Schottky diodes (SiC MPS).

[0036] The SiC MPS diode is a bipolar device, which operates in unipolar mode at low forward bias voltage, and the voltage drop is the forward unipolar on voltage drop of the device. When the forward bias voltage increases, the P+ region in the diode is turned on, and the device enters the bipolar mode, injecting minority carrier holes into the drift layer, triggering conductivity modulation, and reducing the on-resistance. At high forward bias voltage, in order to make the diode enter the bipolar mode more quickly, the node voltage value of the unipolar-bipolar transition, i.e. the forward bipolar on voltage drop, needs to be reduced. However, the current common methods of increasing the area ratio of P+ region, increasing the P+ region junction depth, and using different Schottky metal materials to control the metal work function to increase the Schottky barrier height, all will result in an increase in the on voltage drop and on-state loss of the Schottky barrier diode at low forward bias voltage.

[0037] Based on the above technical problems, the utility model embodiment can include semiconductor substrate 1, at least one first doped area 2 and at least two second doped areas 3, the semiconductor substrate 1 includes first surface area 101, the first doped area 2 extends from the first surface area 101 to the semiconductor substrate 1, wherein, the first doped area 2 adopts the first doped concentration aluminum ion doping to obtain. The second doped area 3 extends from the first surface area 101 to the semiconductor substrate 1, and the first doped area 2 and the second doped area 3, along the first direction of the first surface area 101 staggered arrangement, the second doped area 3 adopts the second doped concentration aluminum ion doping to obtain, and, the second doped area 3's junction depth in the first direction, from the center of the first surface area 101 away, to the center of the first surface area 101 close gradually smaller, the first doped concentration is greater than the second doped concentration. The third doped area 4 extends from the first surface area 101 to the semiconductor substrate 1, the third doped area 4 adopts the first doped concentration aluminum ion doping to obtain, the third doped area 4's area area is greater than the first doped area 2's area area. Thus, can promote the reverse voltage resistance performance of diode and reduce the forward conduction voltage drop. The setting of the different junction depth of the second doped area 3 can realize the continuous adjustable of schottky barrier height. The schottky barrier height of the second doped area 3 of smaller junction depth is lower, and the interval distribution of the second doped area 3 can guarantee the forward conduction characteristic of diode. The second doped area 3 of larger junction depth can increase schottky barrier height, reduce the forward bipolar conduction voltage drop of diode, and reduce the on-state loss.

[0038] Referring Figures 1-3 The utility model embodiment provides a kind of schottky diode, the schottky diode can include semiconductor substrate 1, at least one first doped area 2, at least two second doped areas 3 and at least two third doped areas 4. The semiconductor substrate 1 includes first surface area 101, the first doped area 2 extends from the first surface area 101 to the semiconductor substrate 1, wherein, the first doped area 2 adopts the first doped concentration aluminum ion doping to obtain. The second doped area 3 extends from the first surface area 101 to the semiconductor substrate 1, and the first doped area 2 and the second doped area 3, along the first direction of the first surface area 101 staggered arrangement, the second doped area 3 adopts the second doped concentration aluminum ion doping to obtain, and, the second doped area 3's junction depth in the first direction, from the center of the first surface area 101 away, to the center of the first surface area 101 close gradually smaller.

[0039] The third doped region 4 extends from the first surface region 101 into the semiconductor substrate 1, wherein the third doped region 4 is doped with aluminum ions at a first doping concentration, and the area of the third doped region 4 is greater than the area of the first doped region 2.

[0040] In the embodiment of the utility model, the semiconductor substrate 1 is the support base of diode structure, it can be N type semiconductor substrate 1, the semiconductor substrate 1 can include but not limited to substrate layer 13, buffer layer 12 and drift layer 11 etc., wherein, the substrate layer 13 can be N type silicon carbide substrate, the buffer layer 12 can be N type silicon carbide buffer layer, the drift layer 11 can be N type silicon carbide drift layer. Wherein, the drift layer 11 can be obtained by doping nitrogen element. The semiconductor substrate 1 can include first surface region 101. Wherein, the first surface region 101 can be understood as the part area on the first surface of the semiconductor substrate 1.

[0041] The first doped region 2 and the second doped region 3 extend from the first surface region 101 into the semiconductor substrate 1 respectively. Wherein, the first doped region 2 is doped with aluminum ions at a first doping concentration, and the second doped region 3 is doped with aluminum ions at a second doping concentration. The first doped region 2 can form a depletion region between the semiconductor substrate 1 when reverse voltage, so as to shield the Schottky region electric field, and further reduce the reverse leakage current and improve the withstand voltage capability. Thus, the setting of the first doped region 2 can improve the reverse withstand voltage performance of the diode and reduce the forward conduction voltage drop.

[0042] When the metal contacts the semiconductor substrate 1, the electrons in the semiconductor substrate 1 will flow to the metal, thereby forming a depletion region near the first surface region 101 of the semiconductor and generating an internal electric field, which is called Schottky region electric field. Wherein, the role of the Schottky region electric field is to prevent the electrons from further flowing from the semiconductor substrate 1 to the metal, thereby forming an electron potential barrier at the contact surface, which is called Schottky barrier. The Schottky barrier has rectifying characteristics, that is, it only allows current to flow in one direction, which makes the Schottky diode have unidirectional conductivity.

[0043] The setting of different junction depths of the second doped region 3 can realize the continuous adjustment of the height of the Schottky barrier, for example, the second doped region 3 with smaller junction depth has lower Schottky barrier height, and the interval distribution of the second doped region 3 can ensure the forward conduction characteristics of the diode. The second doped region 3 with larger junction depth can increase the height of the Schottky barrier, reduce the forward bipolar conduction voltage drop of the diode, and reduce the on-state loss. Wherein, the junction depth can be understood as the distance between the end face of the doped region away from the first surface region 101 and the first surface region 101, for reference Figure 2 andFigure 3 As shown, the junction depth of the first doped region 2 can be H1, the junction depth of the second doped region 3 can be H2, and the junction depth of the third doped region 4 can be H3.

[0044] The first doped region 2 and the second doped region 3 are staggered, as shown in Figure 2 and Figure 4 As shown, it can be understood that between two adjacent second doped regions 3 in the first direction, at least one first doped region 2 is arranged.

[0045] The junction depth of the second doped region 3 gradually decreases from the center away from the first surface region 101 to the center close to the first surface region 101 in the first direction, forming a continuous adjustment of the Schottky barrier height. The Schottky barrier height corresponding to the second doped region 3 with smaller junction depth is lower, which can ensure that electrons flow more easily from the metal to the semiconductor substrate 1, thereby improving the forward conduction rate of the Schottky diode while ensuring that the current does not over-flow. The second doped region 3 with larger junction depth can increase the Schottky barrier height, which can reduce the forward bipolar conduction voltage drop of the device. Moreover, before the diode switches from unipolar mode to bipolar mode, the conductivity modulation effect can be triggered earlier, thereby reducing the on-resistance and reducing the on-state loss, and improving the surge resistance of the diode.

[0046] The third doped region 4 can be referred to as a large P+ ion doped region, that is, a P-type doped region formed by a high-concentration aluminum ion. Correspondingly, the first doped region 2 can be referred to as a small P+ ion doped region, that is, a P-type doped region formed by a low-concentration aluminum ion. Among them, P+ ion can be understood as a high-concentration aluminum ion, and the arrangement of the third doped region 4 can be used to improve the conduction capability of the diode under large current, and in combination with the first doped region, it can produce beneficial effects such as improving the reverse voltage resistance performance, surge current resistance performance of the diode, and reducing the forward conduction voltage drop. Among them, the surge current refers to the peak current or overload current that is much larger than the steady-state current generated at the moment of power-on or abnormal situation of the circuit.

[0047] In some embodiments, as shown in Figure 1 and Figure 2 As shown, the third doped region 4 can be provided with two, and the two third doped regions 4 can be distributed on both sides of the first surface region 101 along the first direction.

[0048] An alternative utility model embodiment, as shown in Figure 2As shown, along a first direction of the first surface region 101, the third doped region 4 is in contact with the second doped region 3, and the second doped region 3 is in contact with the first doped region 2.

[0049] In the embodiment of the utility model, along the first direction of the first surface region 101, for example, the X-axis direction, the first doped region 2, the second doped region 3 and the third doped region 4 form continuous arrangement, so that the second doped region 3 can be introduced between the first doped region 2 and the third doped region 4, or between two first doped regions 2, and the continuous adjustable Schottky barrier height can be realized by combining the setting of different junction depths of the second doped region 3. The Schottky barrier height of the second doped region 3 with smaller junction depth is lower, which can ensure the forward conduction characteristic of the diode, that is, a small amount of increase of the forward unipolar conduction voltage drop and reduction of the reverse leakage current of the diode. The second doped region 3 with larger junction depth can increase the Schottky barrier height, reduce the forward bipolar conduction voltage drop of the diode, and reduce the on-state loss.

[0050] An optional embodiment of the utility model, referring to Figure 1 and Figure 3 As shown, the second doped region 3 is spaced apart along a second direction of the first surface region 101, wherein the first direction and the second direction are perpendicular to each other.

[0051] In the embodiment of the utility model, the spaced apart distribution of the second doped region 3 can increase the Schottky area of the non-second doped region 3, so that the relationship between the forward bipolar conduction voltage drop and the forward unipolar conduction voltage drop can be balanced, that is, the forward bipolar conduction voltage drop is reduced in the form of a small amount of increase of the forward unipolar conduction voltage drop. The distribution interval of the second doped region 3 along the second direction of the first surface region 101 is between 3 μm and 12 μm. For example, the distribution interval of the second doped region 3 along the second direction of the first surface region 101 can be 3 μm, 5 μm, 8 μm and 12 μm, etc. The specific distribution interval can be determined by the actual design requirement, which is not limited here. The first direction can be the X-axis direction as shown in Figure 1 , and the second direction can be the Z-axis direction as shown in Figure 1 , and the first surface region 101 is arranged in parallel with the plane formed by the first direction and the second direction.

[0052] An optional embodiment of the utility model, referring to Figure 3 As shown, the third width of the third doped region 4 in the first direction is between 10 μm and 20 μm. The first width of the first doped region 2 in the first direction is between 1 μm and 3 μm.

[0053] In the embodiment of the utility model, the first width W1 of the first doped region 2 in the first direction is set to 1 μm, 2 μm and 3 μm etc. The third width W2 of the third doped region 4 in the first direction is set to 10 μm, 15 μm and 20 μm etc. The third width can be selected within this width range according to the surge current bearing capacity of the diode. For example, the ratio of the third width to the first width can be 5.

[0054] In some embodiments, in the case of including at least two first surface regions 101 on the semiconductor substrate 1, the third doped regions 4 distributed on two first surface regions 101 at adjacent positions form a contact, thereby forming an overall doped region, and the overall width of the overall doped region in the first direction is equal to the cumulative value of two third widths, that is, the overall width of the overall doped region in the first direction is between 20 μm and 40 μm, including 20 μm and 40 μm etc.

[0055] In some embodiments, the junction depth of the first doped region 2 and the junction depth of the third doped region 4 can be adjusted according to the specifications of the diode, for example, the junction depth of the third doped region 4 is greater than the junction depth of the first doped region 2.

[0056] An optional embodiment of the utility model, the junction depth of the first doped region 2 is greater than the junction depth of the second doped region 3.

[0057] In the embodiment of the utility model, the junction depth of the first doped region 2 is greater than the junction depth of the second doped region 3, which can limit the maximum junction depth of the second doped region 3. The second doped region 3 is mainly used to improve the Schottky barrier height to reduce the bipolar conduction voltage drop of the diode, and it is not the main voltage bearing position.

[0058] Therefore, the problem of the positive unipolar conduction voltage drop of the diode increasing too much due to the Schottky barrier height being too large can be avoided, which is not conducive to the opening of the diode. Therefore, the forward conduction characteristics and reverse voltage withstand characteristics of the device are well balanced, and the unipolar conduction voltage drop is slightly increased while the forward bipolar conduction voltage drop is reduced.

[0059] An optional embodiment of the utility model, the doping concentration of the first doped region 2 and the third doped region 4 is between 1 × 10 18 cm -3 and 1 × 10 20 cm -3 (ion number per cubic centimeter).

[0060] The first doped area 2 and the third doped area 4 can have the same doping concentration, and the doping concentration is at least greater than 1*10 18 cm -3 . Thus, the first doped area 2 and the third doped area 4 can have high concentration doping, thereby improving the reverse voltage resistance performance of the diode and enhancing the anti-surge current performance.

[0061] In an optional embodiment, the doping concentration of the second doped area 3 is between 8*10 16 cm -3 and 2*10 17 cm -3 .

[0062] In the embodiment, when the doping concentration of the second doped area 3 is too high, a higher concentration of holes is introduced into the second doped area 3, thereby introducing an additional load center, increasing the forward unipolar conduction voltage drop and leakage current of the diode, and changing the internal electric field distribution of the diode, causing the electric field peak to deviate from the expected position and increasing the risk of diode breakdown.

[0063] In addition, when the doping concentration of the second doped area 3 is too low, the distribution of doped atoms is uneven, the ion activation rate is reduced and the residual resistivity is increased, affecting the operation stability of the diode. Therefore, the doping concentration of the second doped area 3 should be set within the range of 1% to 10% of the corresponding doping concentration of the first doped area 2.

[0064] In a preferred embodiment, the first surface area 101 is provided with at least two.

[0065] In the embodiment, as shown in Figure 1 , the first surface area 101 can be provided with at least two, so that the number of the first surface area 101 can be determined according to the specifications of the diode. Correspondingly, each first surface area 101 is respectively provided with a first doped area 2, a second doped area 3, and a third doped area 4 extending to the semiconductor substrate 1.

[0066] In an optional embodiment, as shown in Figure 6As shown, the semiconductor substrate 1 can include a drift layer 11, a buffer layer 12 and a substrate layer 13, wherein the buffer layer 12 is located between the drift layer 11 and the substrate layer 13, and the first surface region 101 is arranged on the end surface of the drift layer 11 away from the buffer layer 12. For example, the buffer layer 12 is obtained by performing first epitaxial growth on the upper surface of the substrate layer 13. The epitaxial growth is performed by using chemical vapor deposition technology, activating high-temperature gas molecules to promote chemical reaction on the upper surface of the substrate layer 13, generating silicon carbide compounds, and depositing these compounds on the upper surface of the substrate layer 13 to form a silicon carbide film, thereby obtaining the buffer layer 12. The substrate layer 13 can be one of 4H-SiC (tetrahydrogen silicon), 6H-SiC (hexahydrogen silicon) or 3C-SiC (cubic silicon carbide) single crystal substrate.

[0067] The thickness L1 of the substrate layer 13 is set to be between 325 μm and 375 μm. For example, the thickness of the substrate layer 13 can be 325 μm, 350 μm, 375 μm, etc. The thickness L2 of the buffer layer 12 is set to be between 0.5 μm and 1.5 μm. For example, the thickness of the buffer layer 12 can be 0.5 μm, 1 μm and 1.5 μm, etc. On the one hand, if the thickness of the buffer layer 12 is too thick, it will increase the internal resistance and thermal resistance of the semiconductor substrate 1, change the internal electric field distribution of the semiconductor substrate 1, and thus affect the key parameters such as the voltage resistance and leakage current of the diode. On the other hand, if the thickness of the buffer layer 12 is too thin, it will reduce the performance of the buffer layer 12 in blocking defects of the substrate layer 13, and thus affect the device performance and operation reliability of the diode. At the same time, if the thickness of the buffer layer 12 is too thin, it will also increase the process difficulty and production cost, and increase the product failure rate.

[0068] Then, the drift layer 11 is obtained by performing second epitaxial growth on the end surface of the buffer layer 12 away from the substrate layer 13 (which can also be referred to as the upper surface of the buffer layer 12), thereby forming the semiconductor substrate 1. The thickness L3 of the drift layer 11 is set to be between 5 μm and 8 μm. For example, the thickness of the drift layer 11 can be set to 5 μm, 6 μm and 8 μm, etc. Those skilled in the art can determine the specific thickness according to the actual design requirements, which is not limited here.

[0069] In summary, the utility model discloses a kind of Schottky diodes, the diode can include semiconductor substrate 1, at least one first doped region 2 and at least two second doped regions 3, the semiconductor substrate 1 includes first surface area 101, the first doped region 2 extends from the first surface area 101 into the semiconductor substrate 1, wherein, the first doped region 2 is obtained using the first doped concentration of aluminum ion doping.The second doped region 3 extends from the first surface area 101 on the semiconductor substrate 1, and the first doped region 2 and the second doped region 3, along the first direction of the first surface area 101 Staggered arrangement, the second doped region 3 is obtained using the second doped concentration of aluminum ion doping, and, the junction depth of the second doped region 3 is gradually reduced in the first direction, from the center of the first surface area 101 away, to the center of the first surface area 101 close.The third doped region 4 extends from the first surface area 101 into the semiconductor substrate 1, the third doped region 4 is obtained using the first doped concentration of aluminum ion doping, the area area of the third doped region 4 is greater than the area area of the first doped region 2.Thereby, the reverse voltage resistance performance of diode can be improved and the forward conduction voltage drop is reduced, the setting of different junction depths of the second doped region 3 can realize the continuous adjustable of Schottky barrier height.The Schottky barrier height of the second doped region 3 with smaller junction depth can ensure the forward conduction characteristic of diode.The second doped region 3 with larger junction depth can increase the Schottky barrier height, reduce the forward bipolar conduction voltage drop of diode, and reduce the on-state loss.

[0070] Referring to Figure 5 The utility model embodiment further discloses a manufacturing method of the Schottky diode, and the method comprises the following steps of:

[0071] S501, provide a semiconductor substrate 1, deposit plasma enhanced tetraethyl orthosilicate layer on the first surface area 101 of the semiconductor substrate 1.

[0072] In the utility model embodiment, the plasma enhanced tetraethyl orthosilicate layer (PETEOS layer) can be formed using chemical vapor deposition technology, which can be covered on the first surface area 101, so that the radiation resistance of the semiconductor substrate 1 can be improved.

[0073] S502, coat photoresist on the plasma enhanced tetraethyl orthosilicate layer, and form at least one first implantation window and at least two third implantation windows by photoetching.

[0074] S503, using the plasma enhanced tetraethyl orthosilicate layer as a mask, aluminum ions of the first doped concentration are injected into the first implantation window, to obtain the first doped region 2 extending from the first surface area 101 into the semiconductor substrate 1.

[0075] In the embodiment of the utility model, the photoresist can be coated on the end face of the PETEOS layer away from the first surface area 101, wherein the photoresist is also called photoresist, which is a resist film material whose solubility changes through the irradiation or radiation of ultraviolet light, electron beam, ion beam, X-ray and the like. Thus, the first implantation window, the second implantation window and the third implantation window can be obtained through the photoetching process. For example, after the photoresist is exposed and developed, the exposed part is dissolved, the unexposed part is not dissolved, and the dissolved area can form the first implantation window, or the second implantation window, or the third implantation window.

[0076] Therefore, as shown in FIG. 1, the PETEOS layer can be used as a mask to remove the photoresist, and the aluminum ions of the first doping concentration are implanted into the first implantation window to obtain the first doped region 2 extending from the first surface area 101 into the semiconductor substrate 1. Figure 7

[0077] S504, the aluminum ions of the first doping concentration are implanted into the third implantation window to obtain the third doped region 4 extending from the first surface area 101 into the semiconductor substrate 1.

[0078] In the embodiment of the utility model, after the ion implantation of the second doped region 3 is completed, the photoetching process described above can be repeated, the PETEOS layer is used as a mask to remove the photoresist, and the third implantation window is formed. Thus, the aluminum ions of the first doping concentration are implanted into the third implantation window to obtain the third doped region 4 extending from the first surface area 101 into the semiconductor substrate 1. The area of the third doped region 4 is greater than the area of the first doped region 2.

[0079] S505, a second doping step is performed, the second doping step includes forming at least two second implantation windows through photoetching, and implanting the aluminum ions of the second doping concentration into the second implantation window with the plasma-enhanced tetraethyl orthosilicate layer as a mask to obtain the second doped region 3 extending from the first surface area 101 into the semiconductor substrate 1, and the first doped region 2 and the second doped region 3 are staggered along the first direction of the first surface area 101, wherein the first doping concentration is greater than the second doping concentration.

[0080] In the embodiment of the utility model, after the ion implantation of the first doped region 2 is completed, the photoetching process described above can be repeated, the PETEOS layer is used as a mask to remove the photoresist, and the second implantation window is formed. Referring to FIG. 2, the aluminum ions of the second doping concentration are implanted into the second implantation window to obtain the second doped region 3 extending from the first surface area 101 into the semiconductor substrate 1. Figure 8 ​As shown, the second implantation window is implanted with aluminum ions of a second doping concentration to obtain a second doped region 3 extending into the semiconductor substrate 1 from the first surface region 101. The first doped region 2 and the second doped region 3 after implantation are staggered in the first direction of the first surface region 101. That is, in the first direction, at least one first doped region 2 is arranged between two adjacent second doped regions 3.

[0081] S506, repeating the second doping step to obtain at least two second doped regions 3, so that the junction depth of the second doped region 3 gradually decreases from away from the center of the first surface region 101 to close to the center of the first surface region 101 in the first direction.

[0082] In the embodiment of the utility model, the junction depth of the second doped region 3 gradually decreases from away from the center of the first surface region 101 to close to the center of the first surface region 101 in the first direction. Wherein, by using different implantation energies and implanting aluminum ions according to the second doping concentration in the process of executing the second doping step each time, the second doped region 3 with different junction depths can be formed.

[0083] An optional embodiment of the utility model, the first implantation window is implanted with aluminum ions of a first doping concentration to obtain a first doped region 2 extending into the semiconductor substrate 1 from the first surface region 101, comprising:

[0084] The first implantation window is implanted with aluminum ions of a first doping concentration between 1x10 18 cm -3 and 1x10 20 cm -3 to obtain a first doped region 2 extending into the semiconductor substrate 1 from the first surface region 101.

[0085] In the embodiment of the utility model, the first doped region 2 is mainly used to improve the reverse withstand voltage and reduce the leakage current of the MPS diode. The doping concentration of the P+ ion is usually greater than 10 18 cm -3 or equal to 10 18 cm -3The third doped region 4 is used to improve the reverse voltage resistance and surge current resistance of the diode, and reduce the forward conduction voltage drop of the diode. In some embodiments, the implantation energy of P+ ions is between 40KeV and 400KeV (Kilo electron volts), wherein the implantation energy can be adjusted according to the specifications of the diode to ensure the balance between the conduction voltage drop and the reverse leakage current. For example, the higher the implantation energy, the deeper the junction depth of the first doped region 2 or the third doped region 4.

[0086] The doping concentration of the first doped region 2 and the doping concentration of the third doped region 4 can be kept consistent, and the doping concentration is at least greater than 1*10 18 cm -3 . Thus, the first doped region 2 and the third doped region 4 can be high-concentration doped (also referred to as P+ ion doping), thereby improving the reverse voltage resistance of the diode and enhancing the surge current resistance.

[0087] An optional utility model embodiment, the second doped region 3 extending from the first surface region 101 into the semiconductor substrate 1 is obtained by injecting aluminum ions of a second doping concentration into the second implantation window, comprising:

[0088] The second doped region 3 extending from the first surface region 101 into the semiconductor substrate 1 is obtained by injecting aluminum ions of a second doping concentration between 8*10 16 cm -3 and 2*10 17 cm -3 .

[0089] In the utility model embodiment, when the doping concentration of the second doped region 3 is too high, it will introduce a higher concentration of holes in the second doped region 3, thereby introducing additional negative load centers, increasing the forward unipolar conduction voltage drop and leakage current of the diode, and also changing the internal electric field distribution of the diode, making the electric field peak deviate from the expected position and increasing the risk of diode breakdown.

[0090] In addition, when the doping concentration of the second doped region 3 is too low, it will cause uneven distribution of doped atoms, reduce ion activation rate and increase residual resistivity, affecting the operation stability of the diode. Therefore, the second doping concentration corresponding to the second doped region 3 should be set within the interval of 1% to 10% of the doping concentration corresponding to the first doped region 2. Therefore, the aluminum ions of the second doping concentration can also be referred to as P- ions (low-concentration aluminum ions).

[0091] In some embodiments, the P- ion implantation energy is between 40KeV and 300KeV (Kilo electron volt), and the implantation energy of the second doped region 3 is less than that of the first doped region 2, so that the junction depth of the first doped region 2 is greater than that of the second doped region 3, and the maximum junction depth of the second doped region 3 is limited. The second doped region 3 is mainly used to improve the Schottky barrier height to reduce the bipolar conduction voltage drop of the diode, which is not the main voltage bearing position.

[0092] Therefore, the Schottky barrier height can be avoided to be too large, which leads to the increase of the forward unipolar conduction voltage drop of the diode, which is not conducive to the opening of the diode. The forward conduction characteristic and reverse voltage withstand characteristic of the device are well balanced, which ensures that the unipolar conduction voltage drop is slightly increased, and the forward bipolar conduction voltage drop is reduced.

[0093] In some embodiments, referring to Figure 6 As shown in the figure, the semiconductor substrate 1 can include a drift layer 11, a buffer layer 12 and a substrate layer 13, wherein the buffer layer 12 is located between the drift layer 11 and the substrate layer 13, and the first surface region 101 is arranged on the end surface of the drift layer 11 away from the buffer layer 12. For example, the buffer layer 12 is obtained by performing first epitaxial growth on the upper surface of the substrate layer 13. The epitaxial growth is achieved by using chemical vapor deposition technology, activating high-temperature gas molecules to promote chemical reaction on the upper surface of the substrate layer 13, generating silicon carbide compounds, and depositing these compounds on the upper surface of the substrate layer 13 to form a silicon carbide film, thereby obtaining the buffer layer 12. The substrate layer 13 can be one of 4H-SiC (tetrahydrogen silicon), 6H-SiC (hexahydrogen silicon) or 3C-SiC (cubic silicon carbide) single crystal substrate.

[0094] The thickness L1 of the substrate layer 13 is set to be between 325μm and 375μm (microns). For example, the thickness of the substrate layer 13 can be 325μm, 350μm, 375μm, etc. The thickness L2 of the buffer layer 12 is set to be between 0.5μm and 1.5μm (microns). For example, the thickness of the buffer layer 12 can be 0.5μm, 1μm and 1.5μm, etc. On the one hand, the thickness of the buffer layer 12 can be avoided to be too thick, which leads to the increase of internal resistance and thermal resistance in the semiconductor substrate 1, changes the internal electric field distribution in the semiconductor substrate 1, and thus affects the key parameters such as voltage resistance and leakage current of the diode. On the other hand, the thickness of the buffer layer 12 is too thin, which leads to the decline of its performance in blocking defects of the substrate layer 13, and thus affects the device performance and operation reliability of the diode. At the same time, the thickness of the buffer layer 12 is too thin, which also increases the process difficulty and production cost, and increases the product failure rate.

[0095] Then, a second epitaxial growth is performed on the end surface of the buffer layer 12 away from the substrate layer 13 (which can also be referred to as the upper surface of the buffer layer 12), to obtain a drift layer 11, thereby forming the semiconductor substrate 1. The thickness L3 of the drift layer 11 is set to be between 5 μm and 8 μm. For example, the thickness of the drift layer 11 can be set to 5 μm, 6 μm, 8 μm, etc., and the specific thickness can be determined by the actual design requirement, which is not limited herein. The doping concentration of the drift layer 11 is set to be between 5 x 1016 cm-3 and 5 x 1018 cm-3. 15 cm -3 -3 16 cm -3 .

[0096] That is, the thickness of the drift layer 11 is greater than the thickness of the buffer layer 12, and the thickness of the drift layer 11 is less than the thickness of the substrate layer 13. The thickness ratio in the following figures is only for reference, and the specific thickness is limited as described above, which is not limited herein.

[0097] In some optional utility model embodiments, after the first doped region 2, the second doped region 3 and the third doped region 4 are formed, a carbon film can be formed on the upper surface of the drift layer 11 (the first surface region 101), which plays a protective role on the surface of the drift layer 11 during thermal annealing, and then thermal annealing is performed to activate the ions in different doped regions and then remove the carbon film.

[0098] Then, a metal layer is sputtered on the upper surface of the drift layer 11, wherein the metal layer material can be at least one of the following materials: nickel, titanium and nickel-titanium alloy. Photoresist is spin-coated on the upper surface of the drift layer 11, and after photoetching and development, the exposed metal layer is removed by dry etching, and then the photoresist is removed and the metal layer is subjected to thermal annealing treatment to form an anode ohmic metal contact layer 5. As shown in Figure 9 , the thickness L4 of the anode ohmic metal contact layer 5 is set to be between 0.1 μm and 0.5 μm.

[0099] A titanium metal layer is sputtered on the upper surface of the drift layer 11, an aluminum metal layer is sputtered above the titanium metal layer, and then photoresist is spin-coated on the upper surface of the aluminum metal layer. After photoetching and development, the exposed aluminum metal layer is removed by dry etching or wet etching. The exposed titanium metal layer is removed by dry etching. Then the photoresist is removed and the metal layer is subjected to thermal annealing treatment to form an anode metal layer 6 composed of titanium metal and aluminum metal layers, as shown in Figure 9 , wherein the thickness L5 of the anode metal layer 6 is set to be between 4 μm and 6 μm. The anode metal layer 6 and the semiconductor substrate form a Schottky barrier as described in the above utility model embodiments.

[0100] The lower surface of the substrate layer 13 (the end surface of the substrate layer 13 away from the buffer layer 12) is subjected to substrate cutting, so as to thin the thickness of the substrate layer 13 to between 100 μm and 180 μm. The cutting method can be one of the following: mechanical grinding, chemical etching, ICP (Inductively Coupled Plasma) etching, and acoustic wave cutting. Considering the difficulty of controlling the substrate growth quality and the limitation of manufacturing cost, the method of forming the substrate layer 13 is mainly to cut a plurality of substrates from a bulk silicon carbide ingot. Since different devices have different requirements for the thickness of the substrate, the thickness of the substrate can be adjusted in the subsequent process to meet the requirements of the electrical parameters of the device. Therefore, it is easier to precisely control the device parameters by cutting a thicker substrate layer 13 and then thinning it according to different requirements. Thus, the resistance of the substrate layer 13 can be reduced by reducing the thickness of the substrate layer 13.

[0101] Finally, a cathode ohmic metal contact layer is formed on the lower surface of the thinned substrate layer 13 by sputtering or evaporation, and an aluminum metal layer is deposited on the lower surface of the cathode ohmic metal contact layer to form a cathode metal layer 8 composed of the cathode ohmic metal contact layer and the aluminum metal layer, as shown in Figure 2 、 Figure 3 and Figure 4 The material of the cathode ohmic metal contact layer is at least one of nickel, titanium, and silver. The anode metal layer 6 and the cathode metal layer 8 can be used as the pins of a diode.

[0102] In summary, the utility model discloses a kind of Schottky diodes, and the utility model embodiment can include semiconductor substrate 1, at least one first doped region 2 and at least two second doped regions 3, the semiconductor substrate 1 includes first surface area 101, the first doped region 2 extends from the first surface area 101 into the semiconductor substrate 1, wherein, the first doped region 2 is obtained using the first doping concentration of aluminum ion doping.The second doped region 3 extends from the first surface area 101 to the semiconductor substrate 1, and the first doped region 2 and the second doped region 3, along the first direction of the first surface area 101 Staggered arrangement, the second doped region 3 is obtained using the second doping concentration of aluminum ion doping, and, the junction depth of the second doped region 3 is gradually reduced in the first direction, from the center away from the first surface area 101, to the center close to the first surface area 101, the first doping concentration is greater than the second doping concentration.The third doped region 4 extends from the first surface area 101 into the semiconductor substrate 1, the third doped region 4 is obtained using the first doping concentration of aluminum ion doping, the area of the third doped region 4 is greater than the area of the first doped region 2.Thereby, the reverse voltage resistance performance of diode can be improved and the forward conduction voltage drop is reduced, wherein, the setting of different junction depths of the second doped region 3 can realize the continuous adjustment of Schottky barrier height.The Schottky barrier height of the second doped region 3 with smaller junction depth is lower, and the interval distribution of the second doped region 3 can ensure the forward conduction characteristic of diode.The second doped region 3 with larger junction depth can increase the Schottky barrier height, reduce the forward bipolar conduction voltage drop of diode, and reduce the on-state loss.

[0103] Each embodiment in the specification is described in a progressive manner, and each embodiment focuses on the difference from other embodiments, and the same or similar parts between each embodiment can be referred to each other.

[0104] As can be readily imagined by those skilled in the art, any combination application of each of the above embodiments is feasible, so any combination of each of the above embodiments is an embodiment of the utility model, but due to the limitation of length, the specification will not be described in detail here.

[0105] In the specification provided herein, a large number of specific details are described. However, it can be understood that the embodiments of the utility model can be practiced without these specific details. In some examples, well-known methods, structures and techniques are not shown in detail, so as not to obscure the understanding of the specification.

[0106] Similarly, it is to be understood that the embodiments of the application can include more steps and / or options than those expressly described to perform a particular described function and / or option. Furthermore, the steps and / or options as described in the examples above do not have to be performed in the precise order described.

[0107] Furthermore, those skilled in the art will recognize that, in keeping with the practice of the art disclosed herein, wherein like numerals represent like components throughout the several views, that the components of the application can be substituted with other like components falling within the scope of the application and that the application encompasses any and all embodiments of the following claims.

Claims

1. A Schottky diode, characterized by, The Schottky diode comprises: a semiconductor substrate (1) comprising a first surface region (101); at least one first doped region (2) extending from the first surface region (101) into the semiconductor substrate (1), wherein the first doped region (2) is doped with aluminum ions at a first doping concentration; at least two second doped regions (3) extending from the first surface region (101) onto the semiconductor substrate (1), and the first doped region (2) and the second doped regions (3) are staggered along a first direction of the first surface region (101), the second doped regions (3) are doped with aluminum ions at a second doping concentration, and the junction depth of the second doped regions (3) gradually decreases from the center away from the first surface region (101) to the center close to the first surface region (101) in the first direction, wherein the first doping concentration is greater than the second doping concentration; at least two third doped regions (4) extending from the first surface region (101) into the semiconductor substrate (1), wherein the third doped regions (4) are doped with aluminum ions at a first doping concentration, and the area of the third doped regions (4) is greater than the area of the first doped regions (2).

2. The Schottky diode of claim 1, wherein The third doped regions (4) are distributed on both sides of the first direction of the first surface region (101).

3. The Schottky diode of claim 1, wherein In the first direction of the first surface region (101), the third doped regions (4) are in contact with the second doped regions (3), and the second doped regions (3) are in contact with the first doped regions (2).

4. The Schottky diode of claim 1, wherein The second doped regions (3) are spaced apart along a second direction of the first surface region (101), wherein the first direction and the second direction are perpendicular to each other.

5. The Schottky diode of claim 4, wherein, The distribution interval of the second doped regions (3) along the second direction of the first surface region (101) is between 3μm and 12μm.

6. The Schottky diode of claim 1, wherein The junction depth of the first doped regions (2) is greater than the junction depth of the second doped regions (3).

7. The Schottky diode of claim 1, wherein The first width of the first doped regions (2) in the first direction is between 1μm and 3μm.

8. The Schottky diode of claim 7, wherein, The third width of the third doped regions (4) in the first direction is between 10μm and 20μm.

9. The Schottky diode of claim 1, wherein, The first surface region (101) is provided with at least two.

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