Semiconductor device

Abstract

A semiconductor device includes a separation wall and a plurality of liners including a first liner and a second liner between a first fin and a second fin. The first liner is closer to at least one of the metal gate layers and the second liner is closer to the separation wall. An inner spacer layer is around the at least one metal gate layer, the first liner, and the second liner. The at least one metal gate layer has a first critical dimension measured between the inner spacer layers at an end closest to a first liner, and the first liner has a second critical dimension measured between the inner spacer layers, the second critical dimension being equal to the first critical dimension.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to semiconductor devices. BACKGROUND

[0002] Semiconductor devices are used in a variety of electronic applications, such as (for example) personal computers, cell phones, digital cameras, and other electronic equipment. Semiconductor devices are typically fabricated by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor material layers over a semiconductor substrate and patterning the various material layers using lithography to form circuit elements and components on the material layers.

[0003] The semiconductor industry continues to seek improved methods of increasing the integration density of various electronic elements (e.g., transistors, diodes, resistors, capacitors, etc.) by continually reducing the minimum feature size. However, as the minimum feature size is reduced, additional problems arise that need to be addressed. SUMMARY

[0004] In some implementations of the present disclosure, a semiconductor device includes a first fin and a second fin, the first fin having a channel region including a plurality of channel slices and a plurality of metal gate layers; a spacer wall and a plurality of spacers, the plurality of spacers including a first spacer and a second spacer between the first fin and the second fin, wherein the first spacer is closer to at least one of the plurality of metal gate layers and the second spacer is closer to the spacer wall; and internal spacer layers around the at least one of the plurality of metal gate layers, the first spacer, and the second spacer; wherein the at least one of the plurality of metal gate layers has a first critical dimension measured between the internal spacer layers at an end closest to a first spacer, and the first spacer has a second critical dimension measured between the internal spacer layers, the second critical dimension being equal to the first critical dimension.

[0005] In some implementations of the present disclosure, a semiconductor device includes a first fin and a second fin, the first fin having a channel region including a plurality of channel slices and a plurality of metal gate layers; a spacer wall and a plurality of spacers, the plurality of spacers including a first spacer and a second spacer between the first fin and the second fin, wherein the first spacer is closer to at least one of the plurality of metal gate layers and the second spacer is closer to the spacer wall; and internal spacer layers around the at least one of the plurality of metal gate layers, the first spacer, and the second spacer; wherein the at least one of the plurality of metal gate layers has a first critical dimension measured between the internal spacer layers at an end closest to a first spacer, and the first spacer has a second critical dimension measured between the internal spacer layers, an absolute value of a difference between the second critical dimension and the first critical dimension is less than or equal to 5 angstroms.

[0006] In some implementations of the present disclosure, a semiconductor device includes: a first fin and a second fin, the first fin having a channel region including a plurality of channel tiers and a plurality of metal gate tiers; a separation wall and a plurality of liners, the plurality of liners including a first liner and a second liner between the first fin and the second fin, wherein the first liner is closer to at least one of the plurality of metal gate tiers and the second liner is closer to the separation wall; and internal spacer layers around the at least one of the plurality of metal gate tiers, the first liner, and the second liner; wherein the at least one of the plurality of metal gate tiers has a first critical dimension measured between the internal spacer layers at an end closest to the first liner, and the first liner has a second critical dimension measured between the internal spacer layers, the second critical dimension being equal to the first critical dimension; wherein the second liner has different critical dimensions at an end closest to the first liner and at an end closest to the separation wall, respectively. BRIEF DESCRIPTION OF DRAWINGS

[0007] Various aspects of the present disclosure can be best understood with reference to the accompanying drawings. It should be noted that, in the description and drawings, like parts are marked with the same reference numerals. According to standard practice, the various features can not be drawn to scale. In fact, the dimensions of the various features can be arbitrarily increased or decreased for the sake of discussion.

[0008] FIG. 1A A perspective view of a portion of a semiconductor device corresponding to line X1-X1' of

[0009] FIG. 1B A perspective view of a portion of a semiconductor device corresponding to line X2-X2' of FIG. 1A

[0010] A perspective view of a portion of a semiconductor device corresponding to line X2-X2' of FIG. 1C FIG. 1B A perspective view of a portion of a semiconductor device corresponding to line X2-X2' of

[0011] FIG. 1D FIG. 1B A perspective view of a portion of a semiconductor device corresponding to line X2-X2' of

[0012] FIG. 2 is a flowchart depicting an example method of semiconductor manufacturing including manufacturing a multi-gate device, in accordance with some embodiments;

[0013] FIGS. 3A-3L are cross-sectional side views of embodiments of example semiconductor devices at various stages of an example manufacturing process, in accordance with some embodiments;​​

[0014] FIGS. 4A-4F is a cross-sectional side view of an embodiment of an example semiconductor device at various manufacturing stages in an example manufacturing process to form a separation wall and multiple liners, according to some embodiments;

[0015] FIGS. 5A-5D is a cross-sectional schematic of different stages of a manufacturing process to illustrate recessing of a sacrificial epitaxial layer and liner layers to achieve leak prevention, according to some embodiments;

[0016] FIGS. 6A-6C is a cross-sectional schematic of different shapes of material layers around a metal gate layer that can achieve leak prevention due to recessing of liners, including a first liner and a second liner, according to some embodiments;

[0017] FIGS. 7A-7C is a cross-sectional schematic of different shapes of material layers around a metal gate layer that can achieve leak prevention due to recessing of liners, including a first liner and a second liner, according to some embodiments;

[0018] FIGS. 8A-8B is a cross-sectional schematic of different shapes of material layers around a metal gate layer that can achieve leak prevention due to recessing of liners, including a first liner and a second liner, according to some embodiments.

[0019]

SYMBOL DESCRIPTION

[0020] 323: liner

[0021] 100, 300: device

[0022] 102, 104, 106, 108, 320, 320a, 320b, 320c, 320d: fin

[0023] 110, 302, 403: substrate

[0024] 112: STI

[0025] 114: dielectric separation wall

[0026] 116: epitaxial stack region

[0027] 118, 314, 502: sacrificial epitaxial layer

[0028] 120: channel epitaxial layer

[0029] 316: channel epitaxial layer / nanosheet

[0030] 122, 504, 606, 706, 806: first liner

[0031] 124, 506, 608, 708, 808: second liner

[0032] 126, 336, 510: cavity

[0033] 200: method

[0034] 202, 204, 206, 208, 210, 212, 214, 216, 218, 220, 222, 224, 226, 228, 230: block

[0035] 312: epitaxial stack

[0036] 321, 508, 610, 710, 810: separation wall 322: STI feature

[0037] 324: sacrificial gate structure

[0038] 332: gate sidewall spacer

[0039] 334: recess

[0040] 338: internal spacer material layer

[0041] 340: epitaxial S / D feature

[0042] 342: CESL

[0043] 344: ILD layer

[0044] 354: gate trench

[0045] 360: gate structure

[0046] 362: interface layer

[0047] 364: high-k dielectric layer

[0048] 402: hard mask

[0049] 404: liner material

[0050] 406: wall material

[0051] 408: dielectric material

[0052] 602, 702, 802: HKMG layer

[0053] 604, 704, 804: internal spacer layer

[0054] 611: second end

[0055] 612: width

[0056] 613: first end

[0057] 614: inner spacer width

[0058] 616: inner spacer width

[0059] 712, 812: first CD

[0060] 714, 814: second CD

[0061] 716, 816: third CD

[0062] 818: fourth CD

[0063] X1-X1', X2-X2': line DETAILED DESCRIPTION

[0064] The following disclosure provides many different embodiments, or examples, for implementing different characteristics of the provided subject matter. Specific examples of elements and configurations are described below to provide a thorough description of embodiments. Of course, these are simply examples, and are not intended to be limiting.

[0065] For the sake of brevity, conventional techniques related to semiconductor device manufacturing can not be described in detail herein. In addition, the various tasks and processes can be at least partially implemented by a more general-purpose system or a more complete program. Thus, the more general purpose program or system can be manipulated by the user to at least partially configure it for the tasks described herein. The various processes and functions described herein can be used with conventional and / or custom components and processes. Conventional techniques can be particularly related to semiconductor device manufacturing, and thus, for brevity, many conventional techniques will only be mentioned briefly herein or will be omitted entirely without providing the well-known details. As will be readily appreciated by those skilled in the art, the structures disclosed herein can be employed within a variety of technologies and can be incorporated into various semiconductor devices and products. Additionally, it should be noted that semiconductor device structures include different numbers of elements, and a single element shown in the illustrations can represent multiple elements.

[0066] It should be understood that, although the terms first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present disclosure.

[0067] Moreover, spatially relative terms, such as "above", "over", "upper", "top", "bottom", "under", "lower", "beneath", "below", "down", "up", "right", "left", "vertical", "horizontal", "side", "end", "furthest", "nearest" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the figures. The devices can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. When a spatially relative term is used to describe a first component's relationship to a second component, the first component can be directly in contact with the second component or can have intervening components or layers therebetween.

[0068] Furthermore, the disclosure can repeat reference numerals and / or letters in various instances. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and / or configurations discussed.

[0069] It should be noted that references to "one embodiment", "an embodiment", "example embodiment", "exemplary", "example", etc., indicate that the described embodiment can include a particular feature, structure, or characteristic, but every embodiment can not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases are not necessarily indicative of a

[0070] In certain embodiments herein, a "layer of material" is a layer that includes at least 50% by weight of the identified material (e.g., at least 60% by weight of the identified material, at least 75% by weight of the identified material, at least 90% by weight of the identified material, at least 95% by weight of the identified material, or at least 99% by weight of the identified material); and is a layer that is a "material" that includes at least 50% by weight of the identified material (e.g., at least 60% by weight of the identified material, at least 75% by weight of the identified material, at least 90% by weight of the identified material, at least 95% by weight of the identified material, or at least 99% by weight of the identified material). For example, in certain embodiments, each of a layer of aluminum and a layer with aluminum is a layer that is at least 50% by weight, at least 60% by weight, at least 75% by weight, at least 90% by weight, at least 95% by weight, or at least 99% by weight of aluminum.

[0071] It is to be understood that the phraseology or terminology herein is for the purpose of description and not of limitation, such that the terminology or phraseology of the present specification is to be interpreted by those skilled in relevant art in light of the teachings and

[0072] The following disclosure provides many different embodiments, or "examples," for implementing different characteristics of the disclosed subject matter. Specific examples are described in the following description to provide a thorough description of the above-mentioned technologies. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature over or on a second feature can include embodiments where the first feature and the second feature are formed directly contacting one another, and can also include embodiments where additional features can be formed between the first feature and the second feature such that the first feature and the second feature can not be directly contacting one another. Throughout this document, same reference numerals are used to describe similar, but not necessarily identical, elements throughout the various figures and embodiments.

[0073] Various embodiments are discussed herein in the specific context of forming semiconductor structures including fin-like field-effect transistors (FinFET) devices. For example, the semiconductor structures can be complementary metal-oxide-semiconductor (CMOS) devices including P-type metal-oxide-semiconductor (PMOS) FinFET devices and N-type metal-oxide-semiconductor (NMOS) FinFET devices. Embodiments will now be described with respect to specific examples including FinFET fabrication processes. However, embodiments are not limited to the examples provided herein, and these concepts can be implemented in various embodiments. Thus, various embodiments can be applied to other semiconductor devices / processes, such as planar transistors and the like. In addition, some embodiments discussed herein are discussed in the context of devices formed using a gate-last process. In other embodiments, a gate-first process can be used.

[0074] Although various figures illustrate various embodiments of semiconductor devices, additional features can be added to the semiconductor devices depicted in the various figures, and some of the features described below can be replaced, modified, or eliminated in other embodiments of semiconductor devices.

[0075] Additional operations can be provided before, during, and / or after the stages described in these embodiments. Some of the stages described can be replaced or eliminated in various embodiments. Additional features can be added to the semiconductor device structures. Some of the features described below can be replaced or eliminated in various embodiments. Although some embodiments are discussed where operations are performed in a particular order, the operations can be performed in another logical order.

[0076] As used herein, a "layer" is a region, such as a region including any boundaries, and does not necessarily include a uniform thickness. For example, a layer can be a region that includes at least some variation in thickness.

[0077] This disclosure relates generally to semiconductor devices and fabrication thereof, and more specifically to multiple gate devices. Multiple gate devices include those transistors in which a gate structure is formed on at least two sides of a channel region. These multiple gate devices can include n-type metal oxide semiconductor devices or p-type metal oxide semiconductor multiple gate devices. Specific examples herein can be presented and referred to herein as a type of multiple gate transistor referred to as a gate-all-around (GAA) device. GAA devices include any device in which its gate structure or a portion thereof is formed on 4 sides of a channel region (e.g., encloses a portion of the channel region). Devices presented herein also include embodiments having a channel region disposed in a nanosheet channel, a nanowire channel, a strip channel, and / or another suitable channel configuration. Embodiments of devices that can have one or more channel regions (e.g., nanosheets) associated with a single continuous gate structure are presented herein. However, one of ordinary skill in the art will recognize that the teachings can apply to a single channel or any number of channels such as a fin structure of a FinFET device. One of ordinary skill in the art can recognize other examples of semiconductor devices that can benefit from aspects of the present disclosure.

[0078] Gate-all-around (GAA) silicon nanosheet structures have been recognized as an excellent candidate for achieving improved power performance and area scaling compared to other FinFET technologies. In particular, GAA structures provide high drive current due to a wide effective channel width while maintaining short channel control.

[0079] FIGS. 1A-1D Various views of a GAA semiconductor device according to some embodiments of the present disclosure are shown. FIG. 1A A perspective view of a semiconductor device according to some embodiments of the present disclosure is shown. FIG. 1B A perspective view of a portion of a semiconductor device according to some embodiments of the present disclosure is shown. FIG. 1A A perspective view of a portion of a semiconductor device according to some embodiments of the present disclosure is shown. FIG. 1C A perspective view of a portion of a semiconductor device according to some embodiments of the present disclosure is shown. FIG. 1B A cross-sectional view of a line X2-X2' of a semiconductor device according to some embodiments of the present disclosure is shown. FIG. 1D A perspective view of a portion of a semiconductor device according to some embodiments of the present disclosure is shown. FIG. 1Bthe cross-sectional view corresponding to the line X2-X2' of

[0080] FIG. 1A A portion of the semiconductor device 100 including a plurality of fins 102, 104, 106, and 108 on a substrate 110 is shown. The fins 104, 106, and 108 are separated from each other via an isolation structure such as a shallow trench isolation (STI) 112. The fins 102 and 104 are separated from each other via an isolation structure such as a dielectric spacer 114. FIG. 1A Each fin in the example includes an epitaxial stack region 116 that includes alternating epitaxial layers.

[0081] As shown in FIG. 1B The alternating epitaxial layers of the epitaxial stack region 116 include a sacrificial epitaxial layer 118 of a first composition that is interposed by a channel epitaxial layer 120 of a second composition, as shown in

[0082] As shown in FIG. 1C The sacrificial epitaxial layer 118 is recessed to form a cavity 126 around the sacrificial epitaxial layer 118, as shown in However, the first liner 122 can provide a current leakage path between a metal gate layer that replaces the sacrificial epitaxial layer 118 later and a source / drain region that is formed later to oppose the cavity 126. In this disclosure, the source and the drain are used interchangeably and their structures are substantially the same.

[0083] As shown in FIG. 1D To prevent the current leakage path between the metal gate layer that is formed later and the source / drain region that is formed later, the liner (e.g., the first liner 122 and the second liner 124) is also recessed to extend the cavity 126 to the dielectric spacer 114, as shown in The inner spacer material that is formed later in the cavity 126 can prevent the current leakage path between the metal gate layer that is formed later and the source / drain region that is formed later.

[0084] FIG. 2is a flow diagram depicting example method 200 of semiconductor fabrication including fabricating a multi-gate device including a recessed liner layer disposed between a sacrificial epitaxial layer and dielectric separation walls according to various aspects of the present disclosure. As used herein, the term "multi-gate device" is used to describe a device (e.g., a semiconductor transistor) having at least some gate material disposed on multiple sides of at least one channel of the device. In some examples, a multi-gate device can be referred to as a GAA device having gate material disposed on four sides of at least one channel member of the device. A channel member can be referred to as a "nanowire" or "nanosheet," which are used herein to designate any material portion having a nanoscale or even a microscale dimension and having an elongated shape, regardless of the cross-sectional shape of the portion. Thus, the term "nanowire" or "nanosheet" as used herein designates both elongated material portions and beams or strips that include, for example, a circular or substantially circular cross-section, as well as beam-shaped or strip-shaped material portions that include, for example, a cylindrical shape or a substantially rectangular cross-section.

[0085] In conjunction FIGS. 3A-3L Described FIG. 2 , FIGS. 3A-3L Semiconductor devices 300 or structures at various stages of fabrication according to some embodiments are described. Method 200 is merely an example and is not intended to limit the present disclosure beyond the content explicitly set forth in the claims. Additional steps can be provided before, during, and after method 200, and some of the steps described can be replaced or eliminated, for additional embodiments of the method 200. Additional features can be added to the semiconductor devices 300 depicted in the various figures, and some of the features described below can be replaced, modified, or eliminated in other embodiments.

[0086] As with other method embodiments and exemplary devices discussed herein, it is to be understood that portions of the semiconductor devices can be fabricated by semiconductor technology process flows, and thus some processes are only briefly described herein. Additionally, exemplary semiconductor devices can include various other devices and features, such as other types of devices, such as additional transistors, bipolar junction transistors, resistors, capacitors, inductors, dials, fuses, and / or other logic devices, etc., but are simplified for better understanding of the concepts of the present disclosure. In some embodiments, exemplary devices include multiple semiconductor devices (e.g., transistors), including PFETs, NFETs, etc., that can be interconnected. Moreover, it is noted that process steps of method 200 include any description given with reference to the various figures (as with the remainder of the methods and exemplary figures provided in the present disclosure), are merely exemplary, and are not intended to be limiting beyond what is specifically recited in the appended claims.

[0087] FIGS. 3A-3Lare cross-sectional side views of embodiments of example semiconductor devices 300 at various stages of an example fabrication process according to some embodiments. In some figures, some reference numbers for elements or features illustrated in these figures can be omitted to avoid obscuring other elements or features; this is to facilitate the depiction of the various figures.

[0088] At block 202, the example method 200 includes providing a substrate. Referring to FIG. 3A In examples of block 202, the substrate 302 is provided to form the multi-gate device 300. In some embodiments, the substrate 302 can be a semiconductor substrate, such as a silicon (Si) substrate. In some embodiments, the substrate 302 includes a single-crystalline semiconductor layer on at least a surface portion thereof. The substrate 302 can comprise a single-crystalline semiconductor material such as, but not limited to, Si, Ge, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, and InP. Alternatively, the substrate 302 can include compound and / or alloy semiconductors. The substrate 302 can include various layers formed on a semiconductor substrate, including conductive or insulating layers. The substrate 302 can include various doping configurations according to design requirements. For example, different doping profiles (e.g., n-well, p-well) can be formed on the substrate 302 in regions designed for different device types (e.g., n-type field effect transistor (NFET), p-type field effect transistor (PFET)). Suitable doping can include ion implantation and / or diffusion processes of dopants. The substrate 302 has isolation features (e.g., shallow trench isolation (STI) features) interposed to provide regions of different device types. In addition, the substrate 302 can be strained to achieve performance enhancement, can include a silicon-on-insulator (SOI) structure, and / or have other suitable enhancement features.

[0089] At block 204, the example method 200 then includes forming an epitaxial stack including one or more epitaxial layers over the substrate. Referring to FIG. 3BIn the example of FIG. 2A, a sacrificial epitaxial layer 214 is formed over the substrate 202. The sacrificial epitaxial layer 214 is formed of a first composition. In embodiments, the sacrificial epitaxial layer 214 is formed of SiGe. However, other embodiments are possible, including those embodiments that provide a first composition that has a different oxidation rate and / or etch selectivity. In some embodiments, the sacrificial epitaxial layer 214 includes SiGe. However, other embodiments are possible, including those embodiments that provide a first composition that has a different oxidation rate and / or etch selectivity. In some embodiments, the sacrificial epitaxial layer 214 includes SiGe, and the Si oxidation rate of the channel epitaxial layer 216 is less than the SiGe oxidation rate of the sacrificial epitaxial layer 214, where the channel epitaxial layer 216 includes Si. It should be noted that three (3) layers are illustrated in FIG. 2A: the sacrificial epitaxial layer 214 and each of the channel epitaxial layer 216, merely for illustrative purposes and not intended to be limiting beyond what is specifically recited in the claims. In various embodiments, any number of epitaxial layers can be formed in the epitaxial stack 212; the number of layers depends on the desired number of channel regions of the device 200. In some embodiments, the number of channel epitaxial layers 216 is between 2 and 10, such as 3, 4, or 5. FIG. 3B In the example of FIG. 2A, a sacrificial epitaxial layer 214 is formed over the substrate 202. The sacrificial epitaxial layer 214 is formed of a first composition. In embodiments, the sacrificial epitaxial layer 214 is formed of SiGe. However, other embodiments are possible, including those embodiments that provide a first composition that has a different oxidation rate and / or etch selectivity. In some embodiments, the sacrificial epitaxial layer 214 includes SiGe. However, other embodiments are possible, including those embodiments that provide a first composition that has a different oxidation rate and / or etch selectivity. In some embodiments, the sacrificial epitaxial layer 214 includes SiGe, and the Si oxidation rate of the channel epitaxial layer 216 is less than the SiGe oxidation rate of the sacrificial epitaxial layer 214, where the channel epitaxial layer 216 includes Si. It should be noted that three (3) layers are illustrated in FIG. 2A: the sacrificial epitaxial layer 214 and each of the channel epitaxial layer 216, merely for illustrative purposes and not intended to be limiting beyond what is specifically recited in the claims. In various embodiments, any number of epitaxial layers can be formed in the epitaxial stack 212; the number of layers depends on the desired number of channel regions of the device 200. In some embodiments, the number of channel epitaxial layers 216 is between 2 and 10, such as 3, 4, or 5.

[0090] In some embodiments, the sacrificial epitaxial layer 214 has a thickness ranging from about 4 nm to about 12 nm. The sacrificial epitaxial layer 214 can be substantially uniform in thickness. In some embodiments, the channel epitaxial layer 216 has a thickness ranging from about 3 nm to about 6 nm. In some embodiments, the stacked channel epitaxial layers 216 are substantially uniform in thickness.

[0091] As described in more detail below, the channel epitaxial layers 216 can serve as channel regions of a subsequently formed multi-gate device, and their thicknesses are selected based on device performance considerations. The sacrificial epitaxial layer 214 can serve to preserve spacing (or referred to as a gap) between adjacent channel regions of a subsequently formed multi-gate device, and its thickness is selected based on device performance considerations.

[0092] As examples, epitaxial growth of the epitaxial stack 312 can be performed by a molecular beam epitaxy (MBE) process, a metalorganic chemical vapor deposition (MOCVD) process, and / or other suitable epitaxial growth processes. In some embodiments, epitaxially grown layers such as the channel epitaxial layer 316 comprise the same material as the substrate 302, such as silicon (Si). In some embodiments, the epitaxially grown sacrificial epitaxial layer 314 and the channel epitaxial layer 316 comprise different materials than the substrate 302. As described above, in at least some examples, the epitaxially grown sacrificial epitaxial layer 314 comprises a layer of Si 1-x Ge x (e.g., x is about 25% to 55%), while the channel epitaxial layer 316 comprises an epitaxially grown Si layer. Alternatively, in some embodiments, either of the epitaxially grown sacrificial epitaxial layer 314 and the channel epitaxial layer 316 can comprise other materials, such as germanium, compound semiconductors such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide, alloy semiconductors such as SiGe, GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, and / or GaInAsP, or combinations thereof. As discussed, the materials of the epitaxially grown sacrificial epitaxial layer 314 and the channel epitaxial layer 316 can be selected based on providing different oxidation and etch selectivity properties. In various embodiments, the epitaxially grown sacrificial epitaxial layer 314 and the channel epitaxial layer 316 are substantially free of dopants (i.e., have an extrinsic dopant concentration of about 0 cm -3 to about 1 x 1019 17 cm -3 , for example, without intentional doping during the epitaxial growth process.

[0093] In block 206, the example method 200 includes patterning the epitaxial stack to form semiconductor fins, referred to as fins. With reference to the example of FIG. 3C In embodiments of block 206, a plurality of fins 320 extending from the substrate 302 are formed. In various embodiments, each of the fins 320 comprises an upper portion of interleaved sacrificial epitaxial layers 314 and channel epitaxial layers 316 and a bottom portion protruding from the substrate 302.

[0094] The fins 320 can be fabricated using suitable processes, including lithography and etching processes. The lithography process can include forming a photoresist layer over the substrate 302 (e.g., over the epitaxial stack 312), exposing the resist to a pattern, performing a post-exposure bake process, and developing the resist to form masking features including resist. In some embodiments, patterning the resist to form the masking features can be performed using an e-beam lithography process. The masking features can then be used to protect regions of the substrate 302 and the epitaxial stack 312 formed thereon while an etching process forms trenches in unprotected regions via a masking layer such as a hard mask, leaving a plurality of extended fins. The trenches can be etched using dry etching (e.g., reactive ion etching), wet etching, and / or other suitable processes. The trenches can be filled with a dielectric material, forming, for example, a shallow trench isolation feature that plugs the fins.

[0095] At block 208, the example method 200 includes forming isolation features on the substrate. In various embodiments, the isolation features include one or more separation wall layers formed between adjacent fins and / or STI features formed between the fins. Referring to the example of FIG. 2, in embodiments of block 208, a plurality of fins 320 (e.g., fins 320a, 320b, 320c, and 320d) having interleaved sacrificial epitaxial layers 314 and channel epitaxial layers 316 extend from the substrate 302. A plurality of separation wall layers (e.g., including separation walls 321 and one or more liners 323) have been formed between fins 320a and 320b and between fins 320c and 320d. Additionally, an STI feature 322 has been formed between fins 320b and 320c. FIG. 3D

[0096] The STI feature 322 can include one or more dielectric layers. Suitable dielectric materials for the STI feature 322 can include silicon oxide, silicon nitride, silicon carbide, fluorosilicate glass (FSG), low-K dielectric materials, and / or other suitable dielectric materials. The dielectric material can be deposited by any suitable technique including thermal growth, CVD, HDP-CVD, PVD, ALD, and / or spin-on techniques. The deposited dielectric material is subsequently recessed to form the STI feature 322. In the illustrated embodiment, the STI feature 322 is disposed on sidewalls of the overhang of the substrate 302. The top surface of the STI feature 322 can be coplanar with the bottom surface of the epitaxial stack 312, or about 1 nm to about 10 nm lower than the bottom surface of the epitaxial stack 312. Any suitable etching technique can be used to recess the STI feature 322, including dry etching, wet etching, RIE, and / or other etching methods, and in the illustrated embodiment, a non-isotropic dry etching is used to selectively remove the dielectric material of the STI feature 322 without etching the fins 320.

[0097] ​In various embodiments, the isolation wall layer includes isolation walls 321 and one or more liners 323 formed between the isolation walls 321 and the fins 320. The material of the isolation walls 321 can be SiCN, SiOCN, and metal oxides such as Hf02, Zr02, and Al203, or any suitable dielectric material. FIGS. 4A-4F is a cross-sectional side view of an embodiment of the example semiconductor device 300 at various stages of an example fabrication process to form isolation walls and multiple liners according to some embodiments. In the example process to form isolation walls and multiple liners, a hard mask 402 is formed over the fins 320 and patterned, as FIG. 4A is illustrated in the example of FIG. 3B. A liner material 404 for one or more liners is formed over the fins 320, the hard mask 402, and the substrate 403, as FIG. 4B is illustrated in the example of FIG. 3C. The wall material 406 is then formed over the liner material 404, as FIG. 4C is illustrated in the example of FIG. 3D. The wall material 406 is etched, leaving wall material 406 between closely adjacent fins 320a and 320b and between closely adjacent fins 320c and 320d, as FIG. 4D is illustrated in the example of FIG. 3E.

[0098] A dielectric material 408 is formed over the substrate 403 including the liner layer and the wall material and is planarized, e.g., using CMP, as FIG. 4E is illustrated in the example of FIG. 3F. The liner material 404 and the dielectric material 408 are then recessed, and the hard mask 402 is removed to form STI features 322 and one or more liners 323 around the fins 320 and isolation walls 321 and one or more liners 323 between closely adjacent fins, as FIG. 4F is illustrated in the example of FIG. 3G.

[0099] In block 210, the example method 200 includes forming a dummy gate structure over the channel region of the fin. In various embodiments, forming the dummy gate structure includes blanket depositing a sacrificial gate dielectric layer, blanket depositing a sacrificial gate electrode layer on the sacrificial gate dielectric layer, and patterning the sacrificial layer / features to form the dummy gate structure over the channel region of the fin. The sacrificial gate electrode layer can include silicon, such as polysilicon or amorphous silicon. In some embodiments, the thickness of the sacrificial gate dielectric layer can be in a range from about 1 nm to about 5 nm. In some embodiments, the thickness of the sacrificial gate electrode layer can be in a range from about 100 nm to about 200 nm. In some embodiments, the sacrificial gate electrode layer can be subjected to a planarization operation. The sacrificial gate dielectric layer and the sacrificial gate electrode layer can be deposited using CVD (including LPCVD and PECVD), PVD, ALD, or other suitable processes.

[0100] The sacrificial layer / features are patterned to form the dummy gate structure over the channel region of the fin. Referring toFIG. 3E In examples, in embodiments of block 210, a sacrificial gate structure 324 is formed over portions of the fin 320 that will become channel regions. The sacrificial gate structure 324 defines the channel regions of the GAA device. The sacrificial gate structure 324 can include a sacrificial gate dielectric layer and a sacrificial gate electrode layer. The sacrificial gate structure 324 can be formed by forming a mask layer over the sacrificial gate electrode layer. The mask layer can include a liner silicon oxide layer and a silicon nitride mask layer. Subsequently, the mask layer is patterned and the sacrificial gate dielectric layer and electrode layer are patterned into the sacrificial gate structure 324. By patterning the sacrificial gate structure 324, portions of the fin 320 are exposed on opposite sides of the sacrificial gate structure 324, defining source / drain (S / D) regions.

[0101] As discussed with reference to block 224 of the method 200, the sacrificial gate structure 324 is subsequently removed and will be replaced by a final gate stack at a later processing stage of the device 300. In particular, as described below, the sacrificial gate structure 324 is replaced by a high-K dielectric layer (HK) and a metal gate electrode (MG) at a later processing stage.

[0102] In block 212, the example method 200 includes forming gate sidewall spacers on sidewalls of the dummy gate stack. With reference to FIG. 3E In examples, in embodiments of block 212, gate sidewall spacers 332 are formed on sidewalls of the sacrificial gate structure 324. The gate sidewall spacers 332 can include a dielectric material, such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, a SiCN film, silicon oxycarbide, a SiOCN film, and / or combinations thereof. In some embodiments, the gate sidewall spacers 332 include multiple layers, such as a main spacer wall, a liner layer, and the like. As an example, the gate sidewall spacers 332 can be formed by depositing a layer of dielectric material over the sacrificial gate structure 324 using a process, such as a CVD process, a subatmospheric CVD (SACVD) process, a flowable CVD process, an ALD process, a PVD process, or other suitable process. In some embodiments, a back-etch (e.g., anisotropic) process follows the deposition of the layer of dielectric material to expose portions of the fin 320 that are adjacent to and not covered by the sacrificial gate structure 324 (e.g., S / D regions). The layer of dielectric material can remain on the sidewalls of the sacrificial gate structure 324 as the gate sidewall spacers 332. In some embodiments, the back-etch process can include a wet etch process, a dry etch process, a multi-step etch process, and / or combinations thereof. The gate sidewall spacers 332 can have a thickness ranging from about 5 nm to about 20 nm.

[0103] In block 214, the example method includes recessing the sacrificial layer and the trench at the source / drain region. In various embodiments, the recessing is performed by a suitable etching process such as a dry etching process, a wet etching process, or a RIE process. Dry etching can be achieved using an etchant including a bromine-containing gas (e.g., HBr and / or CHBR3), a fluorine-containing gas (e.g., CF4, SF6, CH2F2, CHF3, and / or C2F6), other suitable gases, or combinations thereof.

[0104] In block 216, the example method 200 includes recessing the sacrificial epitaxial layer. FIG. 3F Example embodiments are provided after the cavity 336 is formed by recessing the sacrificial epitaxial layer 314. The sacrificial epitaxial layer 314 can be selectively etched by using a wet etchant such as, but not limited to, ammonium hydroxide (NH4OH), tetramethylammonium hydroxide (TMAH), ethylenediamine pyrocatechol (EDP), or potassium hydroxide (KOH) solution.

[0105] FIGS. 5A-5D are cross-sectional illustrations illustrating different stages of a fabrication process of recessing a sacrificial epitaxial layer and liner layers to achieve leak prevention. FIG. 5A Depicted in is a sacrificial epitaxial layer 502, a first liner 504, a second liner 506, and a separation wall 508. In other examples, additional liners can be included. In a first step, the sacrificial epitaxial layer 502 can be exposed so that the sacrificial epitaxial layer 502 can be recessed. FIG. 5B Depicted in is the sacrificial epitaxial layer 502 after the cavity 510 is recessed. In a second step, the first liner 504 is recessed. As FIG. 5C In an embodiment of the second step, the first liner 504 is recessed, which extends the cavity 510, as depicted in FIG. 5D In an embodiment of the third step, the second liner 506 is recessed, which extends the cavity 510, as depicted in

[0106] In block 218, the example method 200 includes forming an internal spacer. Forming the internal spacer includes depositing an internal spacer material and etching back the internal spacer material. FIG. 3GExample embodiments are provided after deposition and etch back of an inner spacer material layer 338. The inner spacer material layer 338 is formed on the lateral ends of the sacrificial epitaxial layer 314 in the cavities 336 and on the channel epitaxial layer 316 in the recesses 334. The inner spacer material layer 338 can include silicon oxide, silicon nitride, silicon carbide, silicon carbon nitride, silicon carbon oxide, silicon carbon nitrogen oxide, and / or other suitable dielectric materials. In some embodiments, the inner spacer material layer 338 is deposited as a conformal layer. The inner spacer material layer 338 can be formed by ALD or any other suitable method. By forming the inner spacer material layer 338 conformally, the size of the cavities 336 is reduced or completely filled. After forming the inner spacer material layer 338, an etch operation is performed to partially remove the inner spacer material layer 338. By this etch, the inner spacer material layer 338 is substantially retained within the cavities 336.

[0107] In block 220, the example method 200 includes forming source / drain (S / D) features. Referring to the example of FIG. 3, in embodiments of block 220, epitaxial S / D features 340 are formed in the recesses 334. In some embodiments, the epitaxial S / D features 340 include silicon for NFETs and SiGe for PFETs. In some embodiments, the epitaxial S / D features 340 are formed by an epitaxial growth method using CVD, ALD, or molecular beam epitaxy (MBE). The epitaxial S / D features 340 are formed in contact with the channel epitaxial layer 316 and separated from the sacrificial epitaxial layer 314 by the inner spacer material layer 338. FIG. 3H

[0108] In block 222, the example method 200 includes forming a CESL and ILD layers. Referring to the example of FIG. 3, in embodiments of block 222, a CESL 342 and an ILD layer 344 are formed. The CESL 342 is formed on the epitaxial S / D features 340 and the ILD layer 344 is formed on the CESL 342. In some embodiments, the CESL 342 and the ILD layer 344 are formed by CVD, ALD, or any other suitable deposition method. In some embodiments, the CESL 342 and the ILD layer 344 are formed by a conformal deposition method. In some embodiments, the CESL 342 and the ILD layer 344 are formed by a non-conformal deposition method. In some embodiments, the CESL 342 and the ILD layer 344 are formed by a combination of conformal and non-conformal deposition methods. FIG. 3I ​In an embodiment of block 222, a contact etch stop layer (CESL) 342 is formed over the epitaxial S / D features 340, and an interlayer dielectric (ILD) layer 344 is formed over the CESL layer 342. The CESL layer 342 may include silicon nitride, silicon oxynitride, silicon nitride with oxygen (O) or carbon (C), and / or other materials and may be formed by CVD, physical vapor deposition (PVD), ALD, or other suitable methods. The ILD layer 344 may include tetraethylorthosilicate (TEOS) oxide, undoped silicate glass, or doped silicon oxide, such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), borondoped silicon glass (BSG), and / or other suitable dielectric materials. The ILD layer 344 may be formed by PECVD, flowable CVD (FCVD), or other suitable methods. In some embodiments, forming the ILD layer 344 further includes performing a CMP process to planarize the top surface of the device 300 such that the top surface of the sacrificial gate structure 324 is exposed.

[0109] At block 224, the example method 200 includes removing the dummy gate stack to form a gate trench. FIG. 3J In the embodiment of block 224, the sacrificial gate structure 324 is removed to form a gate trench 354. The gate trench 354 exposes the fin 320 in the channel region. The ILD layer 344 and the CESL layer 342 protect the epitaxial S / D features 340 during the removal of the sacrificial gate structure 324. The sacrificial gate structure 324 can be removed using a plasma dry etch and / or wet etch. When the sacrificial gate electrode layer is polysilicon and the ILD layer 344 is an oxide, a wet etchant such as a TMAH solution can be used to selectively remove the sacrificial gate electrode layer. Thereafter, the sacrificial gate dielectric layer is removed using a plasma dry etch and / or wet etch.

[0110] At block 226, the example method 200 includes removing the sacrificial epitaxial layer to form the nanosheets. FIG. 3KIn the embodiment of block 226, the sacrificial epitaxial layers have been removed, releasing the channel members from the channel regions of the GAA device. In the illustrated embodiment, the channel members are channel epitaxial layers 316 in the form of nanosheets. In various embodiments, the channel epitaxial layers 316 comprise silicon, while the sacrificial epitaxial layers 314 comprise silicon germanium. In various embodiments, the plurality of sacrificial epitaxial layers 314 are selectively removed via a selective removal process, including using a suitable oxidizing agent, such as ozone, to oxidize the plurality of sacrificial epitaxial layers 314. Thereafter, the oxidized sacrificial epitaxial layers 314 are selectively removed via a dry etching process, for example by applying HC1 gas or a gas mixture of CF4, SF6, and CHF3 at a temperature of about 500 degrees Celsius to about 700 degrees Celsius.

[0111] In block 228, the example method 200 includes forming a high-K metal gate structure. Referring to FIG. 2, in the illustrated embodiment, the high-K metal gate structure is formed by depositing a high-K dielectric layer 318 over the channel members 316. In various embodiments, the high-K dielectric layer 318 comprises hafnium oxide. In various embodiments, the high-K dielectric layer 318 is deposited via atomic layer deposition (ALD) or chemical vapor deposition (CVD). In various embodiments, the high-K dielectric layer 318 is deposited at a temperature of about 300 degrees Celsius to about 500 degrees Celsius. In various embodiments, the high-K dielectric layer 318 is deposited at a pressure of about 10"6torr to about 10"8torr. In various embodiments, the high-K dielectric layer 318 is deposited at a thickness of about 1 nm to about 5 nm. FIG. 3LIn the example of FIG. 2, a gate structure 360 is formed in the embodiment of block 228. In various embodiments, the gate structure is a gate of a multi-gate transistor. In various embodiments, the gate structure is a high-K metal gate stack, however, other compositions are possible. In various embodiments, the high-K metal gate stack includes a gate dielectric layer that includes an interface layer 362 and a high-k dielectric layer 364. The high-k dielectric layer 364 surrounds each of the nanosheets 316, and the interface layer 362 is interposed between the high-k dielectric layer and the nanosheets 316. The interface layer 362 can include a dielectric material such as silicon oxide (SiO2) or silicon oxynitride (SiON), and can be formed by chemical oxidation, thermal oxidation, atomic layer deposition (ALD), CVD, and / or other suitable methods. The high-k dielectric layer can include hafnium oxide (HfO2), hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium tantalum oxide (HMO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), other suitable high-k dielectric materials, and / or combinations thereof. The high-k material can be further selected from metal oxides, metal nitrides, metal silicates, transition metal oxides, transition metal nitrides, transition metal silicates, metal oxynitrides, metal aluminates, zirconium silicates, zirconium aluminates, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, titanium oxide, aluminum oxide, hafnium oxide-aluminum oxide (HfO2— Al2O3) alloys, other suitable materials, and / or combinations thereof. The high-k dielectric layer can be formed by any suitable process such as atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), remote plasma CVD (RPCVD), plasma enhanced CVD (PECVD), metal organic CVD (MOCVD), sputtering, plating, other suitable processes, and / or combinations thereof. In one embodiment, a highly conformal deposition process such as ALD is used to form the gate dielectric layer to ensure that a gate dielectric layer of uniform thickness is formed around each channel layer. The high-K metal gate structure can include additional material layers.

[0112] At block 230, example method 200 includes performing further fabrication. The semiconductor device may undergo further processing to form various features and regions known in the art. For example, subsequent processing may form contact openings, contact metal, and various contacts / vias / lines and multilayer interconnect features (e.g., metal layers and interlayer dielectrics) on the substrate, which are used to connect the various features to form functional circuits that may include one or more multi-gate devices. To facilitate the example, the multilayer interconnects may include vertical interconnects such as vias or contacts and horizontal interconnects such as metal lines. The various interconnect features may utilize various conductive materials including copper, tungsten, and / or silicide. In one example, a copper-related multilayer interconnect structure is formed using damascene and / or dual damascene processes. Furthermore, additional process steps may be implemented before, during, and after method 200, and some of the process steps described above may be replaced or eliminated according to various embodiments of method 200.

[0113] FIGS. 6A-6C After the metal gate is formed FIG. 1B A schematic cross-sectional view corresponding to line X2-X2' in FIG. illustrates the various shapes of material layers surrounding the metal gate layer, which can be used to prevent leakage due to the recessed liner (including the first and second liners). A high-K metal gate (HKMG) layer 602, an internal spacer layer 604, a first liner 606, a second liner 608, and a separating wall 610 are depicted. In other examples, additional liners may be included. The HKMG layer 602 is bounded by a first end 613 adjacent to the first liner 606 and a second end 611 on the opposite side of the HKMG layer 602 from the first end 613. In these examples, the HKMG layer 602 has a first critical dimension (CD) in the y-direction measured between the inner spacer layers 604, the first liner 606 has a second CD in the y-direction measured between the inner spacer layers 604, the second liner 608 has a third CD in the y-direction measured between the inner spacer layers 604, and the HKMG layer 602 has a width (W) measured from a first end 613 adjacent to the first liner 606 to a second end 611. HKMG )612.

[0114] exist FIG. 6A In the example of , the first CD of the HKMG layer 602, the second CD of the first liner 606, and the third CD of the second liner 608 are approximately equal. FIG. 6B In the example of , the first CD of the HKMG layer 602 and the second CD of the first liner 606 are approximately equal, but the third CD of the second liner 608 is smaller than the first and second CDs. FIG. 6CIn the example of FIG. 5 , the first CD of the HKMG layer 602 and the second CD of the first liner 606 are approximately equal, but the third CD of the second liner 608 is greater than the first and second CDs.

[0115] exist FIG. 6A and FIG. 6B In the example of , a single internal spacer width (W IS1 ) 614, which is defined as the width of the HKMG layer 602 plus the width of the liner closest to the HKMG layer 602, whose CD is substantially greater than the CD of the HKMG layer 602. Because the CD of the first liner 606 and the second liner 608 is less than or equal to the CD of the HKMG layer 602, the inner spacer width (W IS1 )614 extends to the separation wall 610.

[0116] exist FIG. 6C In the example of the first inner spacer width (W IS1 ) 614, which is defined as the width of the HKMG layer 602 plus the width of the liner closest to the HKMG layer 602, the CD of which liner is substantially larger than the CD of the HKMG layer 602, and defines the second inner spacer width (W IS2 ) 616, which is defined as the width of the HKMG layer 602 plus the width of the second liner closest to the HKMG layer 602, the CD of which is substantially larger than the CD of the HKMG layer 602. Because the CD of the first liner 606 is less than or equal to the CD of the HKMG layer 602, and the CD of the second liner 608 is larger than the CD of the HKMG layer 602, the inner spacer width (W IS1 ) 614 extends to the second liner 608. The second inner spacer width (W IS2 ) 616 extends to the separation wall 610 because there is no other internal spacer with a CD greater than the CD of the HKMG layer 602. If there is an additional internal spacer, there may be an additional internal spacer width (e.g., W IS1 、W IS2 、……、W ISn , n≤10).

[0117] exist FIGS. 6A-6C In each of the scenarios depicted in FIG, when the inner spacer layer 604 has a width (W ) greater than that of the HKMG layer 602, HKMG )612 The first inner spacer width (W IS1 )614, leakage prevention is achieved. In other words, when W IS1 -W HKMG When the width of the first inner spacer is greater than 3A, leakage prevention is achieved. IS1)614 structures that are measured to have a CD substantially greater than the CD of the HKMG layer 602 (e.g., 3 Angstroms greater than the CD of the HKMG layer 602).

[0118] FIGS. 7A-7C after metal gate formation and before FIG. 1B corresponding to line X2-X2' of FIG. 6B, illustrating different shaped material layers around the metal gate layer that can achieve leak prevention due to liner (including first liner and second liner) recessing. The HKMG layer 702, inner spacer layer 704, first liner 706, second liner 708, and separation wall 710 are depicted. In other examples, additional liners can be included. In these examples, the HKMG layer 702 has a first critical dimension (CD) 712 measured between the inner spacer layers 704 at an end closest to the first liner 706, the first liner 706 has a second CD 714 measured between the inner spacer layers 704, and the second liner 708 has a third CD 716 measured between the inner spacer layers 704. Due to different etch behavior in different layout designs, there can be different shapes as shown in FIG. 6B. FIGS. 7A-7C

[0119] In examples of FIG. 6B, the first CD 712, the second CD 714, and the third CD 716 are substantially equal. In examples of FIG. 6B, the first CD 712 and the second CD 714 are substantially equal, but the third CD 716 is less than the first CD 712 and the second CD 714. In examples of FIG. 6B, the first CD 712 and the second CD 714 are substantially equal, but the third CD 716 is greater than the first CD 712 and the second CD 714. In these examples, leak prevention can be achieved when the absolute value of the difference between the first CD 712 and the second CD 714 is less than or equal to 5 Angstroms (5A > |first CD 712 - second CD 714|). Leak prevention can also be achieved when the first CD 712 minus the second CD 714 is greater than 3 Angstroms (first CD 712 - second CD 714 > 3A). Further, leak prevention can be achieved when the first CD 712 > the second CD 714. FIG. 7A FIG. 7B FIG. 7C

[0120] In examples of FIG. 6B, the first CD 712, the second CD 714, and the third CD 716 are substantially equal. In examples of FIG. 6B, the first CD 712 and the second CD 714 are substantially equal, but the third CD 716 is less than the first CD 712 and the second CD 714. In examples of FIG. 6B, the first CD 712 and the second CD 714 are substantially equal, but the third CD 716 is greater than the first CD 712 and the second CD 714. In these examples, leak prevention can be achieved when the absolute value of the difference between the first CD 712 and the second CD 714 is less than or equal to 5 Angstroms (5A > |first CD 712 - second CD 714|). Leak prevention can also be achieved when the first CD 712 minus the second CD 714 is greater than 3 Angstroms (first CD 712 - second CD 714 > 3A). Further, leak prevention can be achieved when the first CD 712 > the second CD 714. FIG. 7A ​​​​In the example of FIG, leakage prevention can be achieved when the difference between the first CD 712 and the second CD 714 is less than or equal to 5 angstroms (5A ≥ |first CD 712 - second CD 714|) and when the difference between the second CD 714 and the third CD 716 is less than or equal to 5 angstroms (5A ≥ |second CD 714 - third CD 716|). Furthermore, leakage prevention can be achieved when the difference between the first CD 712 and the third CD 716 is less than or equal to 5 angstroms (5A ≥ |first CD 712 - third CD 716|).

[0121] exist FIG. 7B In the example, when the difference between the first CD 712 and the second CD 714 is less than or equal to 5 angstroms (5 Å ≥ |first CD 712 - second CD 714|) and when the second CD 714 minus the third CD 716 is greater than or equal to 3 angstroms (second CD 714 - third CD 716 ≥ 3 Å), leakage prevention can be achieved. In addition, when the first CD 712 minus the third CD 716 is greater than or equal to 3 angstroms (first CD 712 - third CD 716 ≥ 3 Å), leakage prevention can be achieved.

[0122] exist FIG. 7C In the example, when the difference between the first CD 712 and the second CD 714 is less than or equal to 5 angstroms (5 Å ≥ |first CD 712 - second CD 714|) and when the third CD 716 minus the second CD 714 is greater than or equal to 3 angstroms (third CD 716 - second CD 714 ≥ 3 Å), leakage prevention can be achieved. In addition, when the third CD 716 minus the first CD 712 is greater than or equal to 3 angstroms (third CD 716 - first CD 712 ≥ 3 Å), leakage prevention can be achieved.

[0123] FIGS. 8A-8B After the metal gate is formed FIG. 1Bcorresponding cross-sectional view of the line X2-X2' illustrating different shaped material layers around the metal gate layer that can achieve leak prevention due to liner (including first liner and second liner) recessing. The HKMG layer 802, inner spacer layer 804, first liner 806, second liner 808, and separation wall 810 are depicted. In other examples, additional liners can be included. In these examples, the HKMG layer 802 has a first critical dimension (CD) 812 measured between the inner spacer layer 804 at an end closest to the first liner 806, the first liner 806 has a second CD 814 measured between the inner spacer layer 804, and the second liner 808 has a third CD 816 and a fourth CD 818. The third CD 816 is at an end of the second liner 808 closest to the first liner 806, and the fourth CD 818 is at an end of the second liner 808 closest to the separation wall 810. Due to different etch behavior in different layout designs, there can be FIGS. 8A-8B an asymmetric shape of the second liner 808 as shown in FIG. 8B. The asymmetric shape in the second liner 808 can be caused by a lower etch rate due to a smaller reactive area for the etch process.

[0124] In examples of FIG. 8A, FIG. 8A the first CD 812, the second CD 814, and the third CD 816 are substantially equal, but the fourth CD 818 is larger. In examples of FIG. 8B, FIG. 8B the first CD 812 and the second CD 814 are substantially equal, but the third CD 816 and the fourth CD 818 are larger than the first CD 812 and the second CD 814. In these examples, the third CD 816 is larger than the fourth CD 818. In various embodiments, the third CD 816 is more than 3 Angstroms larger than the fourth CD 818.

[0125] In examples of FIG. 8A, FIG. 8A leak prevention can be achieved when the difference between the first CD 812 and the third CD 816 is less than or equal to 5 Angstroms (5A > |first CD 812 - third CD 816|) and when the fourth CD 818 minus the first CD 812 is greater than or equal to 3 Angstroms (fourth CD 818 - first CD 812 > 3A).

[0126] In examples of FIG. 8B, FIG. 8B leak prevention can be achieved when the third CD 816 minus the first CD 812 is greater than or equal to 3 Angstroms (third CD 816 - first CD 812 > 3A) and when the fourth CD 818 minus the first CD 812 is greater than or equal to 3 Angstroms (fourth CD 818 - first CD 812 > 3A).

[0127] Improved systems, manufacturing methods, manufacturing techniques, and articles of manufacture have been described. The described systems, methods, techniques, and articles of manufacture can be used with various semiconductor devices including gate-all-around FETs (GAAFETs / NSFETs). The described systems, methods, techniques, and articles of manufacture can be used to manufacture semiconductor devices, including semiconductor devices having nanosheet structures. The described systems, methods, techniques, and articles of manufacture can be used to prevent current leakage from a metal gate to a source / drain region via a liner.

[0128] In some aspects, the techniques described herein are directed to a method of manufacturing, comprising: providing a separation wall and a plurality of liners, the plurality of liners including a first liner between a first fin and a second fin, the second fin having an epitaxial stack and a sacrificial gate stack over a channel region of the second fin, wherein the first liner is closer to the epitaxial stack and the second liner is closer to the separation wall; recessing a sacrificial epitaxial layer of the epitaxial stack to form a cavity; recessing the first liner after recessing the sacrificial epitaxial layer, thereby expanding the cavity; recessing the second liner after recessing the first liner, thereby expanding the cavity; forming an inner spacer material in the cavity; forming a source / drain feature; and replacing the sacrificial epitaxial layer and the sacrificial gate stack with a metal gate layer; wherein the metal gate layer has a first critical dimension (CD) measured between the inner spacer material, and wherein the first liner after recessing has a second CD measured between the inner spacer material.

[0129] In some aspects, the techniques described herein are directed to a method, wherein an absolute value of a difference between the first CD and the second CD is less than 5 Angstroms (5A).

[0130] In some aspects, the techniques described herein are directed to a method, wherein: the metal gate layer has a first width measured from a first end adjacent to the first liner to a second end on an opposite side of the metal gate layer from the first end; and the inner spacer material has a second width measured from a line extending along the second end to a structure, the second width being greater than the first width by 3 Angstroms (3A), wherein the structure has a CD greater than or equal to the first CD plus 3A.

[0131] In some aspects, the techniques described herein are directed to a method, wherein the structure is the second liner.

[0132] In some aspects, the techniques described herein are directed to a method, wherein the structure is the separation wall.

[0133] In some aspects, the techniques described herein are with respect to a method, wherein the second liner after recessing has a third CD measured between the inner spacer material, and an absolute value of a difference between the second CD and the third CD is less than or equal to 5 Angstroms (5A).

[0134] In some aspects, the techniques described herein are with respect to a method, wherein the second liner after recessing has a third CD measured between the inner spacer material, and the third CD minus the second CD is greater than or equal to 3 Angstroms (3A).

[0135] In some aspects, the techniques described herein are with respect to a method, wherein the second liner after recessing has a third CD measured between the inner spacer material, and the second CD minus the third CD is greater than or equal to three Angstroms (A).

[0136] In some aspects, the techniques described herein are with respect to a method, wherein: the second liner has an asymmetric liner shape; the second liner has a third CD measured between the inner spacer material, the third CD is measured at an end closest to the first liner; the second liner has a fourth CD measured at an end closest to the separation wall; an absolute value of a difference between the first CD and the third CD is less than or equal to 5A; and the fourth CD minus the first CD is greater than or equal to 3A.

[0137] In some aspects, the techniques described herein are with respect to a method, wherein: the second liner has an asymmetric liner shape; the second liner has a third CD measured between the inner spacer material, the third CD is measured at an end closest to the first liner; the second liner has a fourth CD measured at an end closest to the separation wall; the third CD minus the first CD is greater than or equal to 3A; and the fourth CD minus the first CD is greater than or equal to 3A.

[0138] In some aspects, the techniques described herein are with respect to a semiconductor device, comprising: a first fin and a second fin, the first fin having a channel region comprising a plurality of channel slices and a plurality of metal gate layers; a separation wall and a plurality of liners, the plurality of liners comprising a first liner and a second liner formed between the first fin and the second fin, wherein the first liner is closer to at least one of the plurality of metal gate layers and the second liner is closer to the separation wall; and an inner spacer material formed around the at least one of the plurality of metal gate layers, the first liner, and the second liner; wherein the at least one of the plurality of metal gate layers has a first critical dimension (CD) measured between the inner spacer material at an end closest to the first liner, and the first liner has a second CD measured between the inner spacer material, the second CD is approximately equal to the first CD.

[0139] In some aspects, a semiconductor device includes: a first fin and a second fin, the first fin having a channel region including a plurality of channel tiers and a plurality of metal gate layers; a spacer wall and a plurality of liners, the plurality of liners including a first liner and a second liner between the first fin and the second fin, wherein the first liner is closer to at least one of the plurality of metal gate layers and the second liner is closer to the spacer wall; and inner spacer layers around the at least one metal gate layer, the first liner, and the second liner; wherein the at least one metal gate layer has a first critical dimension measured between the inner spacer layers at an end closest to a first liner and the first liner has a second critical dimension measured between the inner spacer layers, an absolute value of a difference between the second critical dimension and the first critical dimension is less than or equal to 5 Angstroms.

[0140] In some aspects, a semiconductor device includes: a first fin and a second fin, the first fin having a channel region including a plurality of channel tiers and a plurality of metal gate layers; a spacer wall and a plurality of liners, the plurality of liners including a first liner and a second liner between the first fin and the second fin, wherein the first liner is closer to at least one of the plurality of metal gate layers and the second liner is closer to the spacer wall; and inner spacer layers around the at least one metal gate layer, the first liner, and the second liner; wherein the at least one metal gate layer has a first critical dimension measured between the inner spacer layers at an end closest to a first liner and the first liner has a second critical dimension measured between the inner spacer layers, the second critical dimension is equal to the first critical dimension; wherein the second liner has different critical dimensions at an end closest to the first liner and at an end closest to the spacer wall, respectively.

[0141] In some aspects, the techniques described herein are with respect to a semiconductor device, wherein an absolute value of a difference between a first CD and a second CD is less than 5 Angstroms (5A).

[0142] In some aspects, the techniques described herein are with respect to a semiconductor device, wherein: at least one metal gate layer has a first width measured from a first end adjacent to a first liner to a second end; and an inner spacer material has a second width measured from the first end to a structure, the structure having a CD greater than or equal to the first CD plus 3A, the CD being 3A greater than the first width.

[0143] In some aspects, the techniques described herein are with respect to a semiconductor device, wherein the structure is a second liner.

[0144] In some aspects, the techniques described herein are with respect to a semiconductor device, wherein the structure is a spacer.

[0145] In some aspects, the techniques described herein are with respect to a semiconductor device, wherein the second liner has a third CD measured between the inner spacer material, and an absolute value of a difference between the second CD and the third CD is less than or equal to five Angstroms (A).

[0146] In some aspects, the techniques described herein are with respect to a semiconductor device, wherein the second liner has a third CD measured between the inner spacer material, and the third CD minus the second CD is greater than or equal to three Angstroms (A).

[0147] In some aspects, the techniques described herein are with respect to a semiconductor device, wherein the second liner has a third CD measured between the inner spacer material, and the second CD minus the third CD is greater than or equal to three Angstroms (A).

[0148] In some aspects, the techniques described herein are with respect to a semiconductor device, wherein: the second liner has an asymmetric liner shape; the second liner has a third CD measured between the inner spacer material, the third CD being measured at an end closest to the first liner; the second liner has a fourth CD measured at an end closest to the spacer; an absolute value of a difference between the first CD and the third CD is less than or equal to 5 A; and the fourth CD minus the first CD is greater than or equal to 3 A.

[0149] In some aspects, the techniques described herein are with respect to a semiconductor device, wherein: the second liner has an asymmetric liner shape; the second liner has a third CD measured between the inner spacer material, the third CD being measured at an end closest to the first liner; the second liner has a fourth CD measured at an end closest to the spacer; the third CD minus the first CD is greater than or equal to 3 A; and the fourth CD minus the first CD is greater than or equal to 3 A.

[0150] In some aspects, the techniques described herein are directed to a method of manufacturing, comprising: forming a first fin and a second fin, the first fin having an epitaxial stack comprising at least one sacrificial epitaxial layer and at least one channel epitaxial layer; forming a separation wall and a plurality of liners, the plurality of liners comprising a first liner and a second liner located between the first fin and the second fin, wherein the first liner is closer to the at least one sacrificial epitaxial layer of the first fin and the second liner is closer to the separation wall; forming a sacrificial gate stack over a channel region of the first fin; recessing the at least one sacrificial epitaxial layer to form a cavity; recessing the first liner after recessing the at least one sacrificial epitaxial layer, thereby expanding the cavity; recessing the second liner after recessing the first liner, thereby expanding the cavity; forming an inner spacer material in the cavity; forming a source / drain feature; and replacing the sacrificial gate stack and the at least one sacrificial epitaxial layer with a metal gate; wherein the metal gate has a first critical dimension (CD) measured between the inner spacer material, the first liner has a second CD measured between the inner spacer material, and the second liner has a third CD measured between the inner spacer material.

[0151] In some aspects, the techniques described herein are directed to a method, wherein an absolute value of a difference between the first CD and the second CD is less than 5 Angstroms (5A).

[0152] In some aspects, the techniques described herein are directed to a method, wherein: the metal gate has a first width measured from a first end adjacent to the first liner to a second end; and the inner spacer material has a second width measured from the first end to a structure, the structure having a CD greater than or equal to the first CD plus 3 Angstroms (3A), the CD being greater than the first width by 3A.

[0153] In some aspects, the techniques described herein are directed to a method, wherein the structure is the second liner.

[0154] In some aspects, the techniques described herein are directed to a method, wherein the structure is the separation wall.

[0155] In some aspects, the techniques described herein are directed to a method, wherein the second liner after recessing has a third CD measured between the inner spacer material, and an absolute value of a difference between the second CD and the third CD is less than or equal to 5 Angstroms (5A).

[0156] In some aspects, the techniques described herein are with respect to a method in which the second liner after recessing has a third CD measured between the inner spacer material, and the third CD minus the second CD is greater than or equal to 3 Angstroms (3 A).

[0157] In some aspects, the techniques described herein are with respect to a method in which the second liner after recessing has a third CD measured between the inner spacer material, and the second CD minus the third CD is greater than or equal to three Angstroms (A).

[0158] In some aspects, the techniques described herein are with respect to a method in which: the second liner has an asymmetric liner shape; the second liner has a third CD measured between the inner spacer material, the third CD being measured at an end closest to the first liner; the second liner has a fourth CD measured at an end closest to the separation wall; an absolute value of a difference between the first CD and the third CD is less than or equal to 5 A; and the fourth CD minus the first CD is greater than or equal to 3 A.

[0159] In some aspects, the techniques described herein are with respect to a method in which: the second liner has an asymmetric liner shape; the second liner has a third CD measured between the inner spacer material, the third CD being measured at an end closest to the first liner; the second liner has a fourth CD measured at an end closest to the separation wall; the third CD minus the first CD is greater than or equal to 3 A; and the fourth CD minus the first CD is greater than or equal to 3 A.

[0160] In some aspects, the technology described herein relates to a manufacturing method comprising: forming a first fin and a second fin, the first fin having an epitaxial stack comprising at least one sacrificial epitaxial layer and at least one channel epitaxial layer; forming a separation wall and a plurality of liners, the plurality of liners comprising a first liner and a second liner located between the first fin and the second fin, wherein the first liner is closer to the at least one sacrificial epitaxial layer of the first fin and the second liner is closer to the separation wall; forming a first sacrificial gate stack above a channel region of the first fin; recessing the at least one sacrificial epitaxial layer to form a first cavity and a second cavity, wherein the at least one sacrificial layer after the recessing has a first critical dimension (CD) measured between the first cavity and the second cavity at an end closest to the first liner. The invention relates to a method for forming a fin structure comprising: recessing a first liner to enlarge the first cavity and the second cavity, the first liner after the recessing having a second CD measured between the first cavity and the second cavity, wherein an absolute value of a difference between the first CD and the second CD is less than five angstroms (A); recessing the second liner after the recessing of the first liner to enlarge the first cavity and the second cavity, the second liner after the recessing having a third CD measured between the first cavity and the second cavity; forming an inner spacer material in the first cavity and the second cavity; forming source / drain features; removing a sacrificial gate stack and at least one sacrificial epitaxial layer in the fin; and forming a metal gate to replace the sacrificial gate stack and the at least one sacrificial epitaxial layer.

[0161] While at least one exemplary embodiment has been presented in the foregoing detailed description of the present disclosure, it should be understood that a vast number of variations exist. It should also be understood that the one or more exemplary embodiments are merely examples and are not intended to limit the scope, applicability, or configuration of the present disclosure in any way. Rather, the foregoing detailed description will provide those skilled in the art with a convenient roadmap for implementing the exemplary embodiments of the present disclosure. It should be understood that various changes may be made in the functionality and configuration of the components described in the exemplary embodiments without departing from the scope of the present disclosure as set forth in the appended claims.

Claims

1. A semiconductor device, characterized by comprising: including: a first fin and a second fin, the first fin having a channel region including a plurality of channel fin layers and a plurality of metal gate layers; a separation wall and a plurality of liners, the plurality of liners including a first liner and a second liner located between the first fin and the second fin, wherein the first liner is closer to at least one of the plurality of metal gate layers and the second liner is closer to the separation wall; and inner spacer layers located around the at least one metal gate layer, the first liner, and the second liner; wherein the at least one metal gate layer has a first critical dimension measured between the inner spacer layers at an end closest to a first liner, and the first liner has a second critical dimension measured between the inner spacer layers, the second critical dimension being equal to the first critical dimension.

2. The semiconductor device according to claim 1, wherein The second liner has a third critical dimension measured between the inner spacer layers, and an absolute value of a difference between the second critical dimension and the third critical dimension is less than or equal to 5 angstroms.

3. The semiconductor device according to claim 1, wherein The second liner has a third critical dimension measured between the inner spacer layers, and a difference between the second critical dimension and the third critical dimension is greater than or equal to 3 angstroms.

4. The semiconductor device according to claim 1, wherein The second liner has a third critical dimension measured between the inner spacer layers, and a difference between the second critical dimension and the third critical dimension is greater than or equal to 3 angstroms.

5. The semiconductor device of claim 1, wherein: the second liner has an asymmetric liner shape; the second liner has a third critical dimension measured between the inner spacer layers, the third critical dimension being measured at an end closest to the first liner; the second liner has a fourth critical dimension measured at an end closest to the separation wall; an absolute value of a difference between the first critical dimension and the third critical dimension is less than or equal to 5 angstroms; and the fourth critical dimension minus the first critical dimension is greater than or equal to 3 angstroms.

6. The semiconductor device of claim 1, wherein: the second liner has an asymmetric liner shape; the second liner has a third critical dimension measured between the inner spacer layers, the third critical dimension being measured at an end closest to the first liner; the second liner has a fourth critical dimension measured at an end closest to the separation wall; the third critical dimension minus the first critical dimension is greater than or equal to 3 angstroms; and the fourth critical dimension minus the first critical dimension is greater than or equal to 3 angstroms.

7. A semiconductor device, characterized by comprising: including: a first fin and a second fin, the first fin having a channel region including a plurality of channel fin layers and a plurality of metal gate layers; a separation wall and a plurality of liners, the plurality of liners including a first liner and a second liner located between the first fin and the second fin, wherein the first liner is closer to at least one of the plurality of metal gate layers and the second liner is closer to the separation wall; and inner spacer layers located around the at least one metal gate layer, the first liner, and the second liner; wherein the at least one metal gate layer has a first critical dimension measured between the inner spacer layers at an end closest to a first liner, and the first liner has a second critical dimension measured between the inner spacer layers, an absolute value of a difference between the second critical dimension and the first critical dimension is less than or equal to 5 angstroms.

8. The semiconductor device according to claim 7, wherein The second liner has a third critical dimension measured between the inner spacer layers, and a difference between the second critical dimension and the third critical dimension is greater than or equal to 3 angstroms.

9. The semiconductor device according to claim 7, wherein The second liner has a third critical dimension measured between the inner spacer layers, and a difference between the second critical dimension and the third critical dimension is greater than or equal to 3 angstroms.

10. A semiconductor device, characterized by comprising: Comprising: a first fin and a second fin, the first fin having a channel region comprising a plurality of channel sheet layers and a plurality of metal gate layers; a separation wall and a plurality of liners, the plurality of liners including a first liner and a second liner between the first fin and the second fin, wherein the first liner is closer to at least one of the plurality of metal gate layers, and the second liner is closer to the separation wall; and inner spacer layers surrounding the at least one metal gate layer, the first liner, and the second liner; wherein the at least one metal gate layer has a first critical dimension measured between the inner spacer layers at an end closest to a first liner, and the first liner has a second critical dimension measured between the inner spacer layers, the second critical dimension is equal to the first critical dimension; wherein the second liner has different critical dimensions at an end closest to the first liner and at an end closest to the separation wall, respectively.

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