Semiconductor device

Abstract

The embodiment of the utility model provides a semiconductor device comprising a diode. The diode comprises a P-type region, an N-type region and an undoped intrinsic region. Each of a first conductive contact and a second conductive contact is disposed over a first side of the diode. The first conductive contact is electrically coupled from the first side to the P-type region. The second conductive contact is electrically coupled from the first side to the N-type region. Each of a first via and a second via is disposed over a second side of the diode. The second side is different from the first side. A first via is electrically coupled from the second side to the P-type region. A second via is electrically coupled from the second side to the N-type region. The first conductive contact is electrically coupled to the first via. The second conductive contact is electrically coupled to the second via.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to a semiconductor device. BACKGROUND

[0002] The semiconductor integrated circuit (IC) industry has experienced rapid growth. As a result of this growth, the feature sizes of ICs have decreased, and the densities of various components (e.g., transistors, diodes, resistors, capacitors, etc.) have increased. In the effort to keep up with this growth, the industry has placed increasingly greater demands on the photolithography and etching processes used to create the various components in ICs.

[0003] However, as the shrinking process continues, it presents certain manufacturing challenges. For example, the fabrication of a diode structure can result in the presence of positively charged particles within the dielectric structure. The presence of positively charged particles can attract electrons in the vicinity of the dielectric structure, which can result in poorer device performance and is therefore undesirable.

[0004] Therefore, while certain diode fabrication processes are generally sufficient for their intended purpose, they have not been entirely satisfactory in every respect. SUMMARY

[0005] One aspect of the present application relates to a semiconductor device. The semiconductor device includes a diode including a P-type region, an N-type region, and an undoped intrinsic region. A first conductive contact and a second conductive contact are disposed over a first side of the diode. The first conductive contact is electrically coupled from the first side to the P-type region. The second conductive contact is electrically coupled from the first side to the N-type region. A first conductive via and a second conductive via are disposed over a second side of the diode. The second side is different from the first side. The first conductive via is electrically coupled from the second side to the P-type region. The second conductive via is electrically coupled from the second side to the N-type region. The first conductive contact is electrically coupled to the first conductive via. The second conductive contact is electrically coupled to the second conductive via.

[0006] Another aspect of the utility model relates to a semiconductor device. The semiconductor device includes an active region, which includes a plurality of first semiconductor layers and a plurality of second semiconductor layers. The plurality of first semiconductor layers and the plurality of second semiconductor layers are interleaved. A PIN diode is formed in the active region. The PIN diode includes a P-type component, an N-type component, and an undoped component disposed between the P-type component and the N-type component. A first interconnect structure is formed over a first side of the PIN diode. The first interconnect structure includes a first set of interconnect components electrically coupled to the P-type component and a second set of interconnect components electrically coupled to the N-type component. A second interconnect structure is formed over a second side of the PIN diode. The second interconnect structure includes a third set of interconnect components electrically coupled to the P-type component and a fourth set of interconnect components electrically coupled to the N-type component. The first set of interconnect components is electrically connected to the third set of interconnect components. The second set of interconnect components is electrically connected to the fourth set of interconnect components. BRIEF DESCRIPTION OF DRAWINGS

[0007] Aspects of the utility model are best understood from the following detailed description when read in conjunction with the accompanying drawings. To the extent that the figures illustrate shapes of the various features shown in the figures, these shapes are not intended to il lustrate limits of the utility model, unless otherwise explicitly stated herein. Indeed, the utility model can be applied to other shapes as long as they have the properties as described herein.

[0008] Figure 1A A three-dimensional perspective view of a FinFET device is shown.

[0009] Figure 1B A top view of a FinFET device is shown.

[0010] Figure 1C A three-dimensional perspective view of a multi-channel gate-all-around (GAA) device is shown.

[0011] Figure 2A A top view of a diode structure.

[0012] Figure 2B A cross-sectional view of a diode structure.

[0013] Figure 2C A three-dimensional perspective view of a diode structure.

[0014] Figures 3-12 A series of cross-sectional side views of an IC device at various stages of manufacture in accordance with aspects of the utility model are shown.

[0015] Figure 13 A block diagram of a manufacturing system in accordance with aspects of the utility model is shown.

[0016] Figures 14-15 A flowchart of a method of fabricating an IC according to various aspects of the present disclosure is shown. DETAILED DESCRIPTION

[0017] The following disclosure provides many different embodiments, or examples, for implementing different characteristics of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, forms a first feature over or on top of a second feature in the description below can include embodiments where the first and second features are formed in direct contact, and can also include embodiments where additional features can be formed between the first and second features, such that the first and second features can not be directly in contact. In addition, the present disclosure can repeat certain

[0018] Furthermore, spatial or directional terms, such as "below," "above," "lower," "upper," and the like can be used herein for ease of describing one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the figures. The device can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0019] Still further, when numerical or other quantitative values are described herein, such terms are used in their broadest context, for example, to include values that fall within a range of values, for example, ±10% of a stated value or other value. For example, the term "about 5 nm" encompasses a range of sizes from 4.5 nm to 5.5 nm.

[0020] The present disclosure generally relates to improving performance of integrated circuit (IC) devices that include diode structures. More specifically, the diode structures can be formed as a type of passive IC component. For example, the diode structures can be formed by doping a portion of a semiconductor material with P-type dopants and doping another portion of the semiconductor material with N-type dopants. In this manner, a PN junction of a diode can be formed. The diode structures can also include PIN diodes, where the P-type component and the N-type component of the diode structure are separated by an undoped semiconductor component (also referred to as an intrinsic component).

[0021] As semiconductor devices continue to shrink in size, three-dimensional transistor devices such as FinFET or multi-gate all-around (GAA) devices have become increasingly popular in recent years. To ensure compatibility with the manufacture of these three-dimensional transistors, fin diodes (compatible with FinFET manufacture) or lateral PIN diodes (compatible with GAA manufacture) can be formed on an IC in which the three-dimensional transistors are formed. However, there are still certain challenges in the manufacture of these diodes. For example, in a lateral PIN diode manufactured with a GAA transistor, a dielectric structure can be located near the lateral PIN diode. The manufacture of the GAA transistor can involve various etching processes in which positively charged plasma can be used. The positively charged plasma can enter the portion of the IC in which the lateral PIN diode structure is formed. For example, some of the positively charged particles can enter the dielectric structure located near the lateral PIN diode. The presence of the positively charged particles in the dielectric structure can attract electrons. Unfortunately, when a sufficient amount of electrons gather near the surface of the dielectric structure, it can adversely affect the performance of the lateral PIN diode. For example, these electrons can cause unexpected voltage fluctuations, which are undesirable. The junction capacitance of the diode and / or the reverse current of the diode can also be affected, resulting in degraded device performance.

[0022] The present utility embodiments various charge potential equivalence control (CPEC) structures to address the above issues. In some embodiments, the CPEC structures can include additional electrical interconnect structures. These additional electrical interconnect structures (e.g., vias and metal lines) can be used to prevent positively charged plasma from entering the IC device, thereby preventing the accumulation of electrons near the dielectric structure. In this way, the additional electrical interconnect structures (as embodiments of the CPEC structures) can eliminate or reduce the potential damage caused by the presence of the plasma. In some other embodiments, the CPEC structures can include one or more additional P-type doped regions formed between the PIN diode and the dielectric structure. The P-type doped regions attract electrons that would otherwise be attracted to the surface of the dielectric structure. The electrons attracted by the P-type doped regions can cancel each other out (e.g., cancel each other out in terms of charge). In this way, the problem of excessive electron accumulation near the dielectric structure can also be mitigated, which in turn can improve device performance.

[0023] Reference is now made to Figure 1A , Figure 1B , Figure 1C , Figure 2A , Figure 2B , Figure 2C and Figures 3-15Each aspect of the present application is discussed in more detail. In more detail, Figure 1A -B shows an exemplary FinFET device, and Figure 1C An exemplary GAA device is shown. Figures 2A-2C An upper view, a cross-sectional side view, and a three-dimensional perspective view of a diode are shown. Figures 3-12 Cross-sectional side views of portions of IC devices at various stages of fabrication according to embodiments of the present application are shown. Figure 13 A semiconductor manufacturing system that can be used to fabricate IC devices of the present application is shown. Figures 14-15 Methods of fabricating IC devices according to various aspects of the present application are each shown.

[0024] Reference is now made to Figure 1A and Figure 1B , respectively, show a three-dimensional perspective view and an upper view of a portion of an integrated circuit (IC) device 90. The IC device 90 is implemented using a field effect transistor (FET) such as a three-dimensional fin-line FET (FinFET). The FinFET device has a semiconductor fin structure that protrudes vertically from a substrate. The fin structure is an active region from which source / drain regions and / or channel regions are formed. The source / drain regions can refer to either a source or a drain, individually or collectively, depending on the context. The source / drain regions can also refer to regions that provide a source and / or a drain for multiple devices. A gate structure partially encircles the fin structure. In recent years, FinFET devices have gained popularity due to their higher performance than traditional planar transistors.

[0025] As Figure 1AAs shown, the IC device 90 includes a substrate 110. The substrate 110 can include elemental (single element) semiconductors such as silicon, germanium, and / or other suitable materials; compound semiconductors such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, and / or other suitable materials; alloy semiconductors such as SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, and / or other suitable materials. The substrate 110 can be a single layer of material having a uniform composition. Alternatively, the substrate 110 can include multiple layers of material having similar or different compositions suitable for IC device fabrication. In one example, the substrate 110 can be a silicon-on-insulator (SOI) substrate having a semiconductor silicon layer formed on a silicon oxide layer. In another example, the substrate 110 can include a conductive layer, a semiconductor layer, a dielectric layer, other layers, or combinations thereof. Various doped regions such as source / drain regions can be formed in or on the substrate 110. The doped regions can be doped with n-type dopants such as phosphorus or arsenic, and / or p-type dopants such as boron, as required by design. The doped regions can be formed directly on the substrate 110, in a p-well structure, in an n-well structure, in a dual-well structure, or using a raised structure. The doped regions can be formed by implantation of dopant atoms, in-situ doped epitaxial growth, and / or other suitable techniques.

[0026] A three-dimensional active region 120 is formed on the substrate 110. The active region 120 can include an elongated fin structure that protrudes upward from the substrate 110. Thus, the active region 120 can be interchangeably referred to as a fin structure 120 or a fin 120 hereinafter. The fin structure 120 can be fabricated using suitable processes including photolithography and etching processes. The photolithography process can include forming a photoresist layer covering the substrate 110, exposing the photoresist to a pattern, performing a post-exposure bake process, and developing the photoresist to form a mask member (not shown) including the photoresist. Then, the mask member is used to etch recesses in the substrate 110, leaving the fin structure 120 on the substrate 110. The etching process can include dry etching, wet etching, reactive ion etching (RIE), and / or other suitable processes. In some embodiments, the fin structure 120 can be formed by a double patterning or multiple patterning process. Generally, a double patterning or multiple patterning process combines a photolithography process with a self-alignment process, allowing a pattern to be created with a smaller pitch, for example, than is obtainable using a single direct photolithography process. As an example, a layer can be formed on a substrate and patterned using a photolithography process. A spacer is formed along the patterned layer using a self-alignment process. The layer is then removed, and the remaining spacer or mandrel can be used to pattern the fin structure 120.

[0027] The IC device 90 also includes source / drain assemblies 122 formed over the fin structures 120. The source / drain assemblies 122 (also referred to as source / drain regions) can individually or collectively refer to the source or drain of a transistor, depending on the context. The source / drain assemblies 122 can include an epitaxial layer that is epitaxially grown on the fin structures 120. The IC device 90 also includes isolation structures 130 formed over the substrate 110. The isolation structures 130 electrically isolate the various components of the IC device 90. The isolation structures 130 can include silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), low-k dielectric materials, and / or other suitable materials. In some embodiments, the isolation structures 130 can include shallow trench isolation (STI) assemblies. In one embodiment, the isolation structures 130 are formed during the formation of the fin structures 120 by etching trenches in the substrate 110. The trenches can then be filled with the aforementioned isolation materials, followed by a chemical mechanical planarization (CMP) process. Other isolation structures such as field oxide, local oxidation of silicon (LOCOS), and / or other suitable structures can also be implemented as the isolation structures 130. Alternatively, the isolation structures 130 can include a multi-layer structure, e.g., having one or more layers of thermal oxide spacers.

[0028] The IC device 90 also includes gate structures 140 formed on and embedded with the fin structures 120 in the channel regions of each fin 120. In other words, the gate structures 140 each surround the plurality of fin structures 120. The gate structures 140 can be dummy gate structures (e.g., comprising an oxide gate dielectric and a polysilicon gate electrode), or they can be high-k metal gate (HKMG) structures comprising a high-k gate dielectric and a metal gate electrode, where the HKMG structures are formed by replacing the dummy gate structures. Although not shown herein, the gate structures 140 can include additional layers of material, such as an interface layer over the fin structures 120, a cap layer, other suitable layers, or combinations thereof.

[0029] Referring to Figures 1A-1B The plurality of fin structures 120 are each longitudinally oriented along the X-direction, and the plurality of gate structures 140 are each longitudinally oriented along the Y-direction, i.e., substantially perpendicular to the fin structures 120. In many embodiments, the IC device 90 includes additional components, such as gate spacers disposed along the sidewalls of the gate structures 140, a hardmask layer disposed over the gate structures 140, and many other components.

[0030] Figure 1C A three-dimensional perspective view of an exemplary multi-channel gate-all-around (GAA) device 150 is shown. The GAA device has a plurality of elongated nanostructure channels, which can be implemented as nanotubes, nanosheets, or nanowires. For reasons of consistency and clarity, Figure 1C and Figures 1A-1BSimilar components in FIGS. 1-3 will be labeled with the same component symbol. For example, the active regions such as fin structures 120 rise vertically upward from the substrate 110 in the Z direction. The isolation structures 130 provide electrical isolation between the fin structures 120. The gate structures 140 are located above the fin structures 120 and above the isolation structures 130. A layer 155 is located above the gate structures 140, and a gate spacer structure 160 is located on the sidewalls of the gate structures 140. A cap layer 165 is formed on the fin structures 120 to protect the fin structures 120 from oxidation during formation of the isolation structures 130.

[0031] A plurality of nanostructures 170 are disposed on each of the fin structures 120. The nanostructures 170 can include nanosheets, nanotubes, or nanowires, or some other type of nanostructure that extends horizontally along the X direction. The portions of the nanostructures 170 that are beneath the gate structures 140 can function as channels for the GAA devices 150. Dielectric intra-spacers 175 can be disposed between the nanostructures 170. Additionally, although not shown for simplicity reasons, the nanostructures 170 of each stack can be circumferentially wrapped by a gate dielectric. In the illustrated embodiment, the portions of the nanostructures 170 that are outside of the gate structures 140 can function as source / drain components for the GAA devices 150. However, in some embodiments, a continuous source / drain component can be epitaxially grown on the portions of the fin structures 120 that are outside of the gate structures 140. Regardless, conductive source / drain contacts 180 can be formed on the source / drain components to provide electrical connection thereto. An interlayer dielectric (ILD) 185 is formed above the isolation structures 130 around the gate structures 140 and the source / drain contacts 180. The ILD 185 can be referred to as an ILD0 layer. In some embodiments, the ILD 185 can include silicon oxide, silicon nitride, or a low-k dielectric material.

[0032] Figures 1A-1B FinFET devices and Figure 1CThe GAA devices can be used to implement circuits with various functions, such as memory devices (e.g., static random access memory (SRAM) devices), logic circuits, input / output (as a non-limiting example, I / O) devices, application-specific integrated circuit (ASIC) devices, radio frequency (RF) circuits, drivers, microcontrollers, central processing units (CPUs), image sensors, etc. At the same time, the manufacturing process for manufacturing FinFET devices or GAA devices can also be used to form certain types of passive devices, such as diodes. The diodes can be formed on the same wafer as the FinFET devices or GAA devices. As described above, during the manufacturing process of the diodes, positively charged plasma may enter the wafer, which may cause damage and / or reduce device performance. According to various aspects of the present invention, a charge potential equivalence control (CPEC) structure can be implemented to alleviate potential problems caused by positively charged plasma entering the wafer, as discussed in detail below.

[0033] Figure 2A 、 Figure 2B 、 Figure 2C 1 shows a top view, a cross-sectional side view, and a three-dimensional perspective view of an exemplary diode formed according to various aspects of the present invention. The PIN diode 200 includes an active region 210 (also referred to as OD), which can be formed as a fin structure (in the case of a FinFET device) or as a stack of alternating semiconductor layers (in the case of a GAA device). As a non-limiting example, the active region 210 herein is used to form a GAA device (e.g., as described above with reference to FIG. Figure 1C The active region 210 is formed using a process similar to that of the GAA device 150 discussed above. Thus, the active region 210 includes a stack of alternating semiconductor layers 220 and 230. The semiconductor layers 220 and 230 have different material compositions. For example, the semiconductor layer 220 may include silicon, while the semiconductor layer 230 may include silicon germanium, or vice versa. It should be understood that the active region 210 herein is formed simultaneously with the active region of the GAA device (i.e., using the same manufacturing process as used to form the GAA device).

[0034] As described above, the active region 210 formed by these interleaved semiconductor layers 220 and 230 can be used to define a channel region and / or a source / drain region of a GAA transistor. However, in the case of the PIN diode 200, the active region 210 provides an area in which a P-type component, an N-type component, and an intrinsic component of the PIN diode 200 can be formed. In more detail, an implantation process can be performed to implant P-type dopants (e.g., boron) into a portion of the active region 210, thereby forming the P-type component 200A. Another implantation process can be performed to implant N-type dopants (e.g., arsenic or phosphorus) into another portion of the active region 210, thereby forming the N-type component 200B. The P-type component 200A and the N-type component 200B of the PIN diode 200 are separated by an undoped portion of the active region 210, which can also be referred to as an intrinsic portion of the PIN diode 200.

[0035] As shown in Figure 2A , the P-type component 200A, the N-type component 200B, and the intrinsic portion (e.g., the portion of the undoped active region 210 between the P-type component 200A and the N-type component 200B) have different lateral dimensions 270, 271, and 272, respectively. In some embodiments, the lateral dimension 271 is greater than the lateral dimension 272, which is greater than the lateral dimension 270. For example, the ratio between the lateral dimension 270 and the lateral dimension 271 can be in a range between about 1 :3 and about 1 :3.4, and the ratio between the lateral dimension 270 and the lateral dimension 272 can be in a range between about 1 :2.6 and about 1 :3. These ratios can be specified by design rules to comply with the fabrication of GAA devices.

[0036] As shown in Figure 2B and 2C , a dielectric structure 250 is disposed below the PIN diode 200. In some embodiments, the dielectric structure 250 includes a silicon nitride layer. In some embodiments, the dielectric structure 250 includes multiple dielectric layers, such as a silicon nitride layer and a silicon oxide layer. As described above and to be discussed in further detail below, positively charged plasma can enter the dielectric structure 250, which will then attract electrons around the interface between the dielectric structure 250 and the PIN diode 200. These electrons can affect voltage potential, increase parasitic capacitance, and / or degrade other diode performance parameters. Accordingly, the present disclosure implements a CPEC structure to eliminate or at least reduce the presence of these electrons, thereby improving device performance.

[0037] Figure 3 is a cross-sectional side view of a portion of an IC device 300 that includes the PIN diode 200. Figure 3Issues related to the positively charged plasma discussed above are facilitated. In more detail, the PIN diode 200 includes a P-type component 200A, an N-type component 200B, and an undoped portion of the active region 210. The P-type component 200A and the N-type component 200B each extend vertically through the semiconductor layers 220 and 230 in multiple interleaving pairs. Note that multiple isolation structures 305 are also formed in the portion of the IC device 300 shown. In some embodiments, the isolation structures 305 include shallow trench isolation (STI) structures. The PIN diode 200 is formed between the isolation structures 305. Figure 3

[0038] Since the fabrication of the PIN diode 200 here is done using the same fabrication process flow as used to fabricate a GAA device (e.g., a transistor similar to the GAA device 150, but formed in another portion of the IC device 300), other components related to GAA fabrication can also be formed in the area of the IC device 300 containing the PIN diode 200. For example, a gate structure 310 can be formed on the intrinsic portion of the PIN diode 200 (e.g., on a portion of the active region 210 between the P-type component 200A and the N-type component 200B). Further, a conductive contact 320A and a conductive contact 320B can be formed over the P-type component 200A and the N-type component 200B of the PIN diode 200, respectively. Corresponding portions of the conductive contacts 320A and 320B in the GAA portion of the IC device 300 can function as source / drain contacts. However, the conductive contacts 320A and 320B can function as conduits that allow charges to enter the IC device 300. Figure 1C

[0039] In more detail, during fabrication of a GAA device, multiple etching processes can be performed. Some of the etching processes can involve the application of a positively charged plasma, which is represented by the component symbol 350 in Figure 3 Since the conductive contacts 320A and 320B are electrically conductive, they can provide an easy electrical path for the positively charged plasma 350 to enter the IC device 300. For example, the positively charged plasma 350 can enter the dielectric structure 250 through the conductive contacts 320A and 320B and / or through other electrically conductive components. As a result, the dielectric structure 250 can become positively charged. In Figure 3 ​​In particular, this is represented by a plurality of positively charged particles 360 in the dielectric structure 250. The presence of the positively charged particles 360 in the dielectric structure 250 can attract electrons 370 at or near the interface between the dielectric structure 250 and the active region 210 (e.g., a portion of a silicon substrate). The presence of the electrons 370 can result in unintended voltage fluctuations and / or degradation of the junction capacitance of the diode and / or reverse current of the PIN diode 200, which can be undesirable.

[0040] Figure 4 A conceptual block diagram of a CPEC structure 400 for mitigating issues related to positively charged plasma 350 according to a first embodiment of the present application is shown. In more detail, the CPEC structure 400 includes a via 410A and a via 410B that are electrically coupled to the P-type component 200A and the N-type component 200B of the PIN diode 200, respectively. The conductive pads 320A and 320B are formed over a side 430 of the PIN diode 200, while the vias 410A and 410B are formed on a side 431 of the PIN diode 200 that is opposite the side 430. The conductive pad 320A and the via 410A are electrically coupled together by a set of electrical interconnect structures (e.g., vias and metal lines) 460A such that a first voltage can be applied to both the conductive pad 320A and the via 410A through a conductive pad 450A. In this manner, both sides (e.g., the side 430 and the side 431) of the P-type component 200A of the PIN diode 200 are forced to the same potential, which prevents the positively charged plasma 350 from entering the IC device 300 through the P-type component 200A.

[0041] Likewise, the conductive pad 320B and the via 410B are electrically coupled together by a set of electrical interconnect structures (e.g., vias and metal lines) 460B such that a second voltage can be applied to both the conductive pad 320B and the via 410B through a conductive pad 450B. Again, both sides (e.g., the side 430 and the side 431) of the N-type component 200B of the PIN diode 200 are forced to the same potential, which prevents the positively charged plasma 350 from entering the IC device 300 through the N-type component 200B.

[0042] Figure 5 A conceptual block diagram of a CPEC structure 400 for mitigating issues related to positively charged plasma 350 according to a first embodiment of the present application is shown. In more detail, the CPEC structure 400 includes a via 410A and a via 410B that are electrically coupled to the P-type component 200A and the N-type component 200B of the PIN diode 200, respectively. The conductive pads 320A and 320B are formed over a side 430 of the PIN diode 200, while the vias 410A and 410B are formed on a side 431 of the PIN diode 200 that is opposite the side 430. The conductive pad 320A and the via 410A are electrically coupled together by a set of electrical interconnect structures (e.g., vias and metal lines) 460A such that a first voltage can be applied to both the conductive pad 320A and the via 410A through a conductive pad 450A. In this manner, both sides (e.g., the side 430 and the side 431) of the P-type component 200A of the PIN diode 200 are forced to the same potential, which prevents the positively charged plasma 350 from entering the IC device 300 through the P-type component 200A. Figure 4FIG. 4 illustrates a cross-sectional side view of a portion of the IC device 300 of the CPEC structure 400. More specifically, the interconnect structure 500 is formed on the side 430 of the PIN diode 200. The interconnect structure 500 includes a plurality of metal layers containing metal lines that are interconnected together by a plurality of vias. For example, the interconnect structure 500 includes vias 510A-514A and 510B-514B, and metal lines 520A-524A and 520B-524B. It should be understood that the vias and metal lines of the interconnect structure 500 shown in FIG. 4 are provided for simplicity of example only and are not meant to be limiting unless otherwise stated. Figure 5

[0043] One subset of the interconnect structure 500 provides electrical connections to the P-type component 200A of the PIN diode 200, and another subset of the interconnect structure 500 provides electrical connections to the N-type component 200B of the PIN diode 200. For example, the vias 510A-514A and the metal lines 520A-524A are electrically coupled to the P-type component 200A of the PIN diode 200 through the conductive contacts 320A. Similarly, the vias 510B-514B and the metal lines 520B-524B are electrically coupled to the N-type component 200B of the PIN diode 200 through the conductive contacts 320B.

[0044] Meanwhile, the interconnect structure 550 is formed on the side 431 of the PIN diode 200. The interconnect structure 550 can also include a plurality of metal layers containing metal lines and vias. For example, the interconnect structure 550 includes vias 410A-411A and 410B-411B, each of which extends vertically through the dielectric structure 250. The interconnect structure 550 also includes metal lines 420A-421A and 420B-421B, and the conductive pads 450A and 450B discussed above in connection with Figure 4 Figure 4 Figure 4 Figure 5 It should be understood that the vias and metal lines or the interconnect structure 550 shown in FIG. 4 are provided for simplicity of example only and are not meant to be limiting unless otherwise stated.

[0045] As with the interconnect structure 500 discussed above in connection with Figure 4 ​​​​As discussed, via hole 410A provides electrical access to P-type component 200A of PIN diode 200. Since conductive pad 450A is electrically coupled to via hole 410A through metal lines 420A-421A and via hole 411A, a voltage can be applied to P-type component 200A through conductive pad 450A when IC device 300 is in operation. Similarly, via hole 410B provides electrical access to N-type component 200B of PIN diode 200 when IC device 300 is in operation. Since conductive pad 450B is electrically coupled to via hole 410B through metal lines 420B-421B and via hole 411B, a voltage can be applied to N-type component 200B through conductive pad 450B.

[0046] According to various aspects of the present disclosure, interconnect structure 500 and interconnect structure 550 are electrically coupled together such that the same first voltage can be applied to side 430 and side 431 of P-type component 200A, and the same second voltage can be applied to side 430 and side 431 of N-type component 200B. For example, metal line 420A of interconnect structure 550 is electrically coupled to a portion of interconnect structure 500 that includes vias 510A-514A and metal lines 520A-524A. In other words, there can be a plurality of metal lines and vias between metal line 420A and metal line 524A, but these are not specifically shown here for simplicity. Metal line 420A is also electrically coupled to via hole 410A, which is electrically coupled from side 431 to P-type component 200A. Thus, when a first voltage is applied to conductive pad 450A, metal line 420A, as well as via hole 410A and conductive pad 320A, will experience the same first voltage (through the electrical coupling with vias 510A-514A and metal lines 520A-524A).

[0047] In a similar manner, when a second voltage is applied to conductive pad 450B, metal line 420B, as well as via hole 410B and conductive pad 320B, will experience the same second voltage (through the electrical coupling with vias 510B-514B and metal lines 520B-524B). In other words, the first voltage can have two paths to P-type component 200A through side 430 and side 431, and the second voltage can have two paths to N-type component 200B through side 430 and side 431, but the voltage potential of either of these paths is the same. In this way, positively charged plasma has a difficult time entering IC device 300, since the substantially identical voltage potential of the two electrical paths will effectively prevent charged particles from entering. In this manner, it can be said that CPEC structure 400, including portions of both interconnect structures 500 and 550, can prevent positively charged plasma from entering IC device 300, which in turn can reduce damage caused by positively charged plasma and improve device performance.

[0048] It should be appreciated that Figure 5 The portion of the IC device 300 shown is at an intermediate stage of fabrication. For example, at this stage, the interconnect structure 500 of the IC device 300 is bonded to the carrier wafer 560 by the bonding layer 570. Subsequent fabrication processing can remove the IC device 300 from the carrier wafer 560 (and the bonding layer 570).

[0049] Figures 4-5 A first embodiment of the CPEC structure 400 according to various aspects of the present disclosure is shown. Figures 6-9 A second embodiment of the CPEC structure 400 according to various aspects of the present disclosure is shown. According to the second embodiment, the CPEC structure 400 does not utilize an additional interconnect component to balance the voltage potential at the side 430 and the side 431 of the PIN diode 200. Rather, Figures 6-9 The CPEC structure 400 in the second embodiment includes one or more doped regions formed in a substrate (e.g., a silicon substrate) of the active region 210. The formation of the one or more doped regions will be discussed below with reference to Figures 6-9 For reasons of clarity and consistency, similar components appearing in Figures 4-5 will be labeled with the same component designators in Figures 6-9 .

[0050] In more detail, Figures 6-8 are cross-sectional side views of a portion of the IC device 300 at various fabrication stages according to the second embodiment of the present disclosure. Reference is now made to Figure 6 One or more etching processes 580 are performed on the IC device 300 from the side 431. In some embodiments, the one or more etching processes 580 can include dry etching processes, or in some other embodiments can include wet etching processes. It should be appreciated that the one or more etching processes 580 can also be performed simultaneously on another portion of the IC device 300 containing a GAA transistor, forming via trench openings to establish electrical connections from the side 431 to the GAA transistor. For Figure 6 The etching processes 580 etch one or more trench openings, such as via trench openings 590A and 590B, in the portion of the IC device 300 shown. The via trench openings 590A and 590B each extend vertically through the dielectric structure 250 and a portion of the active region 210. However, the via trench openings 590A and 590B are not etched deep enough to expose the P-type component 200A or the N-type component 200B of the PIN diode 200 at the side 431. Note that at this fabrication stage, the positively-charged particles 360 can already be present in the dielectric structure 250, which can then attract the electrons 370 to accumulate near the interface between the dielectric structure 250 and the active region 210.

[0051] Referring now to Figure 7 A dopant implant process 610 is performed to implant dopant material from the side 431 through the via trench openings 590A and 590B into the active region 210. In some embodiments, the dopant implant process 610 implants a P-type dopant material (e.g., boron) into the active region 210. The implanted dopant material forms one or more doped regions in the active region, depending on the number (and / or size) of via trench openings through which the dopant material is implanted. In Figure 7 In the illustrated embodiment, the doped regions 600A and 600B (e.g., P-type boron-containing doped regions) are formed in the active region 210 as part of the CPEC structure 400. Since the dopant implant process 610 is performed from the side 431, the doped regions 600A and 600B each extend from the side 431 toward the side 430. In Figure 7 In the illustrated embodiment, the doped regions 600A and 600B can merge laterally with one another, although it should be appreciated that in other embodiments they can be spaced apart from one another.

[0052] The doped regions 600A and 600B are disposed above the via holes 410A and 410B, respectively. This is because the via trench openings 590A and 590B are aligned with the via holes 410A and 410B, respectively. In accordance with various aspects of the present disclosure, since the doped regions 600A and 600B contain P-type dopants, they will attract and neutralize at least a subset of the electrons 370 that would otherwise be attracted to the interface between the dielectric structure 250 and the substrate of the active region 210. In this manner, the presence of the doped regions 600A and 600B will reduce the number of electrons 370 that accumulate near the dielectric structure 250, even though the dielectric structure 250 still contains positively charged particles 360. In this manner, potential damage to the IC device 300 can be reduced, and / or the performance of the IC device 300 can be improved.

[0053] It should be appreciated that the location and / or size of the doped regions 600A and 600B can be flexibly configured by adjusting various manufacturing process parameters of the present disclosure. For example, the location of each of the doped regions 600A and 600B is primarily dependent on the location of the via trench openings 590A and 590B through which the dopant material is implanted. In other words, the doped region 600A can be substantially vertically aligned with the via trench opening 590A, and the doped region 600B can be substantially vertically aligned with the via trench opening 590B.

[0054] The widths (lateral dimensions) of the doped regions 600A and 600B are also related to the widths of the via trench openings 590A and 590B, respectively. Thus, adjusting the widths of the via trench openings 590A and 590B can also affect the widths of the doped regions 600A and 600B. However, it should be understood that the widths of the via trench openings 590A and 590B are generally set according to the design and / or fabrication specifications of the transistors (e.g., GAA transistors) in different portions of the IC device 300. In other words, the fabrication process that etches (and subsequently fills) the via trench openings 590A and 590B is the same process used to form vias for GAA devices (e.g., as different portions of the IC device 300) on the same wafer. Since GAA fabrication can be the primary concern, the dimensions of the via trench openings 590A and 590B can also be mostly inherited from the GAA transistor fabrication.

[0055] However, the number of via trench openings 590A and 590B can still be configured to effectively adjust the widths of the overall doped regions 600A-600B, since when a sufficient number of trench openings are formed, the doped regions 600A-600B can merge with each other, and the doped regions 600A-600B can be considered as a single doped region. In Figure 7 In embodiments, the merged doped regions 600A-600B can laterally span from one of the isolation structures 305 to an adjacent isolation structure 305. Thus, the doped regions 600A-600B as a whole can be wider than the P-type doped component 200A and / or the N-type doped component 200B of the PIN diode 200. The wider width of the doped regions 600A-600B can be more advantageous for attracting and neutralizing the electrons 370. However, the dimensions of the doped regions 600A-600B are not too large to interfere with the normal operation of the PIN diode 200.

[0056] The depths 620 (e.g., vertical dimensions) of the doped regions 600A and 600B can also be configured by adjusting parameters of the dopant implantation process. For example, by changing the implantation energy, the depths of the doped regions 600A and 600B can be changed. The depths of the trench openings, which can be dictated by the corresponding GAA process, can also affect the depths of the doped regions 600A and 600B. In Figure 7 In embodiments, the depths 620 of the doped regions 600A and 600B extend into the substrate of the active region 210, but do not reach the P-type doped component 200A or the N-type doped component 200B of the PIN diode 200. This helps to ensure that the doped regions 600A and 600B do not adversely interfere with the normal operation of the PIN diode 200.

[0057] Reference is now made to Figure 8A deposition process 630 is performed on the IC device 300 from the side 431 to fill the via trench openings 590A and 590B with one or more electrically conductive materials. In some embodiments, the deposition process 630 can include a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, an atomic layer deposition (ALD) process, or a combination thereof. A planarization process, such as a chemical mechanical polishing (CMP) process, can also be performed to planarize surfaces of the electrically conductive materials deposited in the via trench openings 590A and 590B, where surfaces of the dielectric structure 250 face the side 431. As a result, the via holes 410A and 410B are formed in the via trench openings 590A and 590B. As mentioned above, via holes similar to the via holes 410A and 410B are also formed in the regions of the IC device 300 that contain GAA devices. Thus, it can be seen that the present application utilizes the manufacturing flow of the GAA regions of the IC device 300 to achieve additional objectives that are tailored to the non-GAA regions (e.g., the PIN diode 200 regions) of the IC device 300, which saves manufacturing costs and processing time.

[0058] Figure 9 A cross-sectional side view of a portion of the IC device 300 implementing the CPEC structure 400 of the first embodiment is shown. Figure 8 For example, Figure 9 The CPEC structure 400 shown also includes doped regions 600A and 600B that are doped with P-type dopants. However, unlike the CPEC structure 400 in Figure 8 The CPEC structure 400 in Figure 9 is configured such that the doped regions 600A and 600B do not merge with each other, but are instead separated by a portion of the active region 210. The doped regions 600A and 600B and their corresponding via holes 410A and 410B, respectively, are vertically aligned with the P-type component 200A and the N-type component 200B of the PIN diode 200.

[0059] As mentioned above, the doped regions 600A and 600B help attract and neutralize electrons that would otherwise accumulate near the upper surface of the dielectric structure 250 due to problems caused by the positively charged plasma. Thus, while the IC device 300 herein does not use the additional interconnect components (e.g., the metal lines 420A and 420B of the first embodiment of the CPEC structure 400) to balance the voltage potential of the PIN diode 200, the positively charged plasma can still be greatly mitigated. It should be understood that the positively charged particles 360 and the electrons 370 are not specifically shown in Figure 5 for simplicity. Figure 9

[0060] To provide additional background for the second embodiment of the present application, Figures 10-12 ​A cross-sectional side view of the GAA portion of IC device 300 is shown undergoing a series of fabrication processes corresponding to the formation of via holes 410A and 410B discussed above. Again, for the sake of clarity and consistency, like components appearing in Figures 4-9 will be labeled with the same component designation in Figures 10-12 . It should also be noted that Figures 10-12 sides 430 and 431 are vertically flipped from Figures 4-9 sides 430 and 431.

[0061] Referring now to Figure 10 , the GAA portion of IC device 300 includes a plurality of GAA transistors 700 as embodiments of GAA device 150 discussed above with reference to Figure 1C . Each GAA transistor 700 can be formed at least in part using active region 210 discussed above. For example, each GAA transistor 700 can include a stack of nanostructure channels (e.g., nanosheets, nanorods, nanotubes, nanowires, etc.) formed using semiconductor layer 220. Semiconductor layer 230 is removed and replaced with metal-containing gate structures 720. For example, metal-containing gate structures 720 can each include a high-k gate dielectric and a metal gate electrode. Another portion of metal-containing gate structures 720 can be disposed over side 431 of the stack of nanostructure channels.

[0062] Source / drain components 730 can also be formed laterally on opposite sides of metal-containing gate structures 720. It should be understood that source / drain components 730 can refer to either a source or a drain, individually or collectively, depending on the context. In some embodiments, source / drain components 730 can be formed by one or more epitaxial growth processes. Source / drain vias 750 can be formed from side 430 of the IC to provide electrical connectivity from side 430 to source / drain components 730. Meanwhile, no electrical interconnects have been formed from side 431 of GAA transistors 700 at this stage of fabrication. Dielectric structure 250, which can include dielectric layer 250A (e.g., silicon oxide) and dielectric layer 250B (e.g., silicon nitride), can be disposed over GAA transistors 700 at the stage of fabrication shown in Figure 10 .

[0063] Referring now to Figure 11 , one or more etch processes 580 discussed above with reference to Figure 6 are also performed with respect to a portion of IC device 300. One or more etch processes 580 also etch through dielectric layers 250A and 250B and a portion of active region 210 to expose source / drain components 730. As a result, via trench openings 590C, 590D, and 590E are formed. As discussed above, Figure 11 via trench openings 590C, 590D, and 590E of Figure 6The via trench openings 590A and 590B are formed at the same time (and using the same manufacturing process / steps).

[0064] Reference is now made to Figure 12 A deposition process 630 is performed on the IC device 300 to fill the via trench openings 590C-590E with a conductive material, thereby forming the vias 410C-410E. As mentioned above, Figure 12 The vias 410C, 410D and 410E are formed at the same time (and using the same manufacturing flow / steps) as the vias 410A-410B. The vias 410C-410E are electrically coupled from the side 431 to the source / drain assembly 730, and provide electrical connectivity from the side 431 to the source / drain assembly 730 accordingly. Figure 8 Based on the process of the GAA transistor 700,

[0065] The formation of the CPEC structure 400 is fully compatible with the process used to manufacture the GAA transistor 700. This way, manufacturing costs and / or processing time can be reduced. Figures 10-12 Figures 8-9 The formation of the CPEC structure 400 is fully compatible with the process used to manufacture the GAA transistor 700. This way, manufacturing costs and / or processing time can be reduced.

[0066] Figure 13 An integrated circuit (IC) manufacturing system 900 according to an embodiment of the present application is shown, which can be used to manufacture the IC device 300 of the present application. The IC manufacturing system 900 includes a plurality of entities 902, 904, 906, 908, 910, 912, 914, 916,..., N connected through a communication network 918. The communication network 918 can be a single network or can be various different networks, such as an intranet and the Internet, and can include wired and wireless communication channels.

[0067] In one embodiment, entity 902 represents a service system for manufacturing collaboration; entity 904 represents a user, such as a product engineer monitoring a product of interest; entity 906 represents an engineer, such as a process engineer controlling a process and related recipe, or a facility engineer monitoring or adjusting conditions and settings of a process tool; entity 908 represents a metrology tool for IC testing and measurement; entity 910 represents a semiconductor processing tool, such as an EUV tool for performing a lithography process; entity 912 represents a virtual metrology module associated with the processing tool 910; entity 914 represents a high level process control module associated with the processing tool 910 and with additional other processing tools; and entity 916 represents a sampling module associated with the processing tool 910.

[0068] ​Each entity can interact with other entities and can provide integrated circuit manufacturing, process control, and / or computational capabilities to and / or receive such capabilities from other entities. Each entity can also include one or more computer systems for performing computations and executing automation. For example, a high-level process control module of entity 914 can include a plurality of computer hardware having software instructions encoded therein. The computer hardware can include hard disks, flash drives, CD-ROMs, RAM storage, display devices (e.g., monitors), input / output devices (e.g., mice and keyboards). The software instructions can be written in any suitable programming language and can be designed to perform specific tasks.

[0069] The integrated circuit (IC) manufacturing system 900 enables interaction between entities to enable integrated circuit (IC) manufacturing and advanced process control of IC manufacturing. For example, advanced process control includes adjusting process conditions, settings, and / or recipes for a process tool applicable to a relevant wafer based on metrology results.

[0070] In another embodiment, metrology results are measured from a subset of processed wafers according to an optimal sampling rate determined based on process quality and / or product quality. In yet another embodiment, metrology results are measured from selected fields and points of the subset of processed wafers according to an optimal sampling field / point determined based on various characteristics of process quality and / or product quality.

[0071] One function provided by the IC manufacturing system 900 can enable collaboration and information access in the areas of design, engineering, and process, metrology, and advanced process control. Another function provided by the IC manufacturing system 900 can integrate systems between facilities, such as between metrology tools and process tools. Such integration enables facilities to coordinate their activities. For example, integrating metrology tools and process tools can enable manufacturing information to be more effectively incorporated into manufacturing flows or APC modules, and can enable wafer data from on-line or in-situ measurements using integrated metrology tools in related processes.

[0072] Figure 14 is a flowchart illustrating a method 1000 of manufacturing an IC device in accordance with various aspects of the present disclosure. The method 1000 includes a step 1010 of forming an active region including a plurality of interleaved first and second semiconductor layers.

[0073] The method 1000 includes a step 1020 of doping a first portion of the active region with a P-type dopant.

[0074] The method 1000 includes a step 1030 of doping a second portion of the active region with an N-type dopant. The second portion of the active region is separated from the first portion of the active region by a third portion of the active region that is not doped.

[0075] The method 1000 includes forming a first interconnect structure over a first side of the first portion of the active region and over a first side of the second portion of the active region such that the first portion of the active region is electrically coupled to a first set of interconnect components of the first interconnect structure through the first side and the second portion of the active region is electrically coupled to a second set of interconnect components of the first interconnect structure through the first side, at step 1040.

[0076] The method 1000 includes forming a second interconnect structure over a second side of the first portion of the active region and over a second side of the second portion of the active region such that the first portion of the active region is electrically coupled to a third set of interconnect components of the second interconnect structure through the second side and the second portion of the active region is electrically coupled to a fourth set of interconnect components of the second interconnect structure through the second side, at step 1050. The first set of interconnect components is electrically coupled to the third set of interconnect components. The second set of interconnect components is electrically coupled to the fourth set of interconnect components.

[0077] In some embodiments, the dielectric structure is formed over the second side of the active region. In some embodiments, forming the second interconnect structure includes etching a first trench and a second trench through the dielectric structure from the second side toward the first side such that the first trench exposes a portion of the first portion of the active region from the second side and such that the second trench exposes a portion of the second portion of the active region from the second side, and filling the first trench and the second trench with a conductive material, thereby forming a first via in the first trench and a second via in the second trench.

[0078] In some embodiments, the dielectric structure includes a plurality of dielectric layers; the active region is formed on a semiconductor substrate. The first trench and the second trench are etched to extend through the plurality of dielectric layers and at least partially through the semiconductor substrate.

[0079] In some embodiments, forming the second interconnect structure further includes forming a first metal line over a second side of the first via and a second metal line over a second side of the second via.

[0080] In some embodiments, the first metal line and the first via are part of the third set of interconnect components of the second interconnect structure; the second metal line and the second via are part of the fourth set of interconnect components of the second interconnect structure; the first set of interconnect components is electrically coupled to a first side of the first metal line, and the second set of interconnect components is electrically coupled to a first side of the second metal line.

[0081] In some embodiments, the first portion of the active region, the second portion of the active region, and the third portion of the active region collectively form a PIN diode; forming the second interconnect structure further comprises forming a first contact pad and a second contact pad over the second side of the first metal line and the second metal line, respectively; the first contact pad is configured to receive a first voltage for a P-terminal of the PIN diode; the second contact pad is configured to receive a second voltage for an N-terminal of the PIN diode.

[0082] It should be appreciated that additional processes can be performed before, during, or after steps 1010-1050 of method 1000. For example, in some embodiments, method 1000 can further include a step of biasing the first set of interconnect components and the third set of interconnect components to a same first voltage, and a step of biasing the second set of interconnect components and the fourth set of interconnect components to a same second voltage bias. As another example, method 1000 can include a step of fabricating a gate-all-around (GAA) device at least partially using the fourth portion of the active region.

[0083] Figure 15 is a flowchart showing a method 1000 of fabricating an IC device according to various aspects of the present disclosure. Method 1000 includes a step 1110 of forming a diode in an active region. The diode includes a P-type component embedded in a first portion of the active region, an N-type component embedded in a second portion of the active region, and an undoped component disposed between the P-type component and the N-type component.

[0084] Method 1000 includes a step 1120 of forming an interconnect structure over a first side of the diode. Different portions of the interconnect structure are electrically coupled to the P-type component and the N-type component, respectively.

[0085] Method 1000 includes a step 1130 of etching one or more openings through a dielectric structure disposed over a second side of the diode opposite the first side.

[0086] Method 1000 includes a step 1140 of implanting a dopant material into the active region through the one or more openings.

[0087] Method 1000 includes a step 1150 of filling the one or more openings with a conductive material.

[0088] In some embodiments, the active region includes a stack of a first semiconductor layer and a second semiconductor layer, the first semiconductor layer and the second semiconductor layer having different material compositions and interleaved with one another. In some embodiments, forming the diode includes implanting P-type dopants in a first portion of the active region and implanting N-type dopants in a second portion of the active region, such that each of the P-type dopants and the N-type dopants crosses at least a subset of the first semiconductor layer and the second semiconductor layer stack.

[0089] In some embodiments, implanting includes implanting boron as the dopant material through the one or more openings.

[0090] In some embodiments, performing the implanting is such that the dopant material implanted into the active region does not reach the P-type component or the N-type component of the diode.

[0091] In some embodiments, performing the etching is such that each of the one or more openings is wider than the P-type component or the N-type component.

[0092] In some embodiments, performing the etching is such that none of the one or more openings exposes the P-type component or the N-type component from the second side.

[0093] It should be appreciated that additional processes can be performed before, during, or after steps 1110-1150 of method 1100. For example, in some embodiments, in which a diode is formed in a first portion of the active region, method 1100 further includes steps to form a gate-all-around (GAA) transistor at least partially in a second portion of the active region. The GAA transistor includes a source / drain component, and the aforementioned etching serves as part of an etching process to etch a source / drain via opening for the source / drain component from the second side.

[0094] In summary, the present disclosure relates to forming a CPEC structure to reduce potential harmful effects on a diode caused by positively charged plasma during fabrication. The present disclosure can provide advantages over conventional devices. However, it should be understood that not all advantages are discussed herein, different embodiments can provide different advantages, and any embodiment need not necessarily exhibit all of the advantages. In this regard, various fabrication processes can involve the use of positively charged plasma, which can result in positively charged particles entering a dielectric structure of an IC device that includes a diode. The presence of positively charged particles can attract electrons at or near the surface of the dielectric structure, which can have an adverse effect on the performance and / or expected operation of the diode. One embodiment of the present disclosure addresses this issue by forming a CPEC structure that includes an additional interconnect component, which can balance the voltage potential on both sides of the diode. As a result, positively charged particles can have difficulty finding a path into the dielectric structure. In turn, the harmful effects associated with positively charged plasma can be reduced. Another embodiment of the present disclosure addresses this issue by forming an additional P-type doped region in an active region near the dielectric structure. The additional P-type doped region is formed by utilizing a via formation process that is also performed to form electrical interconnects for conventional transistors (e.g., GAA transistors) of the IC device, which includes a via trench formation process. After the via trenches are etched but before they are filled, P-type dopant material can be implanted into the active region through the open via trenches, which forms the P-type doped region. The P-type doped region attracts and / or neutralizes electrons that would otherwise accumulate near the dielectric structure. In this manner, the harmful effects associated with positively charged plasma can also be reduced, and device performance can be improved. Other advantages can include compatibility with existing fabrication flows, as well as simplicity and low cost of implementation.

[0095] The advanced lithography processes, methods, and materials described above can be used in many applications, including IC devices that use fin field effect transistors (FinFETs). For example, fins can be patterned to produce relatively tight spacing between features, for which the above-described reveals are well suited. In addition, spacers (also known as mandrels) used to form the fins of a FinFET can be treated in accordance with the above-described reveals. It should also be understood that various aspects of the present disclosure discussed above can be applied to multi-channel devices, such as gate-all-around (GAA) devices. To the extent that the present disclosure relates to fin structures or FinFET devices, such discussion can equally apply to GAA devices.

[0096] One aspect of the present utility model relates to a semiconductor device. The semiconductor device includes a diode, which includes a P-type region, an N-type region, and an undoped intrinsic region. A first conductive contact and a second conductive contact are disposed above a first side of the diode. The first conductive contact is electrically coupled from the first side to the P-type region. The second conductive contact is electrically coupled from the first side to the N-type region. A first conductive via and a second conductive via are disposed above a second side of the diode. The second side is different from the first side. The first conductive via is electrically coupled from the second side to the P-type region. The second conductive via is electrically coupled from the second side to the N-type region. The first conductive contact is electrically coupled to the first conductive via. The second conductive contact is electrically coupled to the second conductive via.

[0097] In some embodiments, the undoped intrinsic region includes a plurality of first semiconductor layers and a plurality of second semiconductor layers, the plurality of first semiconductor layers interleaved with the plurality of second semiconductor layers. In some embodiments, the first semiconductor layers include silicon; and the second semiconductor layers include silicon germanium. In some embodiments, the P-type region includes P-doped portions of the plurality of the first semiconductor layers and the second semiconductor layers; and the N-type region includes N-doped portions of the plurality of first semiconductor layers and the plurality of second semiconductor layers. In some embodiments, the device includes a portion of an integrated circuit (IC); the first conductive contact and the first conductive via are electrically biased to a same first voltage when the portion of the IC is operating; and the second conductive contact and the second conductive via are electrically biased to a same second voltage when the portion of the IC is operating. In some embodiments, the semiconductor device further includes a dielectric layer disposed above the second side of the diode, wherein each of the first conductive via and the second conductive via extends vertically through the dielectric layer. In some embodiments, the semiconductor device further includes a first set of interconnect components disposed above and electrically coupled from the first side to the first conductive contact and the second conductive contact; and a second set of interconnect components disposed above and electrically coupled from the second side to the first conductive via and the second conductive via, wherein the second set of interconnect components is electrically coupled to the first set of interconnect components. In some embodiments, the first set of interconnect components includes a plurality of vias and a plurality of first metal lines; a subset of the plurality of vias is in direct contact with the first conductive contact and the second conductive contact; the second set of interconnect components includes a plurality of second metal lines; a first one of the plurality of second metal lines is in direct contact with the first conductive via; and a second one of the plurality of second metal lines is in direct contact with the second conductive via. In some embodiments, the diode is formed in a first region of the device, and wherein the device further includes a second region in which a plurality of gate-all-around (GAA) transistors are formed.

[0098] Another aspect of the utility model relates to a semiconductor device. The semiconductor device includes an active region, and the active region includes a plurality of first semiconductor layers and a plurality of second semiconductor layers. The plurality of first semiconductor layers and the plurality of second semiconductor layers are interleaved. A PIN diode is formed in the active region. The PIN diode includes a P-type component, an N-type component, and an undoped component disposed between the P-type component and the N-type component. A first interconnect structure is formed over a first side of the PIN diode. The first interconnect structure includes a first set of interconnect components electrically coupled to the P-type component and a second set of interconnect components electrically coupled to the N-type component. A second interconnect structure is formed over a second side of the PIN diode. The second interconnect structure includes a third set of interconnect components electrically coupled to the P-type component and a fourth set of interconnect components electrically coupled to the N-type component. The first set of interconnect components and the third set of interconnect components have a same first voltage potential. The second set of interconnect components and the fourth set of interconnect components have a same second voltage potential.

[0099] In some embodiments, the semiconductor device further includes a plurality of gate-all-around (GAA) transistors formed in or on at least a portion of the active region. In some embodiments, the semiconductor device further includes a dielectric structure over the second side in the PIN diode, wherein the third set of interconnect components and the fourth set of interconnect components extend through the dielectric structure. In some embodiments, the third set of interconnect components includes a first via coupled to the P-type component and a first metal line coupled to the first via, and the fourth set of interconnect components includes a second via coupled to the N-type component and a second metal line coupled to the second via.

[0100] Another aspect of the utility model relates to a method of forming a semiconductor device. An active region is formed including a plurality of interleaved first semiconductor layers and second semiconductor layers. A first portion of the active region is doped with a P-type dopant. A second portion of the active region is doped with an N-type dopant. The second portion of the active region is separated from the first portion of the active region by an undoped third portion of the active region. A first interconnect structure is formed over a first side of the first portion of the active region and over a first side of the second portion of the active region such that the first portion of the active region is electrically coupled to a first set of interconnect components of the first interconnect structure through the first side and the second portion of the active region is electrically coupled to a second set of interconnect components of the first interconnect structure through the first side. A second interconnect structure is formed over a second side of the first portion of the active region and over a second side of the second portion of the active region such that the first portion of the active region is electrically coupled to a third set of interconnect components of the second interconnect structure through the second side and the second portion of the active region is electrically coupled to a fourth set of interconnect components of the second interconnect structure through the second side. The first set of interconnect components is electrically coupled to the third set of interconnect components. The second set of interconnect components is electrically coupled to the fourth set of interconnect components.

[0101] In some embodiments, the method further includes biasing the first set of interconnect components and the third set of interconnect components to a same first voltage; and biasing the second set of interconnect components and the fourth set of interconnect components to a same second voltage. In some embodiments, the method further includes fabricating a ring gate (GAA) device using, at least in part, the fourth portion of the active region. In some embodiments, a dielectric structure is formed over the second side of the active region, and wherein forming the second interconnect structure includes etching a first trench and a second trench through the dielectric structure from the second side toward the first side such that the first trench exposes a portion of the first portion of the active region from the second side and the second trench exposes a portion of the second portion of the active region from the second side; and filling the first trench and the second trench with a conductive material, thereby forming a first via in the first trench and a second via in the second trench. In some embodiments, the dielectric structure includes a plurality of dielectric layers; the active region is formed on a semiconductor substrate; and the first trench and the second trench are etched to extend through the plurality of dielectric layers and at least partially through the semiconductor substrate. In some embodiments, forming the second interconnect structure further includes forming a first metal line over the second side of the first via and a second metal line over the second side of the second via; wherein: the first metal line and the first via are part of the third set of interconnect components of the second interconnect structure; the second metal line and the second via are part of the fourth set of interconnect components of the second interconnect structure; the first set of interconnect components is electrically coupled to the first side of the first metal line; and the second set of interconnect components is electrically coupled to the first side in the second metal line. In some embodiments, the first portion of the active region, the second portion of the active region, and the third portion of the active region collectively form a PIN diode; forming the second interconnect structure further includes forming a first contact pad and a second contact pad over the second side of the first metal line and the second metal line, respectively; the first contact pad is configured to receive a first voltage for a P terminal of the PIN diode; and the second contact pad is configured to receive a second voltage for an N terminal of the PIN diode.

[0102] Another aspect of the present application is directed to a device. The device includes a diode including a P-type region, an N-type region, and an undoped intrinsic region disposed between the P-type region and the N-type region. An interconnect structure is disposed over a first side of the diode. A plurality of vias is disposed over a second side of the diode, the second side being different from the first side. One or more doped regions are disposed between the diode and the vias.

[0103] Another aspect of the utility model relates to a device. The device includes an active region, which includes a plurality of interleaved first semiconductor layers and second semiconductor layers. A PIN diode is formed in the active region. The PIN diode includes a P-type component, an N-type component, and an undoped component disposed between the P-type component and the N-type component. A first conductive contact and a second conductive contact are disposed over a first side of the PIN diode. The first conductive contact and the second conductive contact are electrically connected to the P-type component and the N-type component, respectively. A dielectric structure is disposed over a second side of the PIN diode opposite the first side. One or more doped regions are disposed between the PIN diode and the dielectric structure, wherein the one or more doped regions each include P-type dopants.

[0104] Another aspect of the utility model relates to a method. A diode is formed in an active region. The diode includes a P-type component embedded in a first portion of the active region, an N-type component embedded in a second portion of the active region, and an undoped component disposed between the P-type component and the N-type component. An interconnect structure is formed over a first side of the diode. Different portions of the interconnect structure are electrically coupled to the P-type component and the N-type component, respectively. A dielectric structure is disposed over a second side opposite the first side, and one or more openings are etched through the dielectric structure. Dopant material is implanted into the active region through the one or more openings. The one or more openings are filled with a conductive material.

[0105] The foregoing summary was presented to enable a more complete appreciation of the detailed description that follows and to orient the reader. It is not intended to limit the scope of the utility model in any way. It is to be understood that the features mentioned in this summary are intended to be illustrative rather than definitive; thus, there are occasions in which features overlapping or different from those presented in this summary are acceptable under the scope of the utility model. Those skilled in the art will appreciate that they can readily use the utility model as a basis for designing or modifying other processes and structures to produce the same results as the ones introduced here. Those skilled in the art will also realize that not only the combinations stated in this summary are within the scope of the utility model, and that others are possible as well. Those skilled in the art will further recognize the interchangeable use of the terms "first", "second", and "third" with other terms or numbers, as well as the interchangeable use of the terms "top" and "bottom", and the like.

Claims

1. A semiconductor device, characterized by comprising: comprises: a diode comprising a P-type region, an N-type region, and an undoped intrinsic region disposed between the P-type region and the N-type region; a first conductive contact and a second conductive contact each disposed over a first side of the diode, wherein the first conductive contact is electrically coupled to the P-type region from the first side, and wherein the second conductive contact is electrically coupled to the N-type region from the first side; and a first via and a second via each disposed over a second side of the diode, wherein the second side is different from the first side, wherein the first via is electrically coupled to the P-type region from the second side, and wherein the second via is electrically coupled to the N-type region from the second side; wherein: the first conductive contact is electrically coupled to the first via; and the second conductive contact is electrically coupled to the second via.

2. The semiconductor device according to claim 1, wherein the undoped intrinsic region comprises a plurality of first semiconductor layers and a plurality of second semiconductor layers, the plurality of first semiconductor layers interleaved with the plurality of second semiconductor layers.

3. The semiconductor device of claim 2, wherein: the P-type region comprises P-doped portions of the plurality of first and second semiconductor layers; and the N-type region comprises N-doped portions of the plurality of first and second semiconductor layers.

4. The semiconductor device according to claim 1, wherein further comprising: a dielectric layer disposed over the second side of the diode, wherein each of the first via and the second via extends vertically through the dielectric layer.

5. The semiconductor device according to claim 1, wherein further comprising: a first set of interconnect components disposed over and electrically coupled to the first conductive contact and the second conductive contact from the first side; and a second set of interconnect components disposed over and electrically coupled to the first via and the second via from the second side, wherein the second set of interconnect components is electrically coupled to the first set of interconnect components.

6. The semiconductor device of claim 5, wherein: the first set of interconnect components comprises a plurality of vias and a plurality of first metal lines; a subset of the plurality of vias is in direct contact with the first conductive contact and the second conductive contact; the second set of interconnect components comprises a plurality of second metal lines; a first of the plurality of second metal lines is in direct contact with the first via; and a second of the plurality of second metal lines is in direct contact with the second via.

7. The semiconductor device according to claim 1, wherein the diode is formed in a first region of the device, and wherein the device further comprises a second region in which a plurality of ring gate transistors are formed.

8. A semiconductor device, characterized by comprising: comprises: an active region comprising a plurality of first semiconductor layers and a plurality of second semiconductor layers, the plurality of first semiconductor layers interleaved with the plurality of second semiconductor layers; a PIN diode formed in the active region, wherein the PIN diode includes a P-type component, an N-type component, and an undoped component between the P-type component and the N-type component; a first interconnect structure formed over a first side of the PIN diode, wherein the first interconnect structure includes a first set of interconnect components electrically coupled to the P-type component and a second set of interconnect components electrically coupled to the N-type component; a second interconnect structure formed over a second side of the PIN diode, wherein the second interconnect structure includes a third set of interconnect components electrically coupled to the P-type component and a fourth set of interconnect components electrically coupled to the N-type component; wherein: the first set of interconnect components is electrically connected to the third set of interconnect components; and the second set of interconnect components is electrically connected to the fourth set of interconnect components.

9. The semiconductor device according to claim 8, wherein Further comprising: a plurality of ring gate transistors formed in or on at least a portion of the active region.

10. The semiconductor device according to claim 8, wherein Further comprising: a dielectric structure located over the second side in the PIN diode, wherein the third set of interconnect components and the fourth set of interconnect components extend through the dielectric structure.

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