High-precision multi-channel controller and cascade controller group thereof

Abstract

The utility model relates to the technical field of automatic control, in particular to a high-precision multi-channel controller and a cascade controller group thereof, and the high-precision multi-channel controller comprises a power supply, a control board and two acquisition boards, the power supply supplies power to the control board and the acquisition board; the control board comprises a cascade port; the two acquisition boards are connected with the control board; the two acquisition boards receive information of external equipment; and the cascading port is used for cascading the two high-precision multi-channel controllers capable of being cascaded. The advantages of the utility model are that the cascaded 32-bit coding and decoding chips are used to realize the multipath AD / DA function, the problem of connection between a plurality of high-precision AD / DA chips and the control panel is solved, and the high-precision AD / DA chip circuit is high in precision, simple in structure and low in cost. In a cascade mode, a master controller is arranged through an upper computer or a jumper cap, so that the controller works in a master-slave mode.

Description

TECHNICAL FIELD

[0001] The utility model relates to automatic control technical field especially relates to a high-precision multichannel controller and its cascade controller group. BACKGROUND

[0002] In the industry of machinery, material, etc., the fatigue life of mechanical components and materials is usually tested by a testing machine system, and the main components of the testing machine system include a controller, a sensor, an actuator, a rack, a clamp and the like. The main functions of the controller include sensor data acquisition, data processing, control processing, actuator output, data uploading and the like.

[0003] In actual application, a multichannel controller is often needed to complete the coordinated control of equipment, each channel contains one or more sensor inputs, and the actuator output of the equipment is realized through a set of feedback systems. The channels are mutually constrained and work in coordination, thereby completing some complex instructions. The accurate implementation of equipment movement requires high-precision data acquisition and real-time high-precision control output. In real application, different working conditions and application environments have different requirements for the number of channels, and the number of channels is often not enough. UTILITY MODEL CONTENT

[0004] Therefore, the utility model aims at a high-precision multichannel controller and its cascade controller group, which solves the problem of insufficient number of channels by using the architecture of ARM+DSP+FPGA for the control board and connecting two acquisition boards to the control board.

[0005] To achieve the above-mentioned purpose, the technical scheme of the utility model is as follows:

[0006] A cascadeable high-precision multichannel controller includes a power supply, a control board and an acquisition board. The power supply supplies power to the control board. The control board includes a cascade port and an FPGA. The acquisition board is connected to the control board. The acquisition board receives external equipment information and control information from the FPGA. The cascade port is used to cascade two high-precision multichannel controllers.

[0007] Further, the control board further includes an ARM, a DSP and an external interface. The ARM is connected to the DSP, and the DSP is connected to the FPGA. The acquisition board is connected to the FPGA.

[0008] Further, the ARM is used for information interaction with the host computer of the external device and receiving external information; the DSP is used for data processing, receiving the instruction of the ARM, and generating corresponding information transmission to the FPGA according to the instruction; the FPGA is used for receiving the information of the acquisition board, and feeding back the received information to the DSP processor; wherein, after receiving the information feedback by the FPGA, the DSP further feeds back the information to the ARM, and simultaneously sends corresponding instruction to the FPGA; the ARM, the DSP and the FPGA are connected through continuous information interaction until the external instruction is completely executed.

[0009] Further, the ARM is connected with the DSP through the HPI interface of the DSP, and the DSP is connected with the FPGA through the EMIF interface of the DSP.

[0010] Further, the external interface includes the RS-485 interface, the network interface, the indicator light interface, the USB interface, the SD card interface, the debugging interface and the emergency stop switch interface.

[0011] Further, each acquisition board is provided with two groups of buses, and each group of buses adopts the TDM mode to cascade four codec chips.

[0012] Further, each codec chip supports one channel.

[0013] A cascade controller is realized based on the cascadeable high-precision multi-channel controller, and the cascade controller includes at least two high-precision multi-channel controllers, and the two high-precision multi-channel controllers are connected through a cascade port.

[0014] Further, the cascade controller is provided with high-precision multi-channel controllers numbered in sequence.

[0015] Compared with the prior art, the cascadeable high-precision multi-channel controller can achieve the following beneficial effects:

[0016] 1) The cascade 32-bit codec chip is used to realize the multi-channel AD / DA codec function, and the problem of connecting multiple high-precision codec chips with the control board is solved, and the precision is high, the structure is simple, and the cost is low.

[0017] 2) In the cascade mode, the high-precision multi-channel controller is set as a master controller through the host computer or the jumper cap, so that the high-precision multi-channel controller works in the master-slave mode. The synchronous pulse control makes the different high-precision multi-channel controllers work under the same control pulse. The automatic numbering can be realized, the different high-precision multi-channel controllers are easily identified by the system, and the data acquisition and control are facilitated. The synchronous control between the high-precision multi-channel controllers can realize the synchronous start and stop of multiple high-precision multi-channel controllers. BRIEF DESCRIPTION OF DRAWINGS

[0018] The accompanying drawings, which form a part of this application, are intended to provide further understanding of the application and are incorporated herein for a description of the application. The schematic embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0019] Figure 1 is a structural schematic view of a high-precision multi-channel controller according to an embodiment of the present application, which can be cascaded;

[0020] Figure 2 is a structural schematic view of a collection board according to an embodiment of the present application;

[0021] Figure 3 is a structural schematic view of a cascaded controller synchronization pulse according to an embodiment of the present application;

[0022] Figure 4 is a structural schematic view of a cascaded controller synchronization state according to an embodiment of the present application;

[0023] Figure 5 is a structural schematic view of a cascaded controller number control according to an embodiment of the present application. DETAILED DESCRIPTION

[0024] In order to make the purpose, technical scheme and advantages of the present application more clear, the present application is further described in detail below with reference to the drawings and specific embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and do not constitute a limitation on the present application.

[0025] It should be noted that the embodiments in the present application and the features in the embodiments can be combined with each other without conflict.

[0026] In the description of the present application, it should be understood that the terms "center", "longitudinal", "transverse", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only used to facilitate the description of the present application and simplify the description, and therefore cannot be understood as indicating or implying that the device or element indicated must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present application. In addition, the terms "first", "second" and the like are only used for description purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the technical features indicated. Therefore, the features limited by "first", "second" and the like can explicitly or implicitly include one or more features. In the description of the present application, unless otherwise stated, the meaning of "a plurality of" is two or more.

[0027] In the description of the utility model, it is necessary to explain, unless another explicit provision and limitation, the term "installation", "connection", "connection" should be broad sense understanding, for example, can be fixed connection, can also be detachable connection, or integrally connected;Can be mechanical connection, can also be electrical connection;Can be directly connected, can also be indirectly connected through the intermediate medium, can be the communication inside two elements.For ordinary skilled in the art, the above-mentioned terms can be understood by the specific meaning of the utility model through specific circumstances.

[0028] The utility model will be described below in detail with reference to the drawings and in combination with embodiments.

[0029] As Figure 1 The utility model discloses a high-precision multichannel controller of cascading, including power, control panel and two acquisition boards.Power supplies control panel and acquisition board.Two acquisition boards are connected with control panel, and two acquisition boards receive external equipment information, and drive external equipment according to received control panel instruction.Control panel includes ARM, DSP, FPGA, external interface, sending end drive chip, receiving end drive chip and cascade mouth, wherein, ARM is connected with DSP through the HPI (HOST PORT INTERFACE, is a parallel interface with host computer) interface of DSP, and the EMIF (External Memory Interface, external memory interface) interface is connected between DSP and FPGA.Two acquisition boards are connected with FPGA through the pin row female, and the cascade mouth is used to cascade two high-precision multichannel controllers of cascading (hereinafter referred to as controller) in the embodiment, and the cascade mouth is in the form of coaxial terminal and realizes the cascade between two high-precision multichannel controllers of cascading.

[0030] ARM, full name is Advanced RISC Machine, is a reduced instruction set computer (RISC) architecture, and it is widely used in embedded system, mobile device, personal computer, network equipment and server etc.

[0031] DSP, full name is Digital Signal Processor (digital signal processor), is a kind of microprocessor specially used for digital signal processing (Digital Signal Processing, DSP).DSP has powerful digital signal processing capability, can efficiently execute various complex algorithms, such as filtering, transformation, detection, evaluation, compression, identification etc.

[0032] FPGA, full name Field-Programmable Gate Array, is a kind of semi-custom circuit, which combines the flexibility of programmable logic device (PLD) and the high performance of application specific integrated circuit (ASIC).

[0033] Multi-channel control refers to the same controller can control multiple moving parts at the same time, through multi-channel control to realize precise control of multiple parts.

[0034] The external interface includes RS-485 interface, gigabit network interface, indicator interface, USB interface, SD card interface, debugging interface and emergency stop switch interface.

[0035] RS-485 interface is a combination of balanced driver and differential receiver, which enhances the ability to resist common mode interference, that is, good noise immunity. RS-485 interface is a widely used half-duplex serial communication interface, which is mainly used for multi-device communication in industrial automation and control system.

[0036] SD card, full name Secure Digital Memory Card, is a new generation of memory device based on semiconductor flash memory.

[0037] In this embodiment, ARM is connected with external hand control box and temperature controller through two RS-485 interfaces respectively, receives the information of hand control box and temperature controller, and interacts with the host computer of external device through gigabit network interface. DSP is responsible for data processing and receives the instructions of ARM, generates corresponding information according to the instructions and transmits the information to FPGA. FPGA receives the sensor information of external device collected by two acquisition boards, and feeds back the received sensor information to DSP. After receiving the sensor information fed back by FPGA, DSP feeds back the sensor information fed back by FPGA to ARM. At the same time, DSP runs PID (proportion integration differentiation) control algorithm according to the collected sensor information of external device, generates corresponding instructions for FPGA, FPGA generates analog signal through acquisition board and drives external device, or FPGA outputs digital signal to acquisition board and drives external device, so as to control external device to complete corresponding action. ARM, DSP and FPGA interact with each other constantly until the external instruction is completely executed.

[0038] Each acquisition board features two busses. Each bus uses TDM (time-division multiplexing) to cascade four codec chips. Each codec chip features 32-bit AD / DA encoding and decoding, significantly improving analog input and output accuracy. Each codec chip supports one channel, two analog inputs, and two analog outputs. Each acquisition board supports 16 analog inputs, 16 analog outputs, 16 digital inputs and outputs, and 8 digital sensor inputs.

[0039] TDM is a technology that transmits multiple digitized data, voice, and video signals simultaneously over the same communications medium by interleaving bit pulses in different channels or time slots. It allows multiple signals to be transmitted over different time periods, with each signal occupying a fixed time slot, thus enabling the multiplexing of multiple signals on the same physical channel.

[0040] Bus: A public communication trunk line that transmits information between various functional components of a computer. It is a transmission line composed of wires. According to the type of information transmitted by the computer, the computer bus can be divided into a data bus, an address bus, and a control bus, which are used to transmit data, address, and control signals respectively. Common bus types include CPCI (CompactPCI, a peripheral component interconnect standard), PCIe (full name PCI Express (Peripheral Component Interconnect Express), a high-speed serial computer expansion bus standard), I 2 C (Inter-Integrated Circuit, a serial communication protocol), SPI (Serial Peripheral Interface, serial peripheral interface), XINTF (External Interface, external interface), EMIFA (External Memory Interface A, external memory interface A), etc.

[0041] In this embodiment, the acquisition board is used to collect sensor signals from external devices. The sensor signals are signal conditioned and connected to the analog input terminal of the acquisition board. The analog quantities are converted into digital quantities by the codec chip for use by the control board. At the same time, the codec chip receives instructions from the control board and outputs signal conditioned to drive external devices.

[0042] like Figure 2 As shown, the acquisition board includes a driver chip, an encoder chip, a signal conditioning circuit, an operational amplifier and an interface circuit, as well as a connector connected to the control board.

[0043] The signal conditioning circuit can provide a bias voltage for the sensor analog input, and convert the input of the sensor into a differential signal required by the codec chip. After being converted into a digital signal by the codec chip, the signal is transmitted to the DSP by the FPGA, and then transmitted to the ARM by the DSP, which is used for control operation and data display, etc. At the same time, the FPGA receives the control signal from the DSP, converts the digital quantity into an analog quantity through the codec chip, and then converts it into the level required by the external device through the operational amplifier and the interface circuit, so as to drive the external device to act. The driving chip of the acquisition board is connected with the FPGA through the connector, which is used to enhance the driving ability, drive the digital IO signal to control the external device, or connect the acquisition board and the external device with the digital sensor and collect the digital sensor information according to the instruction.

[0044] A cascade controller is realized based on the above-mentioned cascadeable high-precision multi-channel controller, and the cascade controller comprises a plurality of cascadeable high-precision multi-channel controllers (hereinafter referred to as controllers), and adjacent two controllers are connected with the cascade ports of the controllers through coaxial cables to realize the cascade of the plurality of controllers.

[0045] Further, the plurality of controllers are synchronous pulse controlled and synchronous state controlled.

[0046] One of the controllers is set as a master controller (generally, the first controller in the cascade is set as the master controller), and the rest are defined as slave controllers.

[0047] Synchronous pulse control: when the synchronization operation is needed between different controllers, the master controller can send a synchronous pulse, the synchronous pulse is output through the coaxial terminal, and is connected to the input end of the first slave controller. The first slave controller sends the received synchronous pulse to the input end of the next slave controller through its output end until the last slave controller receives the synchronous pulse and inputs it to the input end of the master controller, thereby forming a complete loop control.

[0048] As shown in Figure 3 , the sending end driving chip of the control board converts the 3.3V synchronous pulse of the DSP into a 5V synchronous pulse and outputs it through the coaxial cable. The receiving end driving chip of the control board converts the received 5V synchronous pulse into a 3.3V synchronous pulse. The selection switch of the control board selects whether the synchronous pulse comes from the DSP or the receiving end driving chip through the jumper cap or the setting of the upper computer.

[0049] When the controller is in the cascade state, the main controller sends out a synchronization pulse through the jumper cap or the host computer, and the synchronization pulse is sent out by the DSP of the main controller. After the slave controller detects the synchronization pulse, the system is synchronized. At the same time, the synchronization pulse is input to the sending end drive chip through the selection switch, and then output to the next slave controller through the coaxial terminal of the control panel. If the coaxial terminal of the control panel of the main controller can receive the synchronization pulse sent out by the main controller previously, it indicates that synchronization is achieved.

[0050] Synchronization state control: when one of the cascade controllers fails, the fault information is transmitted to other controllers in time to ensure that other controllers can stop executing actions synchronously. At the same time, the fault information is fed back to the host computer to facilitate finding the fault cause.

[0051] As shown in Figure 4 , in the synchronization state control, the sending end drive chip of the control panel converts the synchronization state signal of the DSP from 3.3V level to 5V and outputs it through the coaxial cable. The receiving end drive chip of the control panel converts the received 5V synchronization state signal to 3.3V, and the DSP receives and detects the state.

[0052] The specific working process is as follows:

[0053] The SO end of the first controller is connected to the SI end of the second controller, and the same applies to the subsequent controllers. The SO end of the last controller is connected to the SI end of the first controller. The first controller is set as the main controller through the host computer control or the jumper cap setting.

[0054] When the controller has no fault, the SO end and the SI end are both low. When any controller fails, if the SI end receives a low level, the SO end level is set to high. Because it is cascaded, after the SO end outputs a high level, the high level signal is returned to the input end of the controller, i.e. the SI end becomes high, which proves that the controllers in the cascade have received the notification.

[0055] When the cascade controller is working, if a high level is received at the SI end, it indicates that a device has failed, and the controller will set the SO end level to high and stop the action. If a fault occurs, the operator can repair the controller reporting the error according to the state information of the host computer.

[0056] Further, each cascadeable high-precision multi-channel controller is sequentially numbered.

[0057] When multiple controllers are cascaded, each controller needs to have its own ID number for easy data display and control. After power-on, the control system of the external device will automatically perform ID numbering according to the cascade order.

[0058] AsFigure 5 As shown, the sending end drive chip of the control board converts the ID instruction signal of the DSP from 3.3V level to 5V and outputs through the coaxial cable. The receiving end drive chip of the control board converts the received 5V ID instruction signal to 3.3V, which is received and detected by the DSP.

[0059] The working process is as follows:

[0060] The first controller is set as the master controller, the IDO end of the first controller is connected to the IDI end of the second controller, and the like. The IDO end of the last controller is connected to the IDI end of the first controller. The ID of each controller is automatically determined, starting from the master controller and ending at the terminal slave controller, and numbered in sequence, i.e. the IDs are 1, 2, 3, and the like in sequence, which follows the position or logical sequence of the controller in the cascaded controller.

[0061] The node ID determination process is as follows: in the idle state, the IDO end of each controller is high. When the control system of the external device starts the ID identification process, each controller receives the ID identification instruction, first checks the state of the IDI end, if the IDI end is high, the controller enters a waiting state and monitors the buffer information of the control board at the same time, records the ID number that has been received. When it is detected that the IDI end is low, it indicates that the ID of the previous controller has been determined, and a low-level signal is sent through the IDO port. At this time, the controller reads the latest recorded ID number and adds 1 to it as its own ID number, and sends a low-level signal through the IDO end to notify the next controller to determine its ID. After sending the ID number, the controller will delay for a period of time, and then clear the IDO end. Therefore, the determination of the node ID actually uses the communication lines IDI and IDO of the adjacent nodes.

[0062] The ID identification instruction is hexadecimal AX, and each node receives AX. If IDI=0, X+1 is saved as its own ID, and AX+1 is issued as a response, and after the sending is completed, IDO is cleared for 20us as the ID identification instruction of the next node. Once each node determines its own ID, it will not be determined again before being powered on again.

[0063] The master controller can understand how many slave controllers are cascaded by receiving the ID identification instruction.

[0064] The above specific embodiments do not constitute a limitation on the protection scope of the present application. Those skilled in the art should understand that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principles of the present application should be included in the protection scope of the present application.

Claims

1. A high-precision multi-channel controller, characterized by, The high-precision multi-channel controller comprises a power supply, a control board and a collection board; the power supply supplies power to the control board; the control board comprises a cascade port and an FPGA; the collection board is connected with the control board; the collection board receives external device information and control information from the FPGA; and the cascade port is used for cascading two high-precision multi-channel controllers.

2. The high precision multi-channel controller of claim 1, wherein, The control board further comprises an ARM, a DSP and an external interface; the ARM is connected with the DSP, and the DSP is connected with the FPGA; and the collection board is connected with the FPGA.

3. The high-precision multi-channel controller according to claim 2, wherein, the ARM is used for information interaction with a host computer of an external device and receiving external information; the DSP is used for data processing, receiving instructions of the ARM and generating corresponding information according to the instructions and transmitting the information to the FPGA; the FPGA is used for receiving information of the collection board and feeding back the received information to the DSP processor; the DSP further feeds back the information to the ARM after receiving the information fed back by the FPGA, and simultaneously sends corresponding instructions to the FPGA; the ARM, the DSP and the FPGA are connected through continuous information interaction until the instructions of the external device are completely executed.

4. The high precision multi-channel controller of claim 2, wherein, The ARM and the DSP are connected through an HPI interface of the DSP, and the DSP and the FPGA are connected through an EMIF interface of the DSP.

5. The high precision multi-channel controller of claim 1, wherein, The external interface comprises an RS-485 interface, a network interface, an indicator light interface, a USB interface, an SD card interface, a debugging interface and an emergency stop switch interface.

6. The high precision multi-channel controller of claim 1, wherein, Each collection board is provided with two groups of buses, and each group of buses adopts a TDM mode to cascade four codec chips.

7. The high precision multi-channel controller of claim 6, wherein, Each codec chip supports one channel.

8. A cascade controller set, characterized by The cascade controller group comprises at least two high-precision multi-channel controllers according to any one of claims 1-7, and adjacent two high-precision multi-channel controllers are connected through the cascade port.

9. The cascade controller bank of claim 8, wherein, The cascade controller group is provided with the high-precision multi-channel controllers numbered in sequence.

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