Shift register, gate drive circuit and display panel

Abstract

The utility model provides a shift register. The shift register has an input stage, an output stage and a reset stage. The shift register includes: an input sub-circuit configured to transmit an input signal to a first node in response to a first clock signal in an input phase; the output sub-circuit is configured to output a second clock signal through the signal output end in response to the potential of the first node in an output stage; in a working period, the starting moment of the effective level of the second clock signal is not earlier than the ending moment of the effective level of the first clock signal; the first control sub-circuit is configured to respond to an input signal and a third clock signal in an input stage and a reset stage, and control the potential of a second node through the third clock signal; and the holding sub-circuit is configured to output the first invalid working level signal through the signal output end in response to the potential of the second node in a reset stage.

Description

TECHNICAL FIELD

[0001] The present disclosure belongs to the technical field of display, and particularly relates to a shift register, a gate driving circuit and a display panel. BACKGROUND

[0002] At present, AMOLED (Active-matrix organic light-emitting diode) flexible screen technology is increasingly mature, and its characteristics of being bendable, light in weight, high in contrast ratio and low in power consumption make it become the next generation display mode to replace liquid crystal display (LCD). The AMOLED is provided with a gate driving circuit for providing a gate driving signal for a pixel unit. The gate driving circuit includes a plurality of cascaded shift registers, each of which is configured to provide a gate driving signal for one or more rows of pixel units. SUMMARY

[0003] The present disclosure aims to at least solve one of the technical problems existing in the prior art, and provides a shift register, including an input sub-circuit, an output sub-circuit, a first control sub-circuit and a holding sub-circuit; wherein,

[0004] The input sub-circuit is configured to transmit an input signal to a first node in response to a first clock signal; the first node is a connection node of the input sub-circuit and the output sub-circuit;

[0005] The output sub-circuit is configured to output a second clock signal through a signal output end in response to a potential of the first node; the first control sub-circuit is configured to control a potential of a second node through a third clock signal in response to the input signal and the third clock signal; the second node is a connection node of the first control sub-circuit and the holding sub-circuit;

[0006] The holding sub-circuit is configured to output a first invalid working level signal through the signal output end in response to the potential of the second node.

[0007] In some embodiments, the first control sub-circuit includes a second transistor, a third transistor and a first capacitor;

[0008] The control electrode of the second transistor is connected to a signal input end, the first electrode is connected to the control electrode of the third transistor, and the second electrode is connected to a second invalid working level signal end; the second invalid working level signal is greater than or equal to the first invalid working level signal;

[0009] The control electrode of the third transistor is connected with the first electrode of the second transistor and the first electrode of the first capacitor, the first electrode of the first capacitor is connected with the second electrode of the first capacitor and a third clock signal terminal, and the second electrode is connected with the second node.

[0010] In some embodiments, the shift register further comprises a first pull-up sub-circuit;

[0011] The first pull-up sub-circuit is configured to pull up the first node by a second invalid working level signal in response to the third clock signal and the potential of the second node; and the second invalid working level signal is greater than or equal to the first invalid working level signal.

[0012] In some embodiments, the first pull-up sub-circuit comprises a sixth transistor and a seventh transistor;

[0013] The control electrode of the sixth transistor is connected with the second node, the first electrode is connected with a second invalid working level signal terminal, and the second electrode is connected with the first electrode of the seventh transistor; and the control electrode of the seventh transistor is connected with a third clock signal terminal, and the second electrode is connected with the first node.

[0014] In some embodiments, the shift register further comprises a second pull-up sub-circuit;

[0015] The second pull-up sub-circuit is configured to pull up the second node by a second invalid working level signal in response to the potential of the first node; and the second invalid working level signal is greater than or equal to the first invalid working level signal.

[0016] In some embodiments, the second pull-up sub-circuit comprises a ninth transistor;

[0017] The control electrode of the ninth transistor is connected with the first node, the first electrode is connected with the second node, and the second electrode is connected with a second invalid working level signal terminal.

[0018] In some embodiments, the shift register further comprises a protection sub-circuit;

[0019] The protection sub-circuit is configured to transmit a second invalid working level signal to the first node in response to a protection level signal; and the second invalid working level signal is greater than or equal to the first invalid working level signal.

[0020] In some embodiments, the protection sub-circuit comprises a tenth transistor;

[0021] The control electrode of the tenth transistor is connected with a protection level signal terminal, the first electrode is connected with the first node, and the second electrode is connected with a second invalid working level signal terminal.

[0022] In some embodiments, the shift register further comprises a voltage stabilizing sub-circuit;

[0023] The voltage stabilizing sub-circuit is connected between the input sub-circuit and the output sub-circuit; a connection node of the voltage stabilizing sub-circuit and the input sub-circuit is a first sub-node, and a connection node of the voltage stabilizing sub-circuit and the output sub-circuit is a second sub-node;

[0024] The voltage stabilizing sub-circuit is configured to transmit the voltage of the first sub-node to the second sub-node in response to a working level signal.

[0025] In some embodiments, the voltage stabilizing sub-circuit comprises an eighth transistor;

[0026] The control electrode of the eighth transistor is connected to a working level signal end, the first electrode is connected to the first sub-node, and the second electrode is connected to the second sub-node.

[0027] In some embodiments, the input sub-circuit comprises a first transistor;

[0028] The control electrode of the first transistor is connected to a first level signal end, the first electrode is connected to a signal input end, and the second electrode is connected to the first node.

[0029] In some embodiments, the output sub-circuit comprises a fifth transistor and a second capacitor;

[0030] The control electrode of the fifth transistor is connected to the first node, the first electrode is connected to the signal output end, and the second electrode is connected to a second clock signal end; the first electrode of the second capacitor is connected to the control electrode of the fifth transistor, and the second electrode is connected to the first electrode of the fifth transistor.

[0031] In some embodiments, the holding sub-circuit comprises a fourth transistor and a third capacitor;

[0032] The control electrode of the fourth transistor is connected to the second node, the first electrode is connected to a first invalid working level signal end, and the second electrode is connected to the signal output end; the first electrode of the third capacitor is connected to the control electrode of the fourth transistor, and the second electrode is connected to the first electrode of the fourth transistor.

[0033] The present disclosure also provides a driving method for driving a shift register, wherein the driving method comprises:

[0034] In the input stage, the shift register is provided with a first clock signal, an input signal and a third clock signal, the input signal is transmitted to the first node through the input sub-circuit, and the third clock signal controls the potential of the second node to be an invalid level; the first node is a connection node of the input sub-circuit and the output sub-circuit, and the second node is a connection node of the first control sub-circuit and the holding sub-circuit;

[0035] In the output stage, the shift register is provided with a second clock signal, and the second clock signal is transmitted to the signal output end through the output sub-circuit and output;

[0036] In the reset stage, the shift register is provided with a third clock signal and a first invalid working level signal, the third clock signal controls the potential of the second node to be a valid level, and the first invalid working level signal is transmitted to the signal output end through the holding sub-circuit and output.

[0037] In some embodiments, in one working period, the starting time of the valid level of the second clock signal is not earlier than the termination time of the valid level of the first clock signal.

[0038] The present disclosure also provides a gate drive circuit comprising a plurality of cascaded shift registers;

[0039] For the gate drive circuit, the i-th shift register is connected to the same clock signal line as the i+4-th shift register; i is a positive integer.

[0040] In some embodiments, the gate drive circuit is connected to four clock signal lines, which are a first clock signal line, a second clock signal line, a third clock signal line and a fourth clock signal line; the starting times of the valid levels of the four clock signals on the four clock signal lines are sequentially different by 1H, and H is a unit scanning time.

[0041] The shift register is configured with a first clock signal end, a second clock signal end and a third clock signal end for receiving the first clock signal, the second clock signal and the third clock signal respectively; the first clock signal end, the second clock signal end and the third clock signal end of the shift register are connected to three different clock signal lines respectively;

[0042] Each group of four cascaded shift registers comprises a group of shift registers, wherein the first clock signal end of the first-stage shift register is connected to the first clock signal line, the second clock signal end is connected to the second clock signal line, and the third clock signal end is connected to the third clock signal line; the first clock signal end of the second-stage shift register is connected to the second clock signal line, the second clock signal end is connected to the third clock signal line, and the third clock signal end is connected to the fourth clock signal line; the first clock signal end of the third-stage shift register is connected to the third clock signal line, the second clock signal end is connected to the fourth clock signal line, and the third clock signal end is connected to the first clock signal line; the first clock signal end of the fourth-stage shift register is connected to the fourth clock signal line, the second clock signal end is connected to the first clock signal line, and the third clock signal end is connected to the second clock signal line.

[0043] The present disclosure also provides a display panel, which is divided into a display area and a peripheral area surrounding the display area; a plurality of pixel units arranged in an array are provided in the display area, and the above-mentioned gate drive circuit is provided in the peripheral area; each of the shift registers in the gate drive circuit is configured to provide a gate drive signal for a row of the pixel units. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] Figure 1a It is a structural block diagram of an existing shift register;

[0045] Figure 1b for Figure 1a Circuit diagram of the shift register;

[0046] Figure 1c for Figure 1b Working timing diagram of the shift register in FIG.

[0047] Figure 2a A structural block diagram of a shift register provided in an embodiment of the present disclosure;

[0048] Figure 2b for Figure 2a Circuit diagram of the shift register;

[0049] Figure 3a A structural block diagram of a shift register provided in an embodiment of the present disclosure;

[0050] Figure 3b for Figure 3a Circuit diagram of the shift register;

[0051] Figure 4a A structural block diagram of a shift register provided in an embodiment of the present disclosure;

[0052] Figure 4b For Figure 4a Circuit schematic diagram of the shift register;

[0053] Figure 5a Structural block diagram of the shift register provided by the embodiment of the present disclosure;

[0054] Figure 5b For Figure 5a Circuit schematic diagram of the shift register;

[0055] Figure 6a Structural block diagram of the shift register provided by the embodiment of the present disclosure;

[0056] Figure 6b For Figure 6a Circuit schematic diagram of the shift register;

[0057] Figure 7a Structural block diagram of the shift register provided by the embodiment of the present disclosure;

[0058] Figure 7b For Figure 7a Circuit schematic diagram of the shift register;

[0059] Figure 8 For Figure 7b Working timing diagram of the shift register;

[0060] Figure 9 Circuit cascade diagram of the gate drive circuit provided by the embodiment of the present disclosure;

[0061] Figure 10 For Figure 9 Working timing diagram of the gate drive circuit;

[0062] Figure 11 Structural schematic diagram of the display panel provided by the embodiment of the present disclosure. DETAILED DESCRIPTION

[0063] In order to enable those skilled in the art to better understand the technical solutions of the present application, the present application will be further described in detail below in combination with the drawings and specific embodiments.

[0064] Unless otherwise defined, the technical or scientific terms used in this application should have the ordinary meaning understood by a person of ordinary skill in the technical field to which this application belongs. The words "one", "a", "the" and the like used in this application do not indicate a limit on quantity and may indicate the singular or plural. The terms "include", "comprise", "have" and any variations thereof used in this application are intended to cover non-exclusive inclusions; for example, a process, method, system, product or device that includes a series of steps or modules (units) is not limited to the listed steps or units, but may also include steps or units that are not listed, or may also include other steps or units that are inherent to these processes, methods, products or devices. The words "connect", "connected", "coupled" and the like used in this application are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The word "multiple" used in this application refers to two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships can exist. For example, "A and / or B" can mean: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates an "or" relationship between the preceding and following objects. The terms "first," "second," and "third" used in this application merely distinguish similar objects and do not represent a specific ordering of the objects. Terms such as "upper," "lower," "left," and "right" are used only to indicate relative positional relationships. If the absolute position of the described objects changes, the relative positional relationship may also change accordingly.

[0065] As used herein, "parallel" and "perpendicular" include the conditions described and conditions similar to the conditions described, and the range of the similar conditions is within an acceptable deviation range, wherein the acceptable deviation range is determined by a person of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the specific quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, wherein the acceptable deviation range for approximate parallelism can be, for example, a deviation within 5°; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, wherein the acceptable deviation range for approximate perpendicularity can also be, for example, a deviation within 5°.

[0066] The transistors used in the embodiments of the present disclosure may be thin film transistors, field effect transistors, or other devices with the same characteristics. Since the source and drain of the transistors used are symmetrical, there is no difference between the source and drain. In the embodiments of the present disclosure, in order to distinguish the source and drain of the transistor, one of the electrodes is referred to as the first electrode, the other electrode is referred to as the second electrode, and the gate is referred to as the control electrode. In addition, the transistors in the embodiments of the present disclosure all use P-type transistors, the control electrode is the gate of the P-type transistor, the first electrode is the source of the P-type transistor, and the second electrode is the drain of the P-type transistor. When a low-level signal is input to the gate, the P-type transistor is turned on. Therefore, for the P-type transistor, the working level signal and the valid level signal are both low-level signals, and the invalid working level signal and the invalid level signal are both high-level signals. Here, the difference between the invalid working level signal and the invalid level signal is that the invalid working level signal refers to a high-level signal with a constant level, such as VGH1, VGH2, etc. The invalid level signal refers to a high level in a signal whose level is changing, for example, the high level in the CLK signal is an invalid level signal, and the low level is a valid level signal. The invalid working level signal and the invalid level signal may be equal in magnitude or unequal in magnitude. Of course, the transistors of the present disclosure may all be N-type transistors. In this case, the working level signal and the valid level signal are both high-level signals, and the invalid working level signal and the invalid level signal are both low-level signals. The present disclosure is not limited to this. The shift register of the present disclosure will be described below using only P-type transistors as an example.

[0067] Figure 1a This is a circuit diagram of an existing shift register. Figure 1a The shift register includes an input subcircuit 01, an output subcircuit 02, a first control subcircuit 03, and a holding subcircuit 04. The connection node between the input subcircuit 01, the output subcircuit 02, and the first control subcircuit 03 is a first node P1, and the connection node between the first control subcircuit 03 and the holding subcircuit 04 is a second node P2.

[0068] Specifically, refer to Figure 1bThe input sub-circuit 01 comprises a first transistor T1, the gate of which is connected to the first clock signal terminal CK, the source of which is connected to the input signal terminal STV, and the drain of which is connected to the first node P1. When the first clock signal is at a low level, the first transistor T1 is turned on, and the input signal is transmitted to the first node P1 through the first transistor. The output sub-circuit 02 comprises a second transistor T2 and a capacitor C1, the gate of the second transistor T2 is connected to the first node P1, the source of the second transistor T2 serves as the signal output terminal OUT, and the drain of the second transistor T2 is connected to the second clock signal terminal CB. The two poles of the first capacitor C1 are connected to the gate and the source of the second transistor T2, respectively. When the potential of the first node P1 is at a low level signal, the second transistor T2 is turned on, and the second clock signal is transmitted to the signal output terminal OUT through the second transistor T2 and outputted. The first capacitor C1 can serve as an energy storage element, and the potential of the first node P1 is controlled through the coupling effect of the capacitor. The first control sub-circuit 03 comprises a third transistor T3, a fourth transistor T4, a fifth transistor T5 and a second capacitor C2. The gates of the third transistor T3 and the fourth transistor T4 are both connected to the first node P1, and the drains of the third transistor T3 and the fourth transistor T4 are both connected to the invalid working level signal terminal VGH. The source of the third transistor T3 is connected to the gate of the fifth transistor T5, and the source of the fourth transistor T4 is connected to the second node P2. The source of the fifth transistor T5 is connected to the second clock signal terminal CB, and the drain of the fifth transistor T5 is connected to the second node P2. The two poles of the second capacitor C2 are connected to the gate and the source of the fifth transistor T5, respectively. When the potential of the first node P1 is at a low level signal, the third transistor T3 and the fourth transistor T4 are both turned on, the invalid working level signal is transmitted to the fifth transistor T5 through the third transistor T3 to turn off the fifth transistor T5, and the second node P2 is pulled up through the fourth transistor T4. When the potential of the first node P1 is at a high level signal, the third transistor T3 and the fourth transistor T4 are both turned off. At this time, if the second clock signal is at a low level signal, the low level signal can turn on the fifth transistor T5, and the fifth transistor T5 transmits the low level signal to the second node P2. The holding sub-circuit 04 comprises a sixth transistor T6 and a third capacitor C3, the gate of the sixth transistor T6 is connected to the second node P2, the source of the sixth transistor T6 is connected to the invalid working level signal terminal VGH, and the drain of the sixth transistor T6 is connected to the source of the second transistor T2 and serves as the signal output terminal OUT. The third capacitor C3 can serve as an energy storage element, and the potential of the second node P2 is controlled through the coupling effect of the capacitor. When the potential of the second node P2 is at a low level signal, the sixth transistor T6 is turned on, and the invalid working level signal is outputted to the signal output terminal OUT through the sixth transistor T6.

[0069] It should be noted that the first clock signal and the second clock signal in the above circuit are inverse signals. Figure 1c The working timing diagram of the above shift register is shown in Figure 1c The above shift register can comprise the following four working stages.

[0070] In the first stage S1, the input signal terminal STV writes a low level signal, the first clock signal terminal CK writes a low level signal, and the second clock signal terminal CB writes a high level signal. The first transistor T1 is turned on, the input signal is transmitted to the first node P1 through the first transistor T1, the potential of the first node P1 is pulled low, the second transistor T2, the third transistor T3 and the fourth transistor T4 are all turned on, the invalid working level signal VGH is transmitted to the fifth transistor T5 through the third transistor T3 to turn off the fifth transistor T5, and the potential of the second node P2 is pulled high through the fourth transistor T4. The high level signal written by the second clock signal terminal CB is transmitted to the signal output terminal OUT through the second transistor T2 and outputted.

[0071] In the second stage S2, the input signal terminal STV writes a high level signal, the first clock signal terminal CK writes a high level signal, and the second clock signal terminal CB writes a low level signal. The first transistor T1 is turned off, the first node P1 continues to maintain a low level signal due to the coupling effect of the first capacitor C1, the second transistor T2, the third transistor T3 and the fourth transistor T4 maintain the open state, and the low level signal written by the second clock signal terminal CB is transmitted to the signal output terminal OUT through the second transistor T2 and outputted.

[0072] In the third stage, the input signal terminal STV writes a high level signal, the first clock signal terminal CK writes a low level signal, and the second clock signal terminal CB writes a high level signal. The first transistor T1 is turned on, the high level signal written by the input signal terminal STV is transmitted to the first node P1 through the first transistor T1, the potential of the first node P1 is pulled high, and the second transistor T2, the third transistor T3 and the fourth transistor T4 are all turned off. The fifth transistor T5 is turned on by the low level signal written by the first clock signal terminal CK, the low level signal is transmitted to the second node P2 through the fifth transistor T5, the potential of the second node P2 is pulled low, and the sixth transistor T6 is turned on. The high level signal written by the invalid working level signal terminal VGH is transmitted to the signal output terminal OUT through the sixth transistor T6 and outputted.

[0073] In the fourth stage, the input signal terminal STV writes a high level signal, the first clock signal terminal CK writes a high level signal, and the second clock signal terminal CB writes a low level signal. The first transistor T1 maintains the off state, the potential of the first node P1 continues to maintain a high level due to the coupling effect of the first capacitor C1, the second transistor T2, the third transistor T3 and the fourth transistor T4 are all turned off. The high level signal written by the first clock signal terminal CK turns off the third transistor T3. The potential of the second node P2 continues to maintain a low level signal due to the coupling effect of the third capacitor C3, the sixth transistor T6 continues to maintain the open state, and the high level signal written by the invalid working level signal terminal VGH is transmitted to the signal output terminal OUT through the sixth transistor T6 and outputted.

[0074] In the third stage S3 and the fourth stage S4, the potential of the first node P1 is a high level signal. Since the width-length ratio of the second transistor T2 is large, the gate-drain capacitance Cgs and the Miller capacitance Cgd of the second transistor T2 are large. When the signal written at the second clock signal end CB changes from a high level to a low level, the low level signal will be coupled to pull down the first node P1, thereby causing the third transistor T3 and the fourth transistor T4 to be partially turned on, further interfering with the potential of the second node P2, and affecting the output.

[0075] Based on the above problems, the present disclosure provides a shift register, Figure 2a is a structural schematic diagram of the shift register, Figure 8 is a working timing diagram of the shift register. Referring to Figure 2a and Figure 8 , the shift register has three working stages, namely an input stage T1, an output stage T2 and a reset stage T3. Specifically, referring to Figure 2a , the shift register comprises an input sub-circuit 1, an output sub-circuit 2, a first control sub-circuit 3 and a holding sub-circuit 4, the connection node of the input sub-circuit 1 and the output sub-circuit 2 is a first node N1, and the connection node of the first control sub-circuit 3 and the holding sub-circuit 4 is a second node N2. Among them, the input sub-circuit 1 is configured to, in the input stage T1, transmit an input signal to the first node N1 in response to a first clock signal. The output sub-circuit 2 is configured to, in the output stage T2, output a second clock signal through a signal output end OUT in response to the potential of the first node N1. The first control sub-circuit 3 is configured to, in the input stage T1 and the reset stage T3, respond to the input signal and a third clock signal, and control the potential of the second node N2 through the third clock signal. The holding sub-circuit 4 is configured to, in the reset stage T3, output a first invalid working level signal through the signal output end OUT in response to the potential of the second node N2. It should be noted that, in a working cycle of the shift register (i.e. in the input, output and reset stages), the starting time of the effective level of the second clock signal is not earlier than the termination time of the effective level of the first clock signal, that is, the effective level duration of the second clock signal and the first clock signal has no overlap. In this way, when the second clock signal is a low level signal to pull down the potential of the first node N1, since the first clock signal is a high level at this time, the first transistor T1 will not be turned on, and the pulled-down potential of the first node N1 will not affect the potential of the second node N2. Therefore, the shift register of the present disclosure has high reliability, and when it is applied to an AMOLED display panel, the product yield can be effectively improved.

[0076] Figure 2b is a specific circuit diagram of the shift register in Figure 2a . Referring to Figure 2bThe input sub-circuit 1 comprises a first transistor T1, wherein a gate of the first transistor T1 is connected with the first clock signal terminal CK1, a source of the first transistor T1 is connected with the input signal terminal INPUT, and a drain of the first transistor T1 is connected with the first node N1. For example, the input signal written in the input signal terminal INPUT can be an STV signal. The output sub-circuit 2 comprises a fifth transistor T5 and a second capacitor C2, wherein a gate of the fifth transistor T5 is connected with the first node N1, a source of the fifth transistor T5 is connected with the signal output terminal OUT, and a drain of the fifth transistor T5 is connected with the second clock signal terminal CB. Two poles of the second capacitor C2 are connected with the gate and the source of the fifth transistor T5 respectively. The first control sub-circuit 3 comprises a second transistor T2, a third transistor T3 and the second capacitor C2, wherein a gate of the second transistor T2 is connected with the input signal terminal INPUT, a source of the second transistor T2 is connected with a gate of the third transistor T3, a drain of the second transistor T2 is connected with the second invalid working level signal terminal VGH2, a source of the third transistor T3 is connected with the third clock signal terminal CK3, a drain of the third transistor T3 is connected with the second node N2, and two poles of the first capacitor C1 are connected with the gate and the source of the third transistor T3 respectively. The holding sub-circuit 4 comprises a fourth transistor T4 and a third capacitor C3, wherein a gate of the fourth transistor T4 is connected with the second node N2, a source of the fourth transistor T4 is connected with the first invalid working level signal terminal VGH1, and a drain of the fourth transistor T4 is connected with the signal output terminal OUT. Two poles of the third capacitor C3 are connected with the gate and the source of the fourth transistor T4 respectively. The first invalid working level signal is less than or equal to the second invalid working level signal.

[0077] With reference to the foregoing description, the input sub-circuit 1, the output sub-circuit 2, the first control sub-circuit 3 and the holding sub-circuit 4 are connected in series to form a signal output circuit. Figure 2b In the input stage T1, the first transistor T1 is opened by the first clock signal, the input signal is transmitted to the first node N1 through the first transistor T1, and the potential of the first node N1 is pulled low. Then, in the output stage T2, the fifth transistor T5 is opened by the low potential of the first node N1, and the second clock signal is transmitted to the signal output terminal OUT through the fifth transistor T5 and outputted. In the input stage T1, the second transistor T2 is opened by the input signal, the second invalid working level signal is transmitted to the gate of the third transistor T3 through the second transistor T2, and the third transistor T3 is turned off. In the reset stage T3, the second transistor T2 is closed by the input signal, at this time, the third transistor T3 is opened by the third clock signal, the third clock signal is transmitted to the second node N2 through the third transistor T3, and the potential of the second node N2 is pulled low. Then, in the reset stage T3, the fourth transistor T4 is opened by the low potential of the second node N2, and the first invalid working level signal is outputted through the fourth transistor T4.

[0078] In some examples, with reference to the foregoing description, Figure 3aThe shift register of the present disclosure further comprises a first pull-up sub-circuit 5 configured to pull up the first node N1 by the second invalid working level signal in the reset phase T3 in response to the third clock signal and the potential of the second node N2. It should be noted that in one working cycle, the starting time of the active level of the third clock signal is not earlier than the ending time of the active level of the second clock signal, so as to ensure that when the output sub-circuit 2 outputs the active level of the second clock signal, the potential of the second node N2 and the first node N1 will not be disturbed by the third clock signal becoming the active level, further affecting the output. Specifically, refer to Figure 3b The first pull-up sub-circuit 5 comprises a sixth transistor T6 and a seventh transistor T7. The gate of the sixth transistor T6 is connected to the second node N2, the source is connected to the second invalid working level signal end VGH2, and the drain is connected to the source of the seventh transistor T7. The gate of the seventh transistor T7 is connected to the third clock signal end, and the drain is connected to the first node N1. In the reset phase T3, the sixth transistor T6 is turned on by the low potential of the second node N2, and the seventh transistor T7 is turned on by the active level of the third clock signal. The second invalid working level signal is transmitted to the first node N1 through the sixth transistor T6 and the seventh transistor T7, and the potential of the first node N1 is pulled up to control the output sub-circuit 4 to stop outputting the second clock signal.

[0079] In some examples, refer to Figure 4a The shift register of the present disclosure further comprises a second pull-up sub-circuit 6 configured to pull up the second node N2 by the second invalid working level signal in the input phase T1 and the output phase T2 in response to the potential of the first node N1. Wherein, the second invalid working level signal is greater than or equal to the first invalid working level signal. Specifically, refer to Figure 4b The second pull-up sub-circuit 6 comprises a ninth transistor T9. The gate of the ninth transistor T9 is connected to the first node N1, the source is connected to the second node N2, and the drain is connected to the second invalid working level signal end VGH2. In the input phase T1 and the output phase T2, the potential of the first node N1 is continuously low, the ninth transistor T9 is turned on by the low potential of the first node N1, and the second invalid working level signal is transmitted to the second node N2 through the ninth transistor T9, so as to pull up the potential of the second node N2, avoid the situation that the first node N1 and the second node N2 have low potential at the same time, and affect the output. Here, the second invalid working level signal is transmitted to the second node N2 and further transmitted to the gate of the fourth transistor T4. Since the gate voltage of the fourth transistor T4 (i.e. the second invalid working level signal) is greater than or equal to the source voltage of the fourth transistor T4 (i.e. the first invalid working level signal), it can be ensured that the fourth transistor T4 is absolutely closed, so as to ensure that the output of the output sub-circuit 4 is not affected.

[0080] In some examples, refer toFigure 5a The shift register of the present disclosure further comprises a voltage stabilizing sub-circuit 7 connected between the input sub-circuit 1 and the output sub-circuit 2. The connection node of the voltage stabilizing sub-circuit 7 and the input sub-circuit 1 is the first sub-node N1-1, and the connection node of the voltage stabilizing sub-circuit 7 and the output sub-circuit 2 is the second sub-node N1-2. The voltage stabilizing sub-circuit 7 is configured to transmit the voltage of the first sub-node N1-1 to the second sub-node N1-2 in response to the working level signal. Specifically, referring to Figure 5b The voltage stabilizing sub-circuit 7 comprises an eighth transistor T8. The gate of the eighth transistor T8 is connected to the working level signal end VGL, the source is connected to the first sub-node N1-1, and the drain is connected to the second sub-node N1-2. The eighth transistor T8 is in an always-on state during the entire working period of the shift register. By setting the eighth transistor T8, the leakage of the second sub-node N1-2 through the first transistor T1 can be avoided, and the voltage of the second sub-node N1-2 is controlled to be in a stable state, further controlling the fifth transistor T5 to be in a stable on or off state.

[0081] In some examples, referring to Figure 6a The shift register of the present disclosure further comprises a protection sub-circuit 8 configured to transmit a second invalid working level signal to the first node N1 in response to the working level signal between the input stages T1. Specifically, referring to Figure 6b The protection sub-circuit 8 comprises a tenth transistor T10. The gate of the tenth transistor T10 is connected to the working level signal end VEL, the source is connected to the first node N1, and the drain is connected to the second invalid working level signal end VGH2. Before the input stage T1, that is, at the power-on moment of the display panel, the second invalid working level signal is transmitted to the first node N1 through the tenth transistor T10, pulling up the potential of the first node N1, ensuring that the fifth transistor T5 is in an off state, so that the signal output by the signal output end OUT is a high level signal, avoiding the occurrence of power-on screen flashing.

[0082] In order to more specifically describe the shift register of the embodiment of the present disclosure, a specific embodiment is given below. Referring to Figure 7a The shift register comprises an input sub-circuit 1, an output sub-circuit 2, a first control sub-circuit 3, a holding sub-circuit 4, a first pull-up sub-circuit 5, a second pull-up sub-circuit 6, a voltage stabilizing sub-circuit 7, and a protection sub-circuit 8. The connection node of the input sub-circuit 1, the first pull-up sub-circuit 5, the second pull-up sub-circuit 6, the voltage stabilizing sub-circuit 7, and the protection sub-circuit 8 is the first sub-node N1-1, the connection node of the output sub-circuit 2 and the protection sub-circuit 8 is the second sub-node N1-2, and the connection node of the first control sub-circuit 3, the first pull-up sub-circuit 5, the second pull-up sub-circuit 6, and the holding sub-circuit 4 is the second node N2.

[0083] Specifically, referring to Figure 7b , the input sub-circuit 1 comprises a first transistor T1, a gate of the first transistor T1 is connected with a first clock signal terminal CK1, a source is connected with an input signal terminal INPUT, and a drain is connected with a first sub-node N1-1. The output sub-circuit 2 comprises a fifth transistor T5 and a second capacitor C2, a gate of the fifth transistor T5 is connected with a second sub-node N1-2, a source is connected with a signal output terminal OUT, and a drain is connected with a second clock signal terminal CK2, two poles of the second capacitor C2 are connected with the gate and the source of the fifth transistor T5 respectively. The first control sub-circuit 3 comprises a second transistor T2, a third transistor T3 and a first capacitor C1, a gate of the second transistor T2 is connected with the input signal terminal INPUT, a source is connected with a gate of the third transistor T3, and a drain is connected with a second invalid working level signal terminal VGH2, a source of the third transistor T3 is connected with a third clock signal terminal CK3, and a drain is connected with a second node N2, two poles of the first capacitor C1 are connected with the gate and the source of the third transistor T3 respectively. The holding sub-circuit 4 comprises a fourth transistor T4 and a third capacitor C3, a gate of the fourth transistor T4 is connected with the second node N2, a source is connected with a first invalid working level signal terminal VGH1, and a drain is connected with the signal output terminal OUT, two poles of the third capacitor C3 are connected with the source and the gate of the fourth transistor T4 respectively. The first pull-up sub-circuit 5 comprises a sixth transistor T6 and a seventh transistor T7, a gate of the sixth transistor T6 is connected with the second node N2, a source is connected with the second invalid working level signal terminal VGH2, and a drain is connected with a source of the seventh transistor T7, a gate of the seventh transistor T7 is connected with the third clock signal terminal CK3, and a drain is connected with the first sub-node N1-1. The second pull-up sub-circuit 6 comprises a ninth transistor T9, a gate of the ninth transistor T9 is connected with the first sub-node N1-1, a source is connected with the second node N2, and a drain is connected with the second invalid working level signal terminal VGH2. The voltage stabilizing sub-circuit 7 comprises an eighth transistor T8, a gate of the eighth transistor T8 is connected with a working level signal terminal VGL, a source is connected with the first sub-node N1-1, and a drain is connected with the second sub-node N1-2. The protection sub-circuit comprises a tenth transistor T10, a gate of the tenth transistor T10 is connected with a protection level signal terminal VEL, a source is connected with the first sub-node N1-1, and a drain is connected with the second invalid working level signal terminal VGH2.

[0084] Figure 8 is a circuit timing diagram corresponding to the shift register in Figure 7b . Referring to Figure 8The working stages of the shift register include: an input stage T1, an output stage T2 and a reset stage T3. It should be noted that before the shift register starts to work, i.e. before the input stage T1, i.e. at the power-on moment of the display panel, the protection level signal end VEL writes a low-level signal to turn on the tenth transistor, the second invalid working level signal is transmitted to the first sub-node N1-1 through the tenth transistor T10, the potentials of the first sub-node N1-1 and the second sub-node N1-2 are pulled high, the fifth transistor T5 is ensured to be in a closed state, and thus the signal output from the signal output end OUT is a high-level signal, i.e. the invalid working level signal, so as to avoid the power-on flash screen. The working processes of the stages of the shift register are as follows:

[0085] In the input stage T1, the input signal end INPUT writes a low-level signal, the first clock signal end CK1 writes a low-level signal, the second clock signal end CK2 writes a high-level signal, and the third clock signal end CK3 writes a high-level signal. The first transistor T1 and the second transistor T2 are turned on, the low-level signal written by the input signal end INPUT is transmitted to the first sub-node N1-1 through the first transistor T1, the potentials of the first sub-node N1-1 and the second sub-node N1-2 are pulled low, the fifth transistor T5 is turned on, and the high-level signal written by the second clock signal end CK2 is transmitted to the signal output end OUT through the fifth transistor T5. At the same time, the second invalid working level signal is transmitted to the gate of the third transistor T3 through the second transistor T2, and the third transistor T3 is closed. Since the first sub-node N1-1 is a low-level signal, the ninth transistor T9 is turned on, the second invalid working level signal is transmitted to the second node N2 through the ninth transistor T9, the potential of the second node N2 is pulled high, and the fourth transistor T4 is closed.

[0086] In the output stage T2, the input signal end INPUT writes a high-level signal, the first clock signal end CK1 writes a high-level signal, the second clock signal end CK2 writes a low-level signal, and the third clock signal end CK3 writes a high-level signal. The first transistor T1 and the second transistor T2 are closed by the high-level signal written by the input signal end INPUT, and the third transistor T3 is closed by the low-level signal written by the third clock signal end CK3, i.e. the shift register has no signal input in the output stage T2. Due to the coupling effect of the second capacitor C2 and the third capacitor C3, the first sub-node N1-1 and the second sub-node N1-2 continue to maintain a low potential, and the second node N2 continues to maintain a high potential. The high potential of the second sub-node N1-2 turns on the fifth transistor T5, and the low-level signal written by the second clock signal end CK2 is transmitted to the signal output end OUT through the fifth transistor T5.

[0087] In the reset stage T3, the input signal end INPUT writes a high level signal, the first clock signal end CK1 writes a high level signal, the second clock signal end CK2 writes a high level signal, and the third clock signal end CK3 writes a low level signal. The first transistor T1 and the second transistor T2 continue to keep the closed state, the third transistor T3 is opened by the low level signal written by the third clock signal end CK3, the third clock signal is transmitted to the second node N2 through the third transistor T3, and the potential of the second node N2 is pulled low. The fourth transistor T4 and the sixth transistor T6 are both opened by the low potential of the second node N2, and the first invalid working level signal VGH1 is transmitted to the signal output end OUT through the fourth transistor T4. At the same time, the low level signal written by the third clock signal end CK3 opens the seventh transistor T7, so that the second invalid working level signal VGH2 is transmitted to the first sub-node N1-1 through the sixth transistor T6 and the seventh transistor T7 in turn, the potential of the first sub-node N1-1 and the second sub-node N1-2 is pulled high, the fifth transistor T5 is closed, and the next working stage is prepared.

[0088] The start time of the effective level of the second clock signal is not earlier than the end time of the effective level of the first clock signal, and the start time of the effective level of the third clock signal is not earlier than the end time of the effective level of the second clock signal. That is, the effective level of the first clock signal, the second clock signal and the third clock signal has no overlap in the duration period, so that the situation of transistor misopening in the working process can be avoided, thereby improving the reliability of the circuit.

[0089] The disclosure also provides a gate drive circuit comprising a plurality of cascaded shift registers of any of the above-mentioned embodiments, and a structural schematic diagram of the gate drive circuit is shown in Figure 9 . Wherein, for the i-th shift register, the signal output end OUT is connected to the input signal end INPUT of the i+1-th shift register, and i is a positive integer.

[0090] Referring to Figures 9-10 , the gate drive circuit is connected with four clock signal lines, i.e. the first clock signal line CLK1, the second clock signal line CLK2, the third clock signal line CLK3 and the fourth clock signal line CLK4. Wherein, the clock signals transmitted on the four clock signal lines are square wave signals with the same period and duty cycle, and the duty cycle of the square wave signal is less than 25%. In one period of the square wave, the start time (i.e. the falling edge) of the four clock signals is sequentially different by 1H, and H is the unit scanning time.

[0091] Continuing to refer to Figure 9For each of the plurality of cascaded shift registers in the gate driving circuit, the first clock signal end CK1 receiving the first clock signal, the second clock signal end CK2 receiving the second clock signal and the third clock signal end CK3 receiving the third clock signal are configured, and the first clock signal end CK1, the second clock signal end CK2 and the third clock signal end CK3 are connected with three different clock signal lines respectively. That is, each of the shift registers is connected with three of the four clock signal lines, i.e. the first clock signal line CLK1, the second clock signal line CLK2, the third clock signal line CLK3 and the fourth clock signal line CLK4. For the gate driving circuit, the i-th shift register and the i+4-th shift register are connected with the same three clock signal lines, and i is a positive integer. For example, the first clock signal end CK1, the second clock signal end CK2 and the third clock signal end CK3 of the first shift register are connected with the first clock signal line CLK1, the second clock signal line CLK2 and the third clock signal line CLK3 respectively, and the first clock signal end CK1, the second clock signal end CK2 and the third clock signal end CK3 of the fifth shift register, the ninth shift register, the thirteenth shift register and the (4a+1)-th shift register are also connected with the first clock signal line CLK1, the second clock signal line CLK2 and the third clock signal line CLK3 respectively, and a is an integer greater than or equal to 0.

[0092] Optionally, four shift registers in each cascade are a group, and the four shift registers in the same group are connected with three different clock signal lines respectively. Specifically, referring to Figure 9For example, the first to fourth stage shift registers GOA1-GOA4, the first clock signal end CK1 of the first stage shift register GOA1 is connected with the first clock signal line CLK1, the second clock signal end CK2 of the first stage shift register GOA1 is connected with the second clock signal line CLK2, and the third clock signal end CK3 of the first stage shift register GOA1 is connected with the third clock signal line CLK3; the first clock signal end CK1 of the second stage shift register GOA2 is connected with the second clock signal line CLK2, the second clock signal end CK2 of the second stage shift register GOA2 is connected with the third clock signal line CLK3, and the third clock signal end CK3 of the second stage shift register GOA2 is connected with the fourth clock signal line CLK4; the first clock signal end CK1 of the third stage shift register GOA3 is connected with the third clock signal line CLK3, the second clock signal end CK2 of the third stage shift register GOA3 is connected with the fourth clock signal line CLK4, and the third clock signal end CK3 of the third stage shift register GOA3 is connected with the first clock signal line CLK1; the first clock signal end CK1 of the fourth stage shift register GOA4 is connected with the fourth clock signal line CLK4, the second clock signal end CK2 of the fourth stage shift register GOA4 is connected with the first clock signal line CLK1, and the third clock signal end CK3 of the fourth stage shift register GOA4 is connected with the second clock signal line CLK2. In this way, the four cascaded shift registers output the first, second, third and fourth gate drive signals in turn, and the starting time of the effective level of the four gate drive signals is sequentially different by 1H. After the first stage shift register GOA1 outputs the first gate drive signal, the first gate drive signal is not only used to drive the corresponding row of pixel units to emit light, but also used as the input signal of the second stage shift register GOA2 to drive the second stage shift register GOA2 to output the second stage shift register GOA2; and so on. Each shift register works in turn, outputs the gate drive signal in turn, drives the corresponding pixel unit to emit light, and drives the next stage shift register to work.

[0093] The present disclosure also provides a display panel, referring to Figure 11The display panel is divided into a display area and a peripheral area surrounding the display area. A plurality of pixel units P arranged in an array are arranged in the display area, and the peripheral area is provided with a gate drive circuit GOA and a source drive circuit Source Driver IC for driving the pixel units P to emit light, and a timing controller Tcon for providing a clock signal CLK for the gate drive circuit GOA. The gate drive circuit GOA provides a gate drive signal for the pixel units P through a gate line Gate, and the source drive circuit Source Driver IC provides a data signal for the pixel units through a data line Date. The pixel unit P includes a pixel drive circuit and a light emitting device, and after receiving the gate drive signal and the data signal, the pixel drive circuit starts to work and drives the light emitting device to emit light. The gate drive circuit includes a plurality of cascaded shift registers in the above embodiments, and each shift register is configured to provide a gate drive signal for a row of pixel units.

[0094] In some examples, the display panel can be included in any product or component having a display function, such as a flexible wearable device, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, etc. Other essential components for the display are understood by those skilled in the art and are not described here in detail, and should not be considered as a limitation on the present application.

[0095] It can be understood that the above embodiments are only exemplary embodiments adopted for illustrating the principles of the present application, and the present application is not limited thereto. Various modifications and improvements can be made by those skilled in the art without departing from the spirit and essence of the present application, and these modifications and improvements are also considered to be within the protection scope of the present application.

Claims

1. A shift register comprising an input sub-circuit, an output sub-circuit, a first control sub-circuit and a holding sub-circuit; wherein, the input sub-circuit is configured to transmit an input signal to a first node in response to a first clock signal; the first node is a connection node of the input sub-circuit and the output sub-circuit; the output sub-circuit is configured to output a second clock signal through a signal output terminal in response to a potential of the first node; the first control sub-circuit is configured to control a potential of a second node through a third clock signal in response to the input signal and the third clock signal; the second node is a connection node of the first control sub-circuit and the holding sub-circuit; the holding sub-circuit is configured to output a first invalid working level signal through the signal output terminal in response to the potential of the second node.

2. The shift register of claim 1, wherein, the first control sub-circuit comprises a second transistor, a third transistor and a first capacitor; a control electrode of the second transistor is connected to a signal input terminal, a first electrode is connected to a control electrode of the third transistor, and a second electrode is connected to a second invalid working level signal terminal; the second invalid working level signal is greater than or equal to the first invalid working level signal; a control electrode of the third transistor is connected to the first electrode of the second transistor and a first electrode of the first capacitor, a first electrode is connected to a second electrode of the first capacitor and a third clock signal terminal, and a second electrode is connected to the second node.

3. The shift register of claim 1, wherein, The shift register further comprises a first pull-up sub-circuit; the first pull-up sub-circuit is configured to pull up the first node through a second invalid working level signal in response to the third clock signal and the potential of the second node; the second invalid working level signal is greater than or equal to the first invalid working level signal.

4. The shift register of claim 3, wherein, the first pull-up sub-circuit comprises a sixth transistor and a seventh transistor; a control electrode of the sixth transistor is connected to the second node, a first electrode is connected to a second invalid working level signal terminal, and a second electrode is connected to a first electrode of the seventh transistor; a control electrode of the seventh transistor is connected to a third clock signal terminal, and a second electrode is connected to the first node.

5. The shift register of claim 1, wherein, The shift register further comprises a second pull-up sub-circuit; the second pull-up sub-circuit is configured to pull up the second node through a second invalid working level signal in response to the potential of the first node; the second invalid working level signal is greater than or equal to the first invalid working level signal.

6. The shift register of claim 5, wherein, the second pull-up sub-circuit comprises a ninth transistor; a control electrode of the ninth transistor is connected to the first node, a first electrode is connected to the second node, and a second electrode is connected to a second invalid working level signal terminal.

7. The shift register of claim 1, wherein, The shift register further comprises a protection sub-circuit; the protection sub-circuit is configured to transmit a second invalid working level signal to the first node in response to a protection level signal; the second invalid working level signal is greater than or equal to the first invalid working level signal.

8. The shift register of claim 7, wherein, the protection sub-circuit comprises a tenth transistor; a control electrode of the tenth transistor is connected to a protection level signal terminal, a first electrode is connected to the first node, and a second electrode is connected to a second invalid working level signal terminal.

9. The shift register of claim 1, wherein, The shift register further comprises a voltage stabilizing sub-circuit; The voltage stabilizing sub-circuit is connected between the input sub-circuit and the output sub-circuit; a connection node of the voltage stabilizing sub-circuit and the input sub-circuit is a first sub-node, and a connection node of the voltage stabilizing sub-circuit and the output sub-circuit is a second sub-node; The voltage stabilizing sub-circuit is configured to transmit the voltage of the first sub-node to the second sub-node in response to a working level signal.

10. The shift register of claim 9, wherein, The voltage stabilizing sub-circuit comprises an eighth transistor; The control electrode of the eighth transistor is connected to a working level signal end, the first electrode is connected to the first sub-node, and the second electrode is connected to the second sub-node.

11. The shift register of claim 1, wherein, The input sub-circuit comprises a first transistor; The control electrode of the first transistor is connected to a first level signal end, the first electrode is connected to a signal input end, and the second electrode is connected to the first node.

12. The shift register of claim 1, wherein, The output sub-circuit comprises a fifth transistor and a second capacitor; The control electrode of the fifth transistor is connected to the first node, the first electrode is connected to the signal output end, and the second electrode is connected to a second clock signal end; The first electrode of the second capacitor is connected to the control electrode of the fifth transistor, and the second electrode is connected to the first electrode of the fifth transistor.

13. The shift register of claim 1, wherein, The holding sub-circuit comprises a fourth transistor and a third capacitor; The control electrode of the fourth transistor is connected to the second node, the first electrode is connected to a first invalid working level signal end, and the second electrode is connected to the signal output end; the first electrode of the third capacitor is connected to the control electrode of the fourth transistor, and the second electrode is connected to the first electrode of the fourth transistor.

14. A gate drive circuit comprising a plurality of cascaded shift registers according to any one of claims 1-13; For the gate drive circuit, the i-th shift register is connected to the i+4-th shift register with the same clock signal line; i is a positive integer.

15. The gate drive circuit of claim 14, wherein, The gate drive circuit is connected to four clock signal lines, which are a first clock signal line, a second clock signal line, a third clock signal line and a fourth clock signal line; the starting time of the effective level of the four clock signals on the four clock signal lines is sequentially different by 1H, H being a unit scanning time; The shift register is configured with a first clock signal end, a second clock signal end and a third clock signal end for receiving the first clock signal, the second clock signal and the third clock signal respectively; the first clock signal end, the second clock signal end and the third clock signal end of the shift register are connected to three different clock signal lines respectively; The voltage stabilizing sub-circuit comprises an eighth transistor; Each four cascaded shift registers is a group, for a group of the shift registers, wherein the first clock signal end of the first stage shift register is connected with the first clock signal line, the second clock signal end is connected with the second clock signal line, and the third clock signal end is connected with the third clock signal line; the first clock signal end of the second stage shift register is connected with the second clock signal line, the second clock signal end is connected with the third clock signal line, and the third clock signal end is connected with the fourth clock signal line; the first clock signal end of the third stage shift register is connected with the third clock signal line, the second clock signal end is connected with the fourth clock signal line, and the third clock signal end is connected with the first clock signal line; the first clock signal end of the fourth stage shift register is connected with the fourth clock signal line, the second clock signal end is connected with the first clock signal line, and the third clock signal end is connected with the second clock signal line.

16. A display panel, which is divided into a display area and a peripheral area surrounding the display area; a plurality of pixel units arranged in an array are arranged in the display area, and a gate driving circuit according to claim 14 or 15 is arranged in the peripheral area; each of the shift registers in the gate driving circuit is configured to provide a gate driving signal for a row of the pixel units.

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