Multi-channel four-quadrant power supply circuit based on FPGA
By using the EP4CE6F17C8 FPGA to replace the AD5648 analog-to-digital converter, combined with PWM regulation and automatic calibration, the high cost and low precision problems of multi-channel four-quadrant power supplies are solved, and the adjustable and independent output of voltage and current are achieved.
Patent Information
- Application Number
- CN202422664513.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-01
- Publication Date
- 2025-10-24
- Estimated Expiration
- 2034-11-01
AI Technical Summary
In existing multi-channel four-quadrant power supplies, ADC chips result in high economic costs, poor readback accuracy, and the inability to adjust voltage or current. Furthermore, the output cannot be effectively calibrated, affecting the accuracy and independence of voltage and current.
The EP4CE6F17C8 FPGA is used to replace the AD5648 analog-to-digital converter, and PWM adjustment is performed through the FPGA's IO port. The voltage and current can be adjusted by combining the algorithm. A readback circuit is set for automatic calibration to ensure output accuracy and independence.
The output voltage and current of each channel can be adjusted, which ensures the readback accuracy and output accuracy, reduces the cost, and ensures the independence and stability of each channel.
Smart Images
Figure CN223472182U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The utility model relates to a kind of multi-channel four-quadrant power supply circuit based on FPGA. BACKGROUND
[0002] In the temperature stability of voltage source or current source and anti-noise interference ability is unchanged, the quantity of measurement in unit time is also unchanged, using original ADC chip as multi-channel four-quadrant power supply, so that multi-channel four-quadrant power supply increases economic cost, the accuracy of back reading is relatively poor, and the voltage or current output by each channel is not controllable and cannot be adjusted;At the same time, using original ADC chip cannot guarantee calibration to the output voltage or current when back reading error is too large, and cannot guarantee back reading accuracy and the accuracy of output voltage or current. SUMMARY
[0003] The utility model discloses a kind of multi-channel four-quadrant power supply circuit based on FPGA, using the FPGA of EP4CE6F17C8 model instead of original multiple AD5648 analog-digital converters, to reduce the production cost of voltage source and current source, and the multi-channel four-quadrant power supply circuit is improved to adapt to the FPGA of EP4CE6F17C8 model.
[0004] Technical scheme: to achieve the above object, a kind of multi-channel four-quadrant power supply circuit based on FPGA of the utility model, including voltage current switching circuit, voltage current amplification circuit, limiting circuit, back reading current circuit, back reading voltage current and isolation circuit;The output end of voltage current switching circuit is electrically connected with the input end of voltage current amplification circuit, and the output end of voltage current amplification circuit is electrically connected with the input end of isolation circuit;The limiting circuit limits the maximum value and minimum value of voltage or current output by voltage current amplification circuit;The back reading current circuit monitors the current output by the output end of isolation circuit and is fed back to voltage current switching circuit, and the back reading voltage circuit monitors the voltage output by the output end of isolation circuit and is fed back to voltage current switching circuit.
[0005] Further, the voltage current switching circuit includes TMI1 end, TMV1 end and voltage current switching end;TMI1 end, TMV1 end and voltage current switching end are electrically connected with the output end of voltage current switching circuit by connecting switch;The voltage current switching end is used to switch current output or voltage output;The output end of voltage current switching circuit is electrically connected with the negative input end of U2A integrated circuit in voltage current amplification circuit.
[0006] Further, the voltage and current amplification circuit further comprises a D2 triode and a D3 triode; a positive input end of the U2A integrated circuit inputs a CTRL1 signal, an output end of the U2A integrated circuit is electrically connected to a negative input end of the U2A integrated circuit through a C1 capacitor; the output end of the U2A integrated circuit is electrically connected to bases of the D2 triode and the D3 triode through an R1 resistor, an emitter of the D2 triode is electrically connected to an emitter of the D3 triode, and the emitters of the D2 triode and the D3 triode are grounded through an R8 resistor.
[0007] Further, the isolation circuit comprises a CH1 integrated circuit; emitters of the D2 triode and the D3 triode are electrically connected to an OUT+ end of the CH1 integrated circuit, and the OUT+ end of the CH1 integrated circuit is grounded through a C9 capacitor; an LED+ end of the CH1 integrated circuit inputs a +3.3V IC through an R11 resistor; and an OUT end of the CH1 integrated circuit outputs a voltage or a current.
[0008] Further, the limiting circuit comprises a D4H triode, a D5L triode, a U6A integrated circuit and a U6B integrated circuit; emitters of the D4H triode and the D5L triode are electrically connected to the output end of the U2A integrated circuit through the R1 resistor; a base of the D4H triode is electrically connected to a positive end of a D1 diode through an R2 resistor, a negative end of the D1 diode is electrically connected to an output end of the U6A integrated circuit, and the output end of the U6A integrated circuit is electrically connected to a negative input end of the U6A integrated circuit through a C2 capacitor; a base of the D5L triode is electrically connected to a negative end of a D7 diode through an R3 resistor, a positive end of the D1 diode is electrically connected to an output end of the U6B integrated circuit, and the output end of the U6B integrated circuit is electrically connected to a negative input end of the U6B integrated circuit through a C3 capacitor; a positive input end of the U6A integrated circuit inputs an LMVH1 signal, a positive input end of the U6B integrated circuit inputs an LMVL1 signal, and the negative input end of the U6A integrated circuit is electrically connected to the negative input end of the U6B integrated circuit through the R4 resistor and the R5 resistor in series.
[0009] Further, the read-back current circuit comprises a U5 integrated circuit; an IN+ end of the U5 integrated circuit is electrically connected to the emitters of the D2 triode and the D3 triode through an R6 resistor, an IN- end of the U5 integrated circuit is electrically connected to the emitters of the D2 triode and the D3 triode through the R6 resistor, and the IN+ end of the U5 integrated circuit is electrically connected to the IN- end of the U5 integrated circuit through a C5 capacitor; and an OUT end of the U5 integrated circuit is electrically connected to a TMI1 end of the voltage and current switching circuit.
[0010] Further, the read-back voltage circuit comprises a U2B integrated circuit; a positive input end of the U2B integrated circuit is electrically connected to emitters of D2 and D3 through an R9 resistor, and the positive input end of the U2B integrated circuit is connected to ground through a C6 capacitor and an R10 resistor in parallel; a negative input end of the U2B integrated circuit is electrically connected to an output end of the U2B integrated circuit, and the output end of the U2B integrated circuit is electrically connected to a TMV1 end of the voltage-current switching circuit.
[0011] Beneficial effects: the utility model discloses a kind of based on FPGA's multi-channel four quadrant power supply circuit, EP4CE6F17C8 model FPGA is replaced with the original multiple AD5648 analog-digital converter, and the multi-channel four quadrant power supply circuit is improved to adapt EP4CE6F17C8 model FPGA;PWM is used with the IO port of FPGA, in a cycle, the size of regulated voltage is realized by adjusting duty cycle, so that each channel realizes output voltage current adjustable;While EP4CE6F17C8 model FPGA combines certain algorithm, eliminate the deviation of the read-back voltage measurement result on board and theoretical value, adopt automatic calibration, ensure that read-back precision guarantees the precision of output;Ensure that each channel can monitor voltage, circuit loop and voltage measurement loop are independently separated, meet the demand of product optical module to voltage source precision, reduce the cost of power supply. BRIEF DESCRIPTION OF DRAWINGS
[0012] Figure 1 It is a block diagram of the multi-channel four quadrant power supply circuit based on FPGA;
[0013] Figure 2 It is a circuit diagram of the multi-channel four quadrant power supply circuit based on FPGA. DETAILED DESCRIPTION
[0014] The utility model will be further described below in connection with the drawings.
[0015] As Figure 1 As shown in a kind of multi-channel four quadrant power supply circuit based on FPGA, it is characterized in that: including voltage-current switching circuit 1, voltage-current amplification circuit 2, limiting circuit 4, read-back current circuit 5, read-back voltage current 6 and isolation circuit 3;The output end of voltage-current switching circuit 1 is electrically connected to the input end of voltage-current amplification circuit 2, and the output end of voltage-current amplification circuit 2 is electrically connected to the input end of isolation circuit 3;The limiting circuit 4 limits the maximum value and minimum value of the voltage or current output by voltage-current amplification circuit 2;The read-back current circuit 4 monitors the current output by the output end of isolation circuit 3 and is fed back to voltage-current switching circuit 1, and the read-back voltage circuit 6 monitors the voltage output by the output end of isolation circuit 3 and is fed back to voltage-current switching circuit 1.
[0016] AsFigure 2 As shown in the figure, the voltage and current switching circuit 1 includes a TMI1 end, a TMV1 end and a voltage and current switching end; the TMI1 end, the TMV1 end and the voltage and current switching end are all electrically connected to the output end of the voltage and current switching circuit 1 through a connection switch; the voltage and current switching end is used for switching current output or voltage output, and when voltage output or current output is needed, the voltage and current switching circuit is switched; the output end of the voltage and current switching circuit 1 is electrically connected to the negative input end of the U2A integrated circuit 21 in the voltage and current amplification circuit 2.
[0017] As shown in the figure, Figure 2 As shown in the figure, the voltage and current amplification circuit 2 further includes a D2 triode 22 and a D3 triode 23; the positive input end of the U2A integrated circuit 21 inputs a CTRL1 signal, the output end of the U2A integrated circuit 21 is electrically connected to the negative input end of the U2A integrated circuit 21 through a C1 capacitor; the output end of the U2A integrated circuit 21 is electrically connected to the base of the D2 triode 22 and the D3 triode 23 through an R1 resistor, the emitter of the D2 triode 22 is electrically connected to the emitter of the D3 triode 23, and the emitters of the D2 triode 22 and the D3 triode 23 are grounded through an R8 resistor. The positive power supply end and the negative power supply end of the U2A integrated circuit 21 are electrically connected to +10V power supply and -10V power supply respectively, the collector of the D2 triode 22 is electrically connected to +10V power supply, the collector of the D3 triode 23 is electrically connected to -10V power supply, and +10V power supply is grounded through a C7 capacitor, -10V power supply is grounded through a C8 capacitor; the U2A integrated circuit 21, the D2 triode 22 and the D3 triode 23 together constitute a push-pull circuit; the U2A integrated circuit 21 adjusts the amplified voltage or current according to the CTRL1 signal output by the IO port of the FPGA after PWM, and outputs by the output end of the U2A integrated circuit 21.
[0018] As shown in the figure, Figure 2As shown, the isolation circuit 3 includes CH1 integrated circuit 31; the OUT+ end of the CH1 integrated circuit 31 is electrically connected to the emitter of D2 triode 22 and D3 triode 23, and the OUT+ end of the CH1 integrated circuit 31 is grounded through C9 capacitor, the LED+ end of the CH1 integrated circuit 31 inputs +3.3VIC through R11 resistor, the NC end of the CH1 integrated circuit 31 is connected to the SW1 signal end of the expansion chip of I / O, when the NC end of the CH1 integrated circuit 31 outputs a switch signal, the corresponding press channel is opened, and the output voltage or current OUT1 of the CH1 integrated circuit 31 outputs voltage or current through the channel; when the NC end of the CH1 integrated circuit 31 does not output a switch signal, the corresponding press channel is closed, and the output voltage or current OUT1 of the CH1 integrated circuit 31 cannot output voltage or current through the channel; the output voltage or current OUT1 of the isolation circuit 3 outputs corresponding voltage or current OUT of each channel; the isolation circuit 3 is used for isolating the output end and the input end, preventing mutual interference between the output end and the input end.
[0019] As shown in the figure, Figure 2 As shown, the limiting circuit 4 includes D4H triode 41, D5L triode 42, U6A integrated circuit 43 and U6B integrated circuit 44; the emitter of the D4H triode 41 and the emitter of the D5L triode 42 are both electrically connected to the output end of the U2A integrated circuit 21 through the R1 resistor; the base of the D4H triode 41 is electrically connected to the positive end of the D1 diode through the R2 resistor, the negative end of the D1 diode is electrically connected to the output end of the U6A integrated circuit 43, and the output end of the U6A integrated circuit 43 is electrically connected to the negative input end of the U6A integrated circuit 43 through the C2 capacitor; the base of the D5L triode 42 is electrically connected to the negative end of the D7 diode through the R3 resistor, the positive end of the D1 diode is electrically connected to the output end of the U6B integrated circuit 44, and the output end of the U6B integrated circuit 44 is electrically connected to the negative input end of the U6B integrated circuit 44 through the C3 capacitor; the positive input end of the U6A integrated circuit 43 inputs the LMVH1 signal, the positive input end of the U6B integrated circuit 44 inputs the LMVL1 signal, and the negative input end of the U6A integrated circuit 43 is electrically connected to the negative input end of the U6B integrated circuit 44 through the R4 resistor and the R5 resistor in series.
[0020] As shown in the figure, Figure 2As shown in the figure, the collector of the D4H triode 41 and the collector of the D5L triode 42 are grounded, the positive power supply end and the negative power supply end of the U6B integrated circuit 44 are electrically connected with the +10V power supply and the -10V power supply respectively, and the +10V power supply is grounded through the C7 capacitor and the -10V power supply is grounded through the C8 capacitor; the LMVH1 signal and the LMVL1 signal are inputted according to the requirement setting to limit the maximum value and the minimum value of the output voltage of the output end of the U2A integrated circuit 21, and the voltage value range of the output of the voltage current amplification circuit 2 is limited through the limiting circuit 4; at the same time of limiting the range of the output voltage, the whole circuit is protected from overvoltage or overcurrent phenomenon and is not damaged.
[0021] As shown in the figure, Figure 2 As shown in the figure, the read-back current circuit includes the U5 integrated circuit 51; the IN+ end of the U5 integrated circuit 51 is electrically connected with the emitter of the D2 triode 22 and the D3 triode 23 through the R6 resistor, the IN- end of the U5 integrated circuit 51 is electrically connected with the emitter of the D2 triode 22 and the D3 triode 23 through the R6 resistor, and the IN+ end of the U5 integrated circuit 51 is electrically connected with the IN- end of the U5 integrated circuit 51 through the C5 capacitor; the OUT end of the U5 integrated circuit 51 is electrically connected with the TMI1 end of the voltage current switching circuit 1; the +VS end of the U5 integrated circuit 51 is electrically connected with the +10V power supply, the -VS end of the U5 integrated circuit 51 is electrically connected with the -10V power supply, and the +10V power supply is grounded through the C7 capacitor and the -10V power supply is grounded through the C8 capacitor.
[0022] As shown in the figure, Figure 2 As shown in the figure, the read-back voltage circuit 6 includes the U2B integrated circuit 61; the positive input end of the U2B integrated circuit 61 is electrically connected with the emitter of the D2 triode 22 and the D3 triode 23 through the R9 resistor, and the positive input end of the U2B integrated circuit 61 is grounded through the C6 capacitor and the R10 resistor in parallel; the negative input end of the U2B integrated circuit 61 is electrically connected with the output end of the U2B integrated circuit 61, and the output end of the U2B integrated circuit 61 is electrically connected with the TMV1 end of the voltage current switching circuit 1.
[0023] The U5 integrated circuit 51 in the back-reading current circuit will monitor the output current input to the TMI1 end of the voltage-current switching circuit 1 and transmitted to the U2A integrated circuit 21 in the voltage-current amplification circuit 2, and at the same time transmitted to the FPGA, and according to the received feedback voltage or current and the output voltage or current, the calculation is carried out to ensure that the back-reading accuracy is about 0.5%; if the error is too large, the FPGA combines the algorithm to eliminate the certain deviation between the back-reading voltage measurement result and the theoretical value, and the automatic calibration is adopted, the duty cycle of the PWM is adjusted to realize the adjustment of the output voltage or current, and the stability and accuracy of the output voltage or current are ensured. The U2B integrated circuit 61 in the back-reading voltage circuit will monitor the output voltage input to the TMV1 end of the voltage-current switching circuit 1 and transmitted to the U2A integrated circuit 21 in the voltage-current amplification circuit 2, and at the same time transmitted to the FPGA, and according to the received feedback voltage or current and the output voltage or current, the calculation is carried out to ensure that the back-reading accuracy is about 0.5%; if the error is too large, the FPGA combines the algorithm to eliminate the certain deviation between the back-reading voltage measurement result and the theoretical value, and the automatic calibration is adopted, the duty cycle of the PWM is adjusted to realize the adjustment of the output voltage or current, and the stability and accuracy of the output voltage or current are ensured. At the same time, according to the monitored voltage output by the back-reading voltage circuit and the monitored current output by the back-reading current circuit, the range of the output voltage limited by the limiting circuit is adjusted to realize the adjustment of the voltage or current.
[0024] The FPGA of EP4CE6F17C8 type is adopted to replace the original multiple AD5648 analog-digital converters, cost is saved, and the multi-channel four-quadrant power supply circuit is improved to adapt to the FPGA of EP4CE6F17C8 type, the IO port of the FPGA is used to realize PWM, in a cycle, the duty cycle is adjusted to realize the size of the regulated voltage, so that the output voltage and current of each channel are realized; since the multi-channel four-quadrant power supply circuit comprises multiple channels for output, to ensure that the multiple channels are independent of each other, the CH1 integrated circuit 31 is not only one; each channel is provided with a CH integrated circuit; 48-channel voltage / current source independent power supply can be realized through the expansion chip of the I / O, for example, the SW1 signal of the expansion chip of the I / O is connected to the NC end of the CH1 integrated circuit to control the switch of channel 1, the SW2 signal of the expansion chip of the I / O is connected to the NC end of the CH2 integrated circuit to control the switch of channel 2, and so on; the setting limiting circuit, the read-back current circuit and the read-back voltage circuit are arranged, and the performance of the 48-channel voltage source is ensured unchanged. The voltage output range of each channel is-7.5-7.5V, the step is 0.1V, the minimum resolution is 10mV, the output ripple is within 50mV, the negative output capacity of each channel is-7.5-0V@200mA, the positive output capacity of each channel is 0-7.5V@5.5W, wherein 3.3V@1.5A and 10V@550mA, and when the current output is 0mA-500mA and-500mA-0mA, the read-back accuracy is 0.5%, and the EOS risk of each channel is prohibited.
[0025] The U2A integrated circuit 21, the U2B integrated circuit 61, the U6A integrated circuit 43 and the U6B integrated circuit 44 are all operational amplifier circuits, the U5 integrated circuit 51 is a current detection chip, and the CH1 integrated circuit 31 is an optical coupling chip.
[0026] The above is only the description of the preferred embodiment of the present application, and those skilled in the art can make some modifications and optimizations on the basis of the above disclosure without departing from the above basic principles, and these modifications and optimizations should be regarded as the protection scope of the present application.
Claims
1. An FPGA-based multi-channel four-quadrant power supply circuit, characterized by: The application relates to a voltage-current switching circuit (1), a voltage-current amplification circuit (2), a limiting circuit (4), a back-reading current circuit (5), a back-reading voltage-current circuit (6) and an isolation circuit (3); the output end of the voltage-current switching circuit (1) is electrically connected with the input end of the voltage-current amplification circuit (2), and the output end of the voltage-current amplification circuit (2) is electrically connected with the input end of the isolation circuit (3); the limiting circuit (4) limits the maximum and minimum values of the voltage or current output by the voltage-current amplification circuit (2); the back-reading current circuit (4) monitors the current output by the output end of the isolation circuit (3) and feeds back to the voltage-current switching circuit (1), and the back-reading voltage circuit (6) monitors the voltage output by the output end of the isolation circuit (3) and feeds back to the voltage-current switching circuit (1).
2. The FPGA-based multi-channel four-quadrant power supply circuit of claim 1, wherein: The voltage-current switching circuit (1) comprises a TMI1 end, a TMV1 end and a voltage-current switching end; the TMI1 end, the TMV1 end and the voltage-current switching end are all electrically connected with the output end of the voltage-current switching circuit (1) through connecting switches. The voltage-current switching end is used for switching current output or voltage output; the output end of the voltage-current switching circuit (1) is electrically connected with the negative input end of a U2A integrated circuit (21) in the voltage-current amplification circuit (2).
3. The FPGA-based multi-channel four-quadrant power supply circuit of claim 2, wherein: The voltage-current amplification circuit (2) further comprises a D2 triode (22) and a D3 triode (23); the positive input end of the U2A integrated circuit (21) inputs a CTRL1 signal, the output end of the U2A integrated circuit (21) is electrically connected with the negative input end of the U2A integrated circuit (21) through a C1 capacitor; the output end of the U2A integrated circuit (21) is electrically connected with the bases of the D2 triode (22) and the D3 triode (23) through an R1 resistor, the emitter of the D2 triode (22) is electrically connected with the emitter of the D3 triode (23), and the emitters of the D2 triode (22) and the D3 triode (23) are grounded through an R8 resistor.
4. The FPGA-based multi-channel four-quadrant power supply circuit of claim 3, wherein: The isolation circuit (3) comprises a CH1 integrated circuit (31); the emitters of the D2 triode (22) and the D3 triode (23) are electrically connected with the OUT+ end of the CH1 integrated circuit (31), and the OUT+ end of the CH1 integrated circuit (31) is grounded through a C9 capacitor; the LED+ end of the CH1 integrated circuit (31) inputs a +3.3VIC through an R11 resistor, and the OUT end of the CH1 integrated circuit (31) outputs voltage or current.
5. The FPGA-based multi-channel four-quadrant power supply circuit of claim 3, wherein: The limiting circuit (4) comprises a D4H transistor (41), a D5L transistor (42), a U6A integrated circuit (43) and a U6B integrated circuit (44); the emitter of the D4H transistor (41) and the emitter of the D5L transistor (42) are both electrically connected to the output end of the U2A integrated circuit (21) through the R1 resistor; the base of the D4H transistor (41) is electrically connected to the positive end of the D1 diode through the R2 resistor, the negative end of the D1 diode is electrically connected to the output end of the U6A integrated circuit (43), and the output end of the U6A integrated circuit (43) is electrically connected to the negative end of the U6A integrated circuit (43) through the C2 capacitor. The base of the D5L transistor (42) is electrically connected to the negative end of the D7 diode through the R3 resistor, the positive end of the D1 diode is electrically connected to the output end of the U6B integrated circuit (44), and the output end of the U6B integrated circuit (44) is electrically connected to the negative input end of the U6B integrated circuit (44) through the C3 capacitor; the positive input end of the U6A integrated circuit (43) inputs the LMVH1 signal, the positive input end of the U6B integrated circuit (44) inputs the LMVL1 signal, and the negative input end of the U6A integrated circuit (43) is electrically connected to the negative input end of the U6B integrated circuit (44) through the R4 resistor and the R5 resistor connected in series.
6. The FPGA-based multi-channel four-quadrant power supply circuit of claim 3, wherein: The readback current circuit comprises a U5 integrated circuit (51); an IN+ terminal of the U5 integrated circuit (51) is electrically connected to the emitters of the D2 transistor (22) and the D3 transistor (23) through a resistor R6, an IN- terminal of the U5 integrated circuit (51) is electrically connected to the emitters of the D2 transistor (22) and the D3 transistor (23) through a resistor R6, and an IN+ terminal of the U5 integrated circuit (51) is electrically connected to an IN- terminal of the U5 integrated circuit (51) through a capacitor C5; and an OUT terminal of the U5 integrated circuit (51) is electrically connected to a TMI1 terminal of a voltage-current switching circuit (1).
7. The FPGA-based multi-channel four-quadrant power supply circuit of claim 3, wherein: The readback voltage circuit (6) comprises a U2B integrated circuit (61); the positive input terminal of the U2B integrated circuit (61) is electrically connected to the emitters of the D2 transistor (22) and the D3 transistor (23) via the R9 resistor, and the positive input terminal of the U2B integrated circuit (61) is grounded via the C6 capacitor and the R10 resistor connected in parallel; the negative input terminal of the U2B integrated circuit (61) is electrically connected to the output terminal of the U2B integrated circuit (61), and the output terminal of the U2B integrated circuit (61) is electrically connected to the TMV1 terminal of the voltage-current switching circuit (1).