Display substrate and display device

Abstract

A display substrate and a display device relate to the technical field of display. The display substrate comprises a plurality of sub-pixels, and each sub-pixel comprises a thin film transistor. The display substrate comprises a substrate, a first conductive layer, a semiconductor layer, a first insulating layer and a second conductive layer, the first conductive layer, the semiconductor layer, the first insulating layer and the second conductive layer are sequentially stacked on one side of the substrate, the first conductive layer is close to the substrate and comprises a data line, and the semiconductor layer comprises a plurality of semiconductor patterns located at different sub-pixels. The semiconductor pattern comprises a source electrode connection region, a first conductor region and a channel region which are arranged along a first direction and are connected in sequence, and the second conductive layer comprises a first switching pattern and a grid electrode; wherein the first insulating layer is provided with a first via hole, the first via hole exposes a part of the data line, the source electrode connecting area and the first conductor area, the data line and the source electrode connecting area are in lap joint with the first switching pattern through the first via hole, and the orthographic projection of the first switching pattern and the orthographic projection of the first conductor area on the substrate are not overlapped.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of display, and in particular, to a display substrate and a display device. BACKGROUND

[0002] Electronic paper usually adopts electrophoresis display (EPD) as a display panel. Electronic paper display not only has the advantages of comfortable reading, ultra-thin and light, bendable, and the like, similar to paper, but also can refresh the display content, and has lower power consumption than liquid crystal display. CONTENT

[0003] The present disclosure provides a display substrate, comprising a display area and a non-display area surrounding the display area, the display area comprising a plurality of sub-pixels, the sub-pixel comprising a thin film transistor;

[0004] The display substrate comprises a first conductive layer, a semiconductor layer, a first insulating layer and a second conductive layer which are sequentially stacked, the first conductive layer is arranged close to the substrate, the first conductive layer comprises a data line, the semiconductor layer comprises a plurality of semiconductor patterns located in different sub-pixels, the semiconductor pattern comprises a source connection area, a first conductorization area and a channel area of the thin film transistor, the source connection area, the first conductorization area and the channel area are arranged along a first direction and sequentially connected, and the second conductive layer comprises a first transfer pattern, a scanning line and a gate of the thin film transistor.

[0005] The first insulating layer is provided with a first via hole, the first via hole exposes a part of the data line, the source connection area and the first conductorization area, the data line and the source connection area are respectively overlapped with the first transfer pattern through the first via hole, and the first transfer pattern does not overlap with the first conductorization area in the orthographic projection on the substrate.

[0006] In some embodiments, the semiconductor pattern further comprises:

[0007] a second conductorization area connected between the first conductorization area and the channel area, the thickness of the first conductorization area is less than the thickness of the second conductorization area, the thickness of the first conductorization area is less than or equal to the thickness of the source connection area, and the thickness of the second conductorization area is less than or equal to the thickness of the channel area.

[0008] In some embodiments, the semiconductor pattern further comprises:

[0009] The drain connection region, the third conductorization region, and the fourth conductorization region of the thin film transistor are arranged along the first direction and are sequentially connected, and the thickness of the third conductorization region is less than the thickness of the fourth conductorization region;

[0010] The second conductive layer further includes a second transfer pattern, the second transfer pattern is located on the side of the gate away from the first transfer pattern, and the first insulating layer further includes a second via hole, the second via hole exposes the drain connection region and the third conductorization region, the second transfer pattern and the drain connection region are overlapped through the second via hole, and the second transfer pattern and the third conductorization region do not overlap in the orthographic projection on the substrate.

[0011] In some embodiments, the sub-pixel further includes a common electrode and a first pixel electrode, the second transfer pattern overlaps the common electrode in the orthographic projection on the substrate, and the second transfer pattern constitutes the first pixel electrode.

[0012] In some embodiments, the sub-pixel further includes a common electrode and a first pixel electrode, the second transfer pattern does not overlap the common electrode in the orthographic projection on the substrate;

[0013] The semiconductor pattern further includes a fifth conductorization region located on the side of the drain connection region away from the channel region and connected with the drain connection region, the fifth conductorization region overlaps the common electrode in the orthographic projection on the substrate, and the fifth conductorization region constitutes the first pixel electrode.

[0014] In some embodiments, the sub-pixel further includes a first common electrode, a first pixel electrode, a second common electrode, and a second pixel electrode, the first pixel electrode is located in the semiconductor layer or the second conductive layer, the first common electrode is located in a layer different from the first pixel electrode and overlaps the first pixel electrode in the orthographic projection on the substrate, and the display substrate further includes:

[0015] A third conductive layer located on the side of the second conductive layer away from the substrate and including the second common electrode; and

[0016] A transparent conductive layer located on the side of the third conductive layer away from the substrate and including the second pixel electrode, the second pixel electrode overlaps the second common electrode in the orthographic projection on the substrate, the second pixel electrode is connected with the first pixel electrode through a via hole, and the first pixel electrode is further connected with the drain connection region of the thin film transistor.

[0017] In some embodiments, the first pixel electrode comprises a plurality of sub-electrodes arranged along a second direction and connected in sequence, the second direction being perpendicular to the first direction, and different sub-electrodes have different widths along the first direction.

[0018] In some embodiments, the widths of the plurality of sub-electrodes along the first direction increase in sequence in a direction away from the channel region along the second direction.

[0019] In some embodiments, the plurality of sub-electrodes are substantially aligned away from the edge of the channel region in the orthographic projection on the substrate.

[0020] In some embodiments, the first common electrode is located on the first conductive layer, and the first common electrode is located between two adjacent data lines.

[0021] The second conductive layer further comprises a third transfer pattern located on the first transfer pattern and on the side of the gate electrode away from the scan line, the second common electrode and the first common electrode are connected to the third transfer pattern through vias, respectively, and the third transfer pattern does not overlap with the orthographic projection of the first pixel electrode on the substrate.

[0022] In some embodiments, the plurality of sub-electrodes comprises a first sub-electrode, a second sub-electrode and a third sub-electrode connected in sequence, the first sub-electrode is connected to the drain connection region of the thin film transistor, and is located on the side of the drain connection region away from the channel region.

[0023] In the orthographic projection on the substrate, the second sub-electrode and the third transfer pattern are arranged along the first direction, the first common electrode overlaps with the second sub-electrode and the third sub-electrode, respectively, and the first common electrode does not overlap with the first sub-electrode.

[0024] In some embodiments, the third conductive layer further comprises:

[0025] A fourth transfer pattern, the fourth transfer pattern is arranged separately from the second common electrode, the second sub-electrode and the second pixel electrode are connected to the fourth transfer pattern through vias, respectively, and in the orthographic projection on the substrate, the fourth transfer pattern is located in the region of the second sub-electrode.

[0026] In some embodiments, the first common electrode is located on the third conductive layer, and the first common electrode shares the same electrode with the second common electrode.

[0027] The second conductive layer further comprises a second transfer pattern, the second transfer pattern is located on a side of the gate away from the first transfer pattern, and the second transfer pattern is configured to connect the first pixel electrode and the second pixel electrode.

[0028] In an orthographic projection on the substrate, the same electrode covers the first transfer pattern and the gate, and has no overlap with the second transfer pattern.

[0029] In some embodiments, the first pixel electrode is located on the semiconductor layer, the plurality of sub-electrodes comprises a fourth sub-electrode and a fifth sub-electrode connected in sequence, the fourth sub-electrode is connected to the drain connection region of the thin film transistor, and is located on a side of the drain connection region away from the channel region.

[0030] In an orthographic projection on the substrate, the second transfer pattern is located within a range of the fourth sub-electrode, and the same electrode respectively overlaps the fourth sub-electrode near the edge of the channel region and the fifth sub-electrode.

[0031] In some embodiments, the display substrate further comprises:

[0032] a second insulating layer disposed between the second conductive layer and the third conductive layer; and

[0033] an organic insulating layer disposed between the second insulating layer and the third conductive layer, and an orthographic projection of the organic insulating layer and the first pixel electrode on the substrate at least partially overlaps.

[0034] In some embodiments, in an orthographic projection on the substrate, the first pixel electrode and the second pixel electrode respectively have no overlap with the scan line, the first pixel electrode is located within a region of the second pixel electrode, a gap width between second pixel electrodes of adjacent two sub-pixels is greater than or equal to 5 microns and less than or equal to 15 microns.

[0035] In some embodiments, in an orthographic projection on the substrate, the first common electrode and the second common electrode respectively have no overlap with the data line, the second common electrode has an overlapping region with the scan line, and a width of the overlapping region along the first direction is less than a width of a non-overlapping region along the first direction.

[0036] The present disclosure provides a display device, comprising: an opposed substrate, an electrophoretic solution, and a display substrate as described in any one of the embodiments, the electrophoretic solution is located between the opposed substrate and the display substrate, and the second conductive layer is located on a side of the substrate close to the electrophoretic solution.

[0037] The above description is only an overview of the technical solution of the present disclosure. In order to more clearly understand the technical means of the present disclosure, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present disclosure more obvious and easy to understand, the specific implementation methods of the present disclosure are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or related technologies, the following is a brief introduction to the drawings required for the description of the embodiments or related technologies. Obviously, the drawings described below are some embodiments of the present disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without inventive efforts. It should be noted that the scales in the drawings are for illustration only and do not represent the actual scale.

[0039] Figure 1 A schematic structural diagram of a first display substrate example is shown;

[0040] Figure 2 A schematic diagram of the structure of a display substrate after the first conductive layer is prepared in the first example is shown;

[0041] Figure 3 A schematic diagram of the structure of a display substrate after the semiconductor layer is prepared in the first example is shown;

[0042] Figure 4 A schematic diagram of the structure of a display substrate after the first insulating layer is prepared in the first example is shown;

[0043] Figure 5 A schematic diagram of the structure of the display substrate after the second conductive layer is prepared in the first example is shown;

[0044] Figure 6 A schematic diagram of the structure of a display substrate after the organic insulating layer is prepared in the first example is shown;

[0045] Figure 7 A schematic diagram of the structure of the display substrate after the second insulating layer is prepared in the first example is shown;

[0046] Figure 8 A schematic diagram of the structure of the display substrate after the third conductive layer is prepared in the first example is shown;

[0047] Figure 9 A schematic diagram of the structure of the display substrate after the third insulating layer is prepared in the first example is shown;

[0048] Figure 10 A schematic diagram of the structure of a display substrate after the transparent conductive layer is prepared in the first example is shown;

[0049] Figure 11A structural diagram of a second display substrate example is shown.

[0050] Figure 12 A structural diagram of a display substrate in which the first conductive layer preparation is completed in the second example is shown.

[0051] Figure 13 A structural diagram of a display substrate in which the semiconductor layer preparation is completed in the second example is shown.

[0052] Figure 14 A structural diagram of a display substrate in which the first insulating layer preparation is completed in the second example is shown.

[0053] Figure 15 A structural diagram of a display substrate in which the second conductive layer preparation is completed in the second example is shown.

[0054] Figure 16 A structural diagram of a display substrate in which the organic insulating layer preparation is completed in the second example is shown.

[0055] Figure 17 A structural diagram of a display substrate in which the second insulating layer preparation is completed in the second example is shown.

[0056] Figure 18 A structural diagram of a display substrate in which the third conductive layer preparation is completed in the second example is shown.

[0057] Figure 19 A structural diagram of a display substrate in which the third insulating layer preparation is completed in the second example is shown.

[0058] Figure 20 A structural diagram of a display substrate in which the transparent conductive layer preparation is completed in the second example is shown.

[0059] Figure 21 A structural diagram of a third display substrate example is shown.

[0060] Figure 22 A structural diagram of a display substrate in which the first conductive layer preparation is completed in the third example is shown.

[0061] Figure 23 A structural diagram of a display substrate in which the semiconductor layer preparation is completed in the third example is shown.

[0062] Figure 24 A structural diagram of a display substrate in which the first insulating layer preparation is completed in the third example is shown.

[0063] Figure 25 A structural diagram of a display substrate in which the second conductive layer preparation is completed in the third example is shown.

[0064] Figure 26A schematic diagram of a display substrate structure in which the preparation of the organic insulating layer is completed in the third example is shown.

[0065] Figure 27 A schematic diagram of a display substrate structure in which the preparation of the third conductive layer is completed in the third example is shown.

[0066] Figure 28 A schematic diagram of a display substrate structure in which the preparation of the third insulating layer is completed in the third example is shown.

[0067] Figure 29 A schematic diagram of a display substrate structure in which the preparation of the transparent conductive layer is completed in the third example is shown.

[0068] Figure 30 A column chart showing the variation of the electric field intensity in the channel region with the doping concentration of the first conductorized region is shown.

[0069] Figure 31 A schematic diagram of a cross-sectional structure of a display device is exemplarily shown.

[0070] Figure 32 A schematic diagram of a connection structure of a display device is exemplarily shown. DETAILED DESCRIPTION

[0071] To make the objects, technical solutions, and advantages of the embodiments of the present disclosure clearer, the technical solutions in the embodiments of the present disclosure will be described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only some, but not all of the embodiments of the present disclosure. Based on the embodiments in the present disclosure, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the protection scope of the present disclosure.

[0072] In the related art, electronic paper mainly realizes full-color display in the following two ways: the first is color-printed electronic paper technology, which is electronic paper matched with color filters, and converts black-and-white electronic paper into full-color electronic paper by using the principle of color mixing; the second is color electronic paper technology, which is composed of ink particles of four colors (such as yellow, cyan, magenta, and white), and the corresponding color ink particles are pushed to the display side by applying an electric field using the principle of positive and negative attraction, and different colors of particles are mixed to present colorful colors.

[0073] In order to drive electronic paper to perform full-color display, a higher driving voltage needs to be provided, for example, VGH≥28V and VGL≤-28V. However, the highest use voltage of the display substrate in the related art cannot meet the driving requirements of color electronic paper, and therefore, there is an urgent need to develop a high-voltage display substrate.

[0074] The present disclosure provides a display substrate, such as Figure 1 ,Figure 11 or Figure 21 As shown in a and b, the display substrate includes a display area AA and a non-display area NA surrounding the display area AA, the display area AA includes a plurality of sub-pixels PX, and each sub-pixel PX includes a thin film transistor.

[0075] It should be noted that, in Figures 1 to 29 , a schematically shows a planar structure of one sub-pixel PX in the display substrate, b schematically shows a cross-sectional structure along AA' in a of the display substrate, and c schematically shows cross-sectional structures along BB' and CC' in a of the display substrate. In Figures 1 to 10 , d schematically shows a planar structure of four sub-pixels PX in the display substrate.

[0076] As shown in a and b, the display substrate includes a display area AA and a non-display area NA surrounding the display area AA, the display area AA includes a plurality of sub-pixels PX, and each sub-pixel PX includes a thin film transistor. Figure 1 , Figure 11 or Figure 21 As shown in a and b, the display substrate includes a display area AA and a non-display area NA surrounding the display area AA, the display area AA includes a plurality of sub-pixels PX, and each sub-pixel PX includes a thin film transistor.

[0077] In the display substrate, the first conductive area DT1 is exposed at the position of the first via H1, and the orthographic projection of the first transfer pattern ZJ1 on the substrate 10 does not overlap the first conductive area DT1, that is, the first transfer pattern ZJ1 does not cover the first conductive area DT1. That is, the first transfer pattern ZJ1 realizes the communication between the data line DL and the source connection area S by half covering or half lapping the first via H1. By adjusting the doping concentration of the first conductive area DT1 exposed by the first via H1, the resistance of the first via H1 can be adjusted, and the voltage division of the first via H1 can be adjusted, thereby facilitating the improvement of the voltage resistance of the thin film transistor.

[0078] In the display substrate, the first conductive area DT1 is exposed at the position of the first via H1, and the orthographic projection of the first transfer pattern ZJ1 on the substrate 10 does not overlap the first conductive area DT1, that is, the first transfer pattern ZJ1 does not cover the first conductive area DT1. That is, the first transfer pattern ZJ1 realizes the communication between the data line DL and the source connection area S by half covering or half lapping the first via H1. By adjusting the doping concentration of the first conductive area DT1 exposed by the first via H1, the resistance of the first via H1 can be adjusted, and the voltage division of the first via H1 can be adjusted, thereby facilitating the improvement of the voltage resistance of the thin film transistor.

[0079] Referring to Figure 30A bar chart showing the channel region CH electric field strength as a function of the first conductorization region DT1 doping concentration is shown. As shown, as the first conductorization region DT1 doping concentration decreases, the channel region CH electric field strength decreases. This is because as the first conductorization region DT1 doping concentration decreases, the first via H1 resistance and voltage division increases, thus the channel region CH electric field strength decreases, which in turn increases the thin film transistor voltage withstand capability. Figure 30

[0080] In the present disclosure, a thin film transistor refers to an element including at least three terminals of a gate G, a drain, and a source. The thin film transistor has a channel region CH between the drain and the source, and a current can flow through the drain, the channel region CH, and the source. In the present disclosure, the channel region CH refers to a region through which a current mainly flows.

[0081] In the present disclosure, in the case of using a thin film transistor having opposite polarity or in the case of changing the current direction in the circuit operation, the functions of the "source" and the "drain" are sometimes exchanged with each other. Therefore, in the present disclosure, the "source" and the "drain" can be exchanged with each other.

[0082] Exemplarily, the material of the active layer 12 includes an oxide semiconductor material such as IGZO, and can also include amorphous silicon or low-temperature polysilicon, and the present disclosure is not limited thereto.

[0083] In some embodiments, the channel region CH of the thin film transistor includes a semiconductor material M1OaNb, where M1 is a single metal or a combination of multiple metals, a > 0, and b ≥ 0, O represents an oxygen element, and N represents a nitrogen element, that is, the semiconductor material is a metal oxide material or a metal nitride oxide material. Suitable metal oxide materials include, but are not limited to, one or more of indium gallium zinc oxide (IGZO), indium gallium tin oxide (IGTO), indium tin zinc oxide (ITZO), indium gallium oxide (IGO), indium gallium zinc tin oxide (IGZTO), indium zinc oxide (IZO), zinc tin oxide (ZTO), In-free OS, rare earth doped oxide (Ln-OS, such as rare earth element doped IGZO / IZO), zinc oxide (ZnO), gallium oxide (GaO), indium oxide (InO), HfInZnO (HIZO), ZnO:F, In2O3:Sn, In2O3:Mo, Cd2SnO4, ZnO:Al, TiO2:Nb, and Cd-Sn-O. The material of the channel CH can be in an amorphous, partially crystalline, single crystalline, or polycrystalline state, and can also be a single layer or a multi-layer structure.

[0084] ​Suitable metal oxynitride materials include, but are not limited to, zinc oxynitride, indium oxynitride, gallium oxynitride, tin oxynitride, cadmium oxynitride, aluminum oxynitride, germanium oxynitride, titanium oxynitride, silicon oxynitride, or a combination thereof. In one example, the material of the channel region CH includes indium gallium zinc oxide (IGZO).

[0085] Exemplarily, referring to Figure 2 , Figure 12 or Figure 22 , the data line DL includes a first line segment XD1 extending along the second direction f2, and a second line segment XD2 extending along the first direction f1. As shown in Figure 1 , Figure 11 or Figure 21 , the second line segment XD2 is connected at a side of the first line segment XD1 close to the channel region CH, the second line segment XD2 is exposed at the first via H1, and the second line segment XD2 has an overlap with a normal projection of the source connection region S on the substrate 10, and the first transfer pattern ZJ1 connects the second line segment XD2 and the source connection region S by half-joining the first via H1. The source connection region S is arranged close to a position where the first line segment XD1 intersects with the scan line GL.

[0086] Exemplarily, the first direction f1 is parallel to an extension direction of the scan line GL.

[0087] Exemplarily, as shown in Figure 1 , Figure 11 or Figure 21 , the sub-pixel PX further includes a pixel electrode EP1 / EP2, the gate G of the thin film transistor is connected with the scan line GL, the source connection region S is connected with the data line DL through the first transfer pattern ZJ1, the drain connection region D is connected with the pixel electrode EP1 / EP2, and the pixel electrode EP1 / EP2 is used to drive the target particles to move. The target particles can be electrophoretic particles such as two-color particles, three-color particles, four-color particles, or the like, or can be liquid crystal molecules.

[0088] In the present disclosure, the movement of the target particles can refer to the up-and-down movement (such as movement along a direction perpendicular to the substrate 10) or the left-and-right movement (such as movement along a direction parallel to the substrate 10) between two substrates or polar plates, or can refer to the up-and-down, left-and-right, or front-and-back deflection of the target particles between the two substrates or polar plates.

[0089] Since the source connection region S and the first conductorization region DT1 can be over-etched in the process of forming the first via H1, as shown in Figure 1 , Figure 11 or Figure 21 , the thicknesses of the source connection region S and the first conductorization region DT1 are less than the thickness of the channel region CH.

[0090] Exemplarily, as shown inFigure 1 , Figure 11 or Figure 21 As shown in FIG. 1, the thickness of the first conductive region DT1 is less than or equal to the thickness of the source connection region S.

[0091] In some embodiments, as shown in FIG. 1, the semiconductor pattern further comprises: a second conductive region DT2 connected between the first conductive region DT1 and the channel region CH, the thickness of the first conductive region DT1 is less than the thickness of the second conductive region DT2, and the thickness of the second conductive region DT2 is less than or equal to the thickness of the channel region CH. Figure 1 , Figure 11 or Figure 21 As shown in FIG. 1, the thickness of the first conductive region DT1 is less than or equal to the thickness of the source connection region S.

[0092] In some embodiments, as shown in FIG. 1, the semiconductor pattern further comprises: a second conductive region DT2 connected between the first conductive region DT1 and the channel region CH, the thickness of the first conductive region DT1 is less than the thickness of the second conductive region DT2, and the thickness of the second conductive region DT2 is less than or equal to the thickness of the channel region CH. Figure 1 or Figure 21 As shown in FIG. 1, the thickness of the first conductive region DT1 is less than or equal to the thickness of the source connection region S.

[0093] In some embodiments, as shown in FIG. 1, the semiconductor pattern further comprises: a second conductive region DT2 connected between the first conductive region DT1 and the channel region CH, the thickness of the first conductive region DT1 is less than the thickness of the second conductive region DT2, and the thickness of the second conductive region DT2 is less than or equal to the thickness of the channel region CH.

[0094] As shown in FIG. 1, the thickness of the first conductive region DT1 is less than or equal to the thickness of the source connection region S.

[0095] Exemplarily, the thickness of the drain connection region D is substantially equal to that of the source connection region S, the thickness of the third conductor region DT3 is substantially equal to that of the first conductor region DT1, and the thickness of the fourth conductor region DT4 is substantially equal to that of the second conductor region DT2.

[0096] In a specific implementation, after forming the second conductive layer M2, the first insulating layer GI can be etched a second time using the second conductive layer M2 as a mask. Then, the semiconductor material in the exposed areas of the semiconductor layer ACT (such as the first conductive area DT1, the second conductive area DT2, the third conductive area DT3, and the fourth conductive area DT4) can be conductively converted using a self-aligned process, again using the second conductive layer M2 as a mask. For example, the conductive conversion process can be performed by injecting plasma (such as plasma containing at least one of helium, oxygen, nitrogen, chlorine, hydrogen, boron, and phosphorus) into the semiconductor material using dry etching equipment or ion implantation equipment, or by doping one or more of the aforementioned elements into the semiconductor material to achieve conductive conversion. The conductive conversion of the semiconductor material using the dry etching equipment can be performed simultaneously with the secondary etching process of the first insulating layer GI, thereby simplifying the process.

[0097] In a specific implementation, after forming the second conductive layer M2, the first insulating layer GI may not be etched for the second time. The second conductive layer M2 may be directly used as a mask to conduct the semiconductor material in the exposed areas of the semiconductor layer ACT (such as the first conductive area DT1, the second conductive area DT2, the third conductive area DT3 and the fourth conductive area DT4) through a self-alignment process. The conduction process may, for example, use dry etching equipment or ion implantation equipment to inject plasma (such as plasma containing at least one of helium, oxygen, nitrogen, chlorine, hydrogen, boron and phosphorus) into the semiconductor material, or use an ion doping process to dope any one or more of the above elements into the semiconductor material to achieve conduction.

[0098] For example, when the first insulating layer GI is etched twice, Figure 1 、 Figure 11 or Figure 21 As shown, the second conductive region DT2 and the first insulating layer GI do not overlap in their orthographic projections on the substrate 10. The thickness of the first conductive region DT1 is thinner than the thicknesses of the source connection region S and the second conductive region DT2. The thickness of the second conductive region DT2 is thinner than the thickness of the channel region CH. The fourth conductive region DT4 and the first insulating layer GI do not overlap in their orthographic projections on the substrate 10. The thickness of the third conductive region DT3 is thinner than the thicknesses of the drain connection region D and the fourth conductive region DT4. The thickness of the fourth conductive region DT4 is thinner than the thickness of the channel region CH.

[0099] Exemplarily, the first insulating layer GI covers the surface of the second conductorized region DT2 facing away from the substrate 10, the thickness of the second conductorized region DT2 is substantially equal to the thickness of the channel region CH, and the thickness of the first conductorized region DT1 is substantially equal to the thickness of the source connection region S. The first insulating layer GI covers the surface of the fourth conductorized region DT4 facing away from the substrate 10, the thickness of the fourth conductorized region DT4 is substantially equal to the thickness of the channel region CH, and the thickness of the third conductorized region DT3 is substantially equal to the thickness of the drain connection region D.

[0100] Exemplarily, the pixel electrodes EP1 / EP2 of different sub-pixels PX are arranged to be separated from each other, the pixel electrodes EP1 / EP2 can include a first pixel electrode EP1 and can further include a second pixel electrode EP2, the first pixel electrode EP1 and the second pixel electrode EP2 are arranged in different layers and connected by a via, for example.

[0101] Exemplarily, the sub-pixel PX can further include a common electrode EC1 / EC2, the common electrode EC1 / EC2 and the pixel electrode EP1 / EP2 have a mutual overlap on the orthographic projection of the substrate 10 to form a storage capacitor. The common electrodes EC1 / EC2 of different sub-pixels PX can be connected to each other. The common electrode EC1 / EC2 can include a first common electrode EC1 and can further include a second common electrode EC2, the first common electrode EC1 and the second common electrode EC2 can be arranged in the same layer and connected to each other, or can be arranged in different layers and connected by a via.

[0102] In some embodiments, as shown in Figure 1 , the second jumper pattern ZJ2 has an overlap with the orthographic projection of the common electrode EC1 / EC2 on the substrate 10, and the second jumper pattern ZJ2 constitutes the first pixel electrode EP1.

[0103] In some embodiments, as shown in Figure 21 , the second jumper pattern ZJ2 has no overlap with the orthographic projection of the common electrode EC1 / EC2 on the substrate 10. The semiconductor pattern further includes a fifth conductorized region DT5 located on the side of the drain connection region D away from the channel region CH and connected to the drain connection region D, the fifth conductorized region DT5 has an overlap with the orthographic projection of the common electrode EC1 / EC2 on the substrate 10, and the fifth conductorized region DT5 constitutes the first pixel electrode EP1. The second jumper pattern ZJ2 functions to connect the first pixel electrode EP1 and the second pixel electrode EP2.

[0104] In some embodiments, as shown in Figure 1 , Figure 11 or Figure 21As shown, the sub-pixel PX further includes a first common electrode EC1, a first pixel electrode EP1, a second common electrode EC2 and a second pixel electrode EP2. The first pixel electrode EP1 is located in the semiconductor layer ACT (as shown in FIG. 1A) or the second conductive layer M2 (as shown in FIG. 1B). Figure 11 and Figure 21 As shown, the first pixel electrode EP1 is located in the second conductive layer M2, and the first pixel electrode EP1 is the second transfer pattern ZJ2 of the second conductive layer M2. The first pixel electrode EP1 is connected to the drain connection region D through the second via H2. Figure 1

[0105] As shown, the first pixel electrode EP1 is located in the second conductive layer M2, and the first pixel electrode EP1 is the second transfer pattern ZJ2 of the second conductive layer M2. The first pixel electrode EP1 is connected to the drain connection region D through the second via H2.

[0106] As shown, the first pixel electrode EP1 is located in the second conductive layer M2, and the first pixel electrode EP1 is the second transfer pattern ZJ2 of the second conductive layer M2. The first pixel electrode EP1 is connected to the drain connection region D through the second via H2. Figure 1 As shown, the first pixel electrode EP1 is located in the second conductive layer M2, and the first pixel electrode EP1 is the second transfer pattern ZJ2 of the second conductive layer M2. The first pixel electrode EP1 is connected to the drain connection region D through the second via H2.

[0107] Figure 21 As shown, the first pixel electrode EP1 is located in the second conductive layer M2, and the first pixel electrode EP1 is the second transfer pattern ZJ2 of the second conductive layer M2. The first pixel electrode EP1 is connected to the drain connection region D through the second via H2.

[0108] As shown, the first pixel electrode EP1 is located in the second conductive layer M2, and the first pixel electrode EP1 is the second transfer pattern ZJ2 of the second conductive layer M2. The first pixel electrode EP1 is connected to the drain connection region D through the second via H2. Figure 11 As shown, the first pixel electrode EP1 is located in the second conductive layer M2, and the first pixel electrode EP1 is the second transfer pattern ZJ2 of the second conductive layer M2. The first pixel electrode EP1 is connected to the drain connection region D through the second via H2.

[0109] Figure 1 As shown, the first pixel electrode EP1 is located in the second conductive layer M2, and the first pixel electrode EP1 is the second transfer pattern ZJ2 of the second conductive layer M2. The first pixel electrode EP1 is connected to the drain connection region D through the second via H2. Figure 11 Figure 21 As shown, the first pixel electrode EP1 is located in the second conductive layer M2, and the first pixel electrode EP1 is the second transfer pattern ZJ2 of the second conductive layer M2. The first pixel electrode EP1 is connected to the drain connection region D through the second via H2.

[0110] As shown, the first pixel electrode EP1 is located in the second conductive layer M2, and the first pixel electrode EP1 is the second transfer pattern ZJ2 of the second conductive layer M2. The first pixel electrode EP1 is connected to the drain connection region D through the second via H2. Figure 1 and Figure 11 As shown, the first pixel electrode EP1 is located in the second conductive layer M2, and the first pixel electrode EP1 is the second transfer pattern ZJ2 of the second conductive layer M2. The first pixel electrode EP1 is connected to the drain connection region D through the second via H2. Figure 21 ​​​​as shown.

[0111] In some embodiments, as shown in Figure 1 , Figure 11 or Figure 21 , the first pixel electrode EP1 includes a plurality of sub-electrodes 11, the plurality of sub-electrodes 11 are arranged along a second direction f2 and connected in sequence, the second direction f2 intersects the first direction f1, and the widths of different sub-electrodes 11 along the first direction f1 are different.

[0112] Exemplarily, the second direction f2 is parallel to the extension direction of the data line DL. The first direction f1 is perpendicular to the second direction f2, for example.

[0113] Exemplarily, as shown in Figure 1 , Figure 11 or Figure 21 , the widths of the plurality of sub-electrodes 11 along the first direction f1 increase in sequence in the direction away from the channel region CH along the second direction f2.

[0114] Exemplarily, as shown in Figure 1 , Figure 11 or Figure 21 , in the orthographic projection on the substrate 10, the edges (e.g., the lower edges of the sub-electrodes 11 as shown) of the plurality of sub-electrodes 11 away from the channel region CH or the data line DL are approximately aligned.

[0115] Exemplarily, as shown in Figure 1 , Figure 11 or Figure 21 , the plurality of sub-electrodes form a stepped structure in sequence.

[0116] Exemplarily, as shown in Figure 1 or Figure 11 , the plurality of sub-electrodes 11 include a first sub-electrode 111, a second sub-electrode 112, and a third sub-electrode 113 connected in sequence, the first sub-electrode 111 is connected with the drain connection region D of the thin film transistor and is located on the side of the drain connection region D away from the channel region CH. The first sub-electrode 111, the second sub-electrode 112, and the third sub-electrode 113 are arranged in sequence in the direction away from the channel region CH along the second direction f2, the widths of the first sub-electrode 111, the second sub-electrode 112, and the third sub-electrode 113 along the first direction f1 increase in sequence. Moreover, the edges of the first sub-electrode 111, the second sub-electrode 112, and the third sub-electrode 113 away from the channel region CH or the data line DL are approximately aligned, and the first sub-electrode 111, the second sub-electrode 112, and the third sub-electrode 113 form a three-level stepped structure.

[0117] Exemplarily, as shown in Figure 1As shown, the plurality of sub-electrodes 11 includes a fourth sub-electrode 114 and a fifth sub-electrode 115 connected in sequence, the fourth sub-electrode 114 is connected with the drain connection region D of the thin film transistor, and is located on the side of the drain connection region D away from the channel region CH. The fourth sub-electrode 114 and the fifth sub-electrode 115 are arranged in sequence along the second direction f2 and away from the channel region CH, and the widths of the fourth sub-electrode 114 and the fifth sub-electrode 115 along the first direction f1 increase in sequence. Moreover, the edges of the fourth sub-electrode 114 and the fifth sub-electrode 115 away from the channel region CH or the data line DL are substantially aligned, and the fourth sub-electrode 114 and the fifth sub-electrode 115 form a two-level stepped structure.

[0118] In some embodiments, as shown in Figure 11 or Figure 1 As shown, the first common electrode EC1 is located in the first conductive layer M1. For example, the first common electrode EC1 is located between two adjacent data lines DL.

[0119] As shown in Figure 1 , the first common electrode EC1 is located in the first conductive layer M1, and the first pixel electrode EP1 is located in the second conductive layer M2, that is, the two plates of the first storage capacitor Cst1 are located in the first conductive layer M1 and the second conductive layer M2, respectively.

[0120] As shown in Figure 11 , the first common electrode EC1 is located in the first conductive layer M1, and the first pixel electrode EP1 is located in the semiconductor layer ACT, that is, the two plates of the first storage capacitor Cst1 are located in the first conductive layer M1 and the semiconductor layer ACT, respectively, and Figure 1 Compared with , the first storage capacitor Cst1 reduces the first insulating layer GI between the two plates, which is beneficial to increase the capacitance of the first storage capacitor Cst1 or reduce the area of the first pixel electrode EP1 and the first common electrode EC1, and further beneficial to improve the pixel density.

[0121] Exemplarily, as shown in Figure 11 or Figure 1 As shown, the second conductive layer M2 further includes a third transfer pattern ZJ3, the third transfer pattern ZJ3 is located on the side of the first transfer pattern ZJ1 and the gate G away from the scan line GL, the second common electrode EC2 and the first common electrode EC1 are connected with the third transfer pattern ZJ3 through the via, and the third transfer pattern ZJ3 does not overlap with the orthographic projection of the first pixel electrode EP1 on the substrate 10.

[0122] As shown in Figure 11 or Figure 1 As shown, the first common electrode EC1 is connected with the third transfer pattern ZJ3 through the via H3, and the second common electrode EC2 is connected with the third transfer pattern ZJ3 through the via RH1.

[0123] Exemplarily, as shown in FIG. 1A or FIG. 1B, in the orthographic projection on the substrate 10, the first common electrode EC1 is arranged along the first direction f1 and overlaps with the first sub-electrode 111 and the second sub-electrode 112, and does not overlap with the third sub-electrode 113. The first common electrode EC1 is located on the side of the first sub-electrode 111 away from the scan line GL. Figure 11 Figure 1 Exemplarily, as shown in FIG. 1A or FIG. 1B, in the orthographic projection on the substrate 10, the first common electrode EC1 is arranged along the first direction f1 and overlaps with the first sub-electrode 111 and the second sub-electrode 112, and does not overlap with the third sub-electrode 113. The first common electrode EC1 is located on the side of the first sub-electrode 111 away from the scan line GL.

[0124] Exemplarily, as shown in FIG. 1A or FIG. 1B, in the orthographic projection on the substrate 10, the first common electrode EC1 is arranged along the first direction f1 and overlaps with the first sub-electrode 111 and the second sub-electrode 112, and does not overlap with the third sub-electrode 113. The first common electrode EC1 is located on the side of the first sub-electrode 111 away from the scan line GL. Figure 1 Figure 11 Exemplarily, as shown in FIG. 1A or FIG. 1B, in the orthographic projection on the substrate 10, the first common electrode EC1 is arranged along the first direction f1 and overlaps with the first sub-electrode 111 and the second sub-electrode 112, and does not overlap with the third sub-electrode 113. The first common electrode EC1 is located on the side of the first sub-electrode 111 away from the scan line GL.

[0125] Exemplarily, as shown in FIG. 1A or FIG. 1B, in the orthographic projection on the substrate 10, the first common electrode EC1 is arranged along the first direction f1 and overlaps with the first sub-electrode 111 and the second sub-electrode 112, and does not overlap with the third sub-electrode 113. The first common electrode EC1 is located on the side of the first sub-electrode 111 away from the scan line GL. Figure 1 Exemplarily, as shown in FIG. 1A or FIG. 1B, in the orthographic projection on the substrate 10, the first common electrode EC1 is arranged along the first direction f1 and overlaps with the first sub-electrode 111 and the second sub-electrode 112, and does not overlap with the third sub-electrode 113. The first common electrode EC1 is located on the side of the first sub-electrode 111 away from the scan line GL.

[0126] Figure 11 Exemplarily, as shown in FIG. 1A or FIG. 1B, in the orthographic projection on the substrate 10, the first common electrode EC1 is arranged along the first direction f1 and overlaps with the first sub-electrode 111 and the second sub-electrode 112, and does not overlap with the third sub-electrode 113. The first common electrode EC1 is located on the side of the first sub-electrode 111 away from the scan line GL. Figure 1 Exemplarily, as shown in FIG. 1A or FIG. 1B, in the orthographic projection on the substrate 10, the first common electrode EC1 is arranged along the first direction f1 and overlaps with the first sub-electrode 111 and the second sub-electrode 112, and does not overlap with the third sub-electrode 113. The first common electrode EC1 is located on the side of the first sub-electrode 111 away from the scan line GL.

[0127] Figure 11 Exemplarily, as shown in FIG. 1A or FIG. 1B, in the orthographic projection on the substrate 10, the first common electrode EC1 is arranged along the first direction f1 and overlaps with the first sub-electrode 111 and the second sub-electrode 112, and does not overlap with the third sub-electrode 113. The first common electrode EC1 is located on the side of the first sub-electrode 111 away from the scan line GL. Figure 1 Exemplarily, as shown in FIG. 1A or FIG. 1B, in the orthographic projection on the substrate 10, the first common electrode EC1 is arranged along the first direction f1 and overlaps with the first sub-electrode 111 and the second sub-electrode 112, and does not overlap with the third sub-electrode 113. The first common electrode EC1 is located on the side of the first sub-electrode 111 away from the scan line GL.​​​​

[0128] Exemplarily, as shown in Figure 11 or Figure 1 shown, the third conductive layer M3 further comprises a fourth transfer pattern ZJ4, the fourth transfer pattern ZJ4 is arranged separately from the second common electrode EC2, the second sub-electrode 112 and the second pixel electrode EP2 are connected to the fourth transfer pattern ZJ4 through the via, and in the orthographic projection on the substrate 10, the fourth transfer pattern ZJ4 is located in the area of the second sub-electrode 112.

[0129] As shown in Figure 1 or Figure 21 shown, the second sub-electrode 112 is connected to the fourth transfer pattern ZJ4 through the via RH2, and the second pixel electrode EP2 is connected to the fourth transfer pattern ZJ4 through the via H4.

[0130] Exemplarily, as shown in Figure 21 shown, the fourth transfer pattern ZJ4 is aligned with the third transfer pattern ZJ3 away from the edge of the scan line GL, and in the second direction f2, the width of the fourth transfer pattern ZJ4 is smaller than the width of the third transfer pattern ZJ3. The fourth transfer pattern ZJ4 is located in the gap of the second common electrode EC2 away from the third transfer pattern ZJ3, and the second common electrode EC2 is arranged on three sides of the fourth transfer pattern ZJ4, such as the left side, the right side and the upper side as shown. The shape of the fourth transfer pattern ZJ4 is, for example, a square. The width of the second common electrode EC2 in the first direction f1 is greater than the width of the first pixel electrode EP1 and the first common electrode EC1 in the first direction f1, and the second common electrode EC2 covers the first pixel electrode EP1 and the first common electrode EC1 in the first direction f1. In the orthographic projection on the substrate 10, the edges of the second common electrode EC2 and the data line DL close to each other are substantially aligned.

[0131] Exemplarily, as shown in Figure 21 shown, the gap between the fourth transfer pattern ZJ4 and the second common electrode EC2 is substantially equal to the gap between the third transfer pattern ZJ3 and the first pixel electrode EP1.

[0132] In some embodiments, as shown in Figure 21 shown, the first common electrode EC1 is located in the third conductive layer M3, and the first common electrode EC1 and the second common electrode EC2 share the same electrode EC. This embodiment can greatly reduce the number of vias, thereby increasing the direct area between electrodes, and further increasing the storage capacitance, which is conducive to improving the pixel density and can more flexibly adjust the size of the storage capacitance according to actual needs.

[0133] Exemplarily, as shown in Figure 21As shown, the second conductive layer M2 further includes a second transfer pattern ZJ2, which is located on the side of the gate G away from the first transfer pattern ZJ1 and is used to connect the first pixel electrode EP1 and the second pixel electrode EP2. In the orthographic projection on the substrate 10, the same electrode EC covers the first transfer pattern ZJ1 and the gate G and does not overlap the second transfer pattern ZJ2. The second transfer pattern ZJ2 is located in the gap of the same electrode EC, and the same electrode EC is located on both sides of the second transfer pattern ZJ2, as shown in the following figure. Figure 21 As shown in the upper side and the right side.

[0134] As shown in the following figure, Figure 21 The second transfer pattern ZJ2 is connected to the first pixel electrode EP1 through a second via H2, and is connected to the second pixel electrode EP2 through a via H5. The center of the second via H2 does not coincide with that of the via H5, and the orthographic projection of the second via H2 and the via H5 on the substrate 10 partially overlaps.

[0135] Exemplarily, as shown in the following figure, Figure 27 The first pixel electrode EP1 is located in the semiconductor layer ACT.

[0136] Exemplarily, as shown in the following figure, Figure 21 In the orthographic projection on the substrate 10, the second transfer pattern ZJ2 is located within the range of the fourth sub-electrode 114, and the same electrode EC overlaps the fourth sub-electrode 114 near the edge of the channel region CH and the fifth sub-electrode 115, respectively.

[0137] Exemplarily, as shown in the following figure, Figure 1 The edge of the gate G away from the scan line GL is aligned with the edge of the second transfer pattern ZJ2 away from the scan line GL. The edges of the same electrode EC near the data line DL are approximately aligned.

[0138] Exemplarily, as shown in the following figure, Figure 11 The same electrode EC includes a first sub-common electrode EC11 and a second sub-common electrode EC12 arranged along the second direction f2 and connected in sequence. In the first direction f1, the width of the first sub-common electrode EC11 is smaller than that of the second sub-common electrode EC12. The junction line of the first sub-common electrode EC11 and the second sub-common electrode EC12 is approximately aligned with the edge of the gate G away from the scan line GL. The first sub-common electrode EC11 is located on the side of the second transfer pattern ZJ2 near the gate G.

[0139] Exemplarily, as shown in the following figure, Figure 21As shown, the display substrate further comprises a second insulating layer PVX1 disposed between the second conductive layer M2 and the third conductive layer M3, and an organic insulating layer RS disposed between the second insulating layer PVX1 and the third conductive layer M3, and the first pixel electrode EP1 and the organic insulating layer RS have no overlap in the orthographic projection on the substrate 10.

[0140] By removing the organic insulating layer RS above the first pixel electrode EP1, the distance between the first pixel electrode EP1 and the first common electrode EC1 is reduced, so that a first storage capacitor Cst1 with a larger capacitance can be formed or the area of the first pixel electrode EP1 and the first common electrode EC1 is reduced, thereby facilitating the increase of the pixel density.

[0141] In some embodiments, as shown in Figure 1 , Figure 11 or Figure 21 , in the orthographic projection on the substrate 10, the first pixel electrode EP1 and the second pixel electrode EP2 have no overlap with the scan line GL, respectively, the first pixel electrode EP1 is located in the area of the second pixel electrode EP2, the gap width w1 between the second pixel electrodes EP2 of adjacent two sub-pixels PX is greater than or equal to 5 microns and less than or equal to 15 microns.

[0142] Exemplarily, as shown in Figure 1 , Figure 11 or Figure 21 , in the orthographic projection on the substrate 10, the first pixel electrode EP1 has no overlap with the data line DL and the scan line GL, and in the first direction f1, the second pixel electrode EP2 at least partially covers the data line DL.

[0143] In some embodiments, as shown in Figure 1 , Figure 11 or Figure 21 , in the orthographic projection on the substrate 10, the first common electrode EC1 and the second common electrode EC2 have no overlap with the data line DL, respectively, the second common electrode EC2 has an overlapping area with the scan line GL, and the width of the overlapping area along the first direction f1 is less than the width of the non-overlapping area along the first direction f1.

[0144] By reducing the width of the second common electrode EC2 in the overlapping area, the parasitic capacitance between the second common electrode EC2 and the scan line GL can be reduced, and the signal stability can be improved.

[0145] Exemplarily, as shown in Figure 1 , Figure 1 or Figures 1 to 29 , in the orthographic projection on the substrate 10, the first common electrode EC1 has no overlap with the scan line GL and the data line DL.

[0146] Exemplarily, as shown in Figure 1 The width w2 of the overlapping area of the second common electrode EC2 and the scan line GL along the first direction f1 is greater than or equal to one time of the line width of the scan line GL and less than or equal to two times of the line width of the scan line GL. The line width of the scan line GL is the width of the scan line GL along the second direction f2.

[0147] Exemplarily, the first conductive layer M1, the second conductive layer M2 and the third conductive layer M3 are all metal layers.

[0148] Exemplarily, the first conductive layer M1, the second conductive layer M2 and the third conductive layer M3 can each independently adopt any one or more of copper, molybdenum, aluminum, titanium, silver, nickel, niobium and the like, and the structure of each conductive layer can be single-layer or stacked.

[0149] In some embodiments, the first conductive layer M1, the second conductive layer M2 and the third conductive layer M3 can include at least one of copper or copper alloy, molybdenum-niobium alloy, molybdenum-nickel alloy, molybdenum-nickel-titanium alloy, such as copper / molybdenum-niobium, molybdenum-niobium / copper, copper / molybdenum-nickel-titanium, molybdenum-nickel-titanium / copper, molybdenum-nickel / copper, copper / molybdenum-nickel, molybdenum-niobium / copper / molybdenum-nickel-titanium, molybdenum-niobium / copper / molybdenum-niobium, molybdenum-nickel / copper / molybdenum-nickel-titanium, and the like.

[0150] Exemplarily, the transparent conductive layer TD can adopt a transparent conductive material, such as ITO, IZO, IGZO, IGO, ZTO and the like metal oxide. The adoption of the metal oxide can improve the oxidation resistance of the transparent conductive layer TD.

[0151] In order to meet the driving requirements of the color electronic paper, exemplarily, in each sub-pixel PX, the storage capacitance formed by the common electrode EC1 / EC2 and the pixel electrode EP1 / EP2 is greater than or equal to 1.0 pF and less than or equal to 2.0 pF, such as 1.2 pF.

[0152] Exemplarily, the storage capacitance includes a first storage capacitance Cst1 formed by the first common electrode EC1 and the first pixel electrode EP1, and a second storage capacitance Cst2 formed by the second common electrode EC2 and the second pixel electrode EP2. Since the first common electrode EC1 is connected to the second common electrode EC2 and the second pixel electrode EP2 is connected to the second pixel electrode EP2, the first storage capacitance Cst1 and the second storage capacitance Cst2 are connected in parallel. Therefore, in each sub-pixel PX, the storage capacitance formed by the common electrode EC1 / EC2 and the pixel electrode EP1 / EP2 is the sum of the capacitance values of the first storage capacitance Cst1 and the second storage capacitance Cst2.

[0153] Exemplarily, as shown in Figure 1As shown in Figure d, data lines DL extend along the row direction (i.e., the second direction f2), and scan lines GL extend along the column direction (i.e., the first direction f1). Subpixels PX in the same column are connected to the same scan line GL, while subpixels PX in two adjacent columns are connected to different scan lines GL. Two columns of subpixels PX are disposed between the two adjacent scan lines GL. Subpixels PX in the same row are connected to two data lines DL, which are disposed on either side of the subpixels PX in that row. Two adjacent subpixels PX in the same row are connected to different data lines DL.

[0154] The following combination Figure 1 The technical solutions provided by the present disclosure are exemplified.

[0155] In a first exemplary embodiment, Figure 1 As shown, the display substrate includes: a substrate 10, and a first conductive layer M1, a buffer layer BF, a semiconductor layer ACT, a first insulating layer GI, a second conductive layer M2, a second insulating layer PVX1, an organic insulating layer RS, a third conductive layer M3, a third insulating layer PVX2 and a transparent conductive layer TD stacked in sequence on one side of the substrate 10, and the first conductive layer M1 is arranged close to the substrate 10.

[0156] like Figure 1 As shown, the first conductive layer M1 includes a data line DL and a first common electrode EC1, the semiconductor layer ACT includes a semiconductor pattern, the semiconductor pattern includes a source connection area S, a first conductive area DT1, a second conductive area DT2, a channel area CH, a fourth conductive area DT4, a third conductive area DT3 and a drain connection area D arranged along a first direction f1 and connected in sequence, the second conductive layer M2 includes a scan line GL, a gate G, a first transfer pattern ZJ1, a second transfer pattern ZJ2 and a third transfer pattern ZJ3, the third conductive layer M3 includes a second common electrode EC2 and a fourth transfer pattern ZJ4, and the transparent conductive layer TD includes a second pixel electrode EP2.

[0157] like Figure 1 As shown, the first transfer pattern ZJ1 connects the data line DL and the source connection area S through a first via H1 half-overlappingly arranged on the first insulating layer GI, and the second transfer pattern ZJ2 is connected to the drain connection area D through a second via H2 half-overlappingly arranged on the first insulating layer GI, and the second transfer pattern ZJ2 serves as the first pixel electrode EP1.

[0158] like Figures 2 to 10As shown, the first common electrode EC1 and the second common electrode EC2 are connected through the third transfer pattern ZJ3. Specifically, the first common electrode EC1 and the third transfer pattern ZJ3 are connected through vias set on the first insulating layer GI and the buffer layer BF, and the second common electrode EC2 and the third transfer pattern ZJ3 are connected through vias set on the second insulating layer PVX1 and the organic insulating layer RS.

[0159] like Figure 2 As shown, the first pixel electrode EP1 and the second pixel electrode EP2 are connected through the fourth switching pattern ZJ4. Specifically, the first pixel electrode EP1 and the fourth switching pattern ZJ4 are connected through vias set on the second insulating layer PVX1 and the organic insulating layer RS, and the second pixel electrode EP2 and the fourth switching pattern ZJ4 are connected through vias set on the third insulating layer PVX2.

[0160] like Figure 3 As shown, the first common electrode EC1 and the first pixel electrode EP1 form the two plates of the first storage capacitor Cst1. The dielectric layer between the two plates includes a first insulating layer GI and a buffer layer BF. The second common electrode EC2 and the second pixel electrode EP2 form the two plates of the second storage capacitor Cst2. The dielectric layer between the two plates includes a third insulating layer PVX2. Testing has shown that when the technical solution provided in this embodiment is applied to a 300 PPI display substrate, the storage capacitance of each subpixel PX can reach 1.2 pF.

[0161] Reference Figure 4 The display substrate provided in this embodiment can be prepared by the following steps:

[0162] Step 11: forming a patterned first conductive layer M1 on the substrate 10, such as Figure 5 As shown, the first conductive layer M1 includes the data line DL and the first common electrode EC1, and may also include a shielding pattern (not shown in the figure), the orthographic projection of the shielding pattern on the substrate 10 covers the channel region CH.

[0163] Step 12: A buffer layer BF and a patterned semiconductor layer ACT are sequentially formed on the side of the first conductive layer M1 facing away from the substrate 10, as shown in FIG. Figure 6 The semiconductor layer ACT is a transparent material and includes semiconductor patterns located in different sub-pixels PX. The semiconductor patterns include a source connection region S, a first conductive region DT1, a second conductive region DT2, a channel region CH, a fourth conductive region DT4, a third conductive region DT3, and a drain connection region D, which are arranged along a first direction f1 and connected in sequence.

[0164] Step 13: forming a patterned first insulating layer GI on the side of the semiconductor layer ACT facing away from the substrate 10, such as Figure 6As shown, the first insulating layer GI is provided with a first via H1, a second via H2 and a third via H3, in the orthographic projection on the substrate 10, the first via H1 and the second via H2 are located on both sides of the channel region CH, the first via H1 exposes a part of the data line DL, the source connection region S and the first conductorized region DT1, the second via H2 exposes the drain connection region D and the third conductorized region DT3, and the third via H3 is located in the region of the first common electrode EC1.

[0165] Step 14: forming a patterned second conductive layer M2 on the side of the first insulating layer GI away from the substrate 10, as shown in FIG. 4B. Figure 7 As shown, the second conductive layer M2 includes a scan line GL, a gate G, a first transfer pattern ZJ1, a second transfer pattern ZJ2 (i.e. a first pixel electrode EP1) and a third transfer pattern ZJ3, the gate G is connected to one side of the scan line GL, the gate G overlaps the channel region CH, the first transfer pattern ZJ1 half covers the first via H1 and is in communication with the data line DL and the source connection region S respectively, the second transfer pattern ZJ2 half covers the second via H2 and is in communication with the drain connection region D, and the third transfer pattern ZJ3 fully covers the third via H3 and is in communication with the first common electrode EC1.

[0166] After the formation of the second conductive layer M2, the first insulating layer GI can be etched again using the second conductive layer M2 as a mask, and then the exposed regions (such as the first conductorized region DT1, the second conductorized region DT2, the third conductorized region DT3 and the fourth conductorized region DT4) in the semiconductor layer ACT can be conductorized using a self-alignment process with the second conductive layer M2 as a mask. The conductorization process can use a dry etching device or an ion implantation device to inject plasma (such as plasma containing at least one of helium, oxygen, nitrogen, chlorine, hydrogen, boron, phosphorus elements) into the semiconductor material, or use an ion doping process to dope any one or more of the above elements into the semiconductor material to realize conductorization. Among them, the conductorization of the semiconductor material using the dry etching device can be carried out synchronously with the second etching process of the first insulating layer GI, so as to simplify the process.

[0167] Step 15: sequentially depositing a second insulating material on the side of the second conductive layer M2 away from the substrate 10 to form a second insulating material layer, and then coating an organic insulating material to form an organic insulating material layer. Then, the organic insulating material layer is patterned to form an organic insulating layer RS, as shown in FIG. 4C. Figure 7As shown, two organic vias are arranged on the organic insulating layer RS, which are a first organic via RH1 and a second organic via RH2. The first organic via RH1 is located in the region of the third transfer pattern ZJ3, and the first organic via RH1 is arranged along the second direction f2 with the third via H3. The second organic via RH2 is located in the region of the first pixel electrode EP1, such as the region of the second sub-electrode 112.

[0168] Exemplarily, as shown in Figure 8 As shown, the third via H3 is arranged along the second direction f2 with the first organic via RH1, and the first organic via RH1 is arranged along the first direction f1 with the second organic via RH2. The first organic via RH1 and the second organic via RH2 have the same shape and the same size.

[0169] Step 16: The second insulating material layer is patterned to form a second insulating layer PVX1, as shown in Figure 9 As shown, two vias are arranged on the second insulating layer PVX1, which are a via PH1 and a via PH2. The via PH1 is arranged in the first organic via RH1, and the via PH2 is arranged in the second organic via RH2.

[0170] Exemplarily, as shown in Figure 10 As shown, the via PH1 is arranged in the center of the first organic via RH1, and the via PH2 is arranged in the center of the second organic via RH2. The via PH1 and the via PH2 are arranged along the first direction f1.

[0171] Step 17: A patterned third conductive layer M3 is formed on the side of the organic insulating layer RS away from the substrate 10, as shown in Figure 11 As shown, the third conductive layer M3 includes a second common electrode EC2 and a fourth transfer pattern ZJ4 which are separated from each other. The second common electrode EC2 covers the via RH1 on the third transfer pattern ZJ3 and communicates with the third transfer pattern ZJ3, and further communicates with the first common electrode EC1. The fourth transfer pattern ZJ4 covers the via RH2 on the first pixel electrode EP1 and communicates with the first pixel electrode EP1.

[0172] Step 18: A patterned third insulating layer PVX2 is formed on the side of the third conductive layer M3 away from the substrate 10, as shown in Figure 11 As shown, the third insulating layer PVX2 is provided with a via H4 which is located in the region of the second organic via RH2 and is used to expose the fourth transfer pattern ZJ4.

[0173] Step 19: A patterned transparent conductive layer TD is formed on the side of the third insulating layer PVX2 away from the substrate 10, as shown in Figure 11As shown, the transparent conductive layer TD includes a second pixel electrode EP2 located in a different sub-pixel PX. The second pixel electrode EP2 covers the via hole H4 located on the fourth switching pattern ZJ4 and is connected to the fourth switching pattern ZJ4 and further connected to the first pixel electrode EP1.

[0174] In a second exemplary embodiment, Figure 11 As shown, the display substrate includes: a substrate 10, and a first conductive layer M1, a buffer layer BF, a semiconductor layer ACT, a first insulating layer GI, a second conductive layer M2, a second insulating layer PVX1, an organic insulating layer RS, a third conductive layer M3, a third insulating layer PVX2 and a transparent conductive layer TD stacked in sequence on one side of the substrate 10, and the first conductive layer M1 is arranged close to the substrate 10.

[0175] like Figure 11 As shown, the first conductive layer M1 includes a data line DL and a first common electrode EC1, the semiconductor layer ACT includes a semiconductor pattern, the semiconductor pattern includes a source connection area S, a first conductive area DT1, a second conductive area DT2, a channel area CH, a drain connection area D and a sixth conductive area DT6 (i.e., a first pixel electrode EP1) arranged along a first direction f1 and connected in sequence, the second conductive layer M2 includes a scan line GL, a gate G, a first transfer pattern ZJ1 and a third transfer pattern ZJ3, the third conductive layer M3 includes a second common electrode EC2 and a fourth transfer pattern ZJ4, and the transparent conductive layer TD includes a second pixel electrode EP2.

[0176] like Figure 11 As shown, the first transfer pattern ZJ1 is connected to the data line DL and the source connection region S through a first via hole H1 half-overlappingly provided on the first insulating layer GI.

[0177] like Figures 12 to 20 As shown, the first common electrode EC1 and the second common electrode EC2 are connected through the third transfer pattern ZJ3. Specifically, the first common electrode EC1 and the third transfer pattern ZJ3 are connected through vias set on the first insulating layer GI and the buffer layer BF, and the second common electrode EC2 and the third transfer pattern ZJ3 are connected through vias set on the second insulating layer PVX1 and the organic insulating layer RS.

[0178] like Figure 12 As shown, the first pixel electrode EP1 and the second pixel electrode EP2 are connected through the fourth switching pattern ZJ4. Specifically, the first pixel electrode EP1 and the fourth switching pattern ZJ4 are connected through vias set on the second insulating layer PVX1 and the organic insulating layer RS, and the second pixel electrode EP2 and the fourth switching pattern ZJ4 are connected through vias set on the third insulating layer PVX2.

[0179] like Figure 13As shown, the first common electrode EC1 and the first pixel electrode EP1 form the two plates of the first storage capacitor Cst1, and the dielectric layer between the two plates includes a buffer layer BF. The second common electrode EC2 and the second pixel electrode EP2 form the two plates of the second storage capacitor Cst2, and the dielectric layer between the two plates includes a third insulating layer PVX2.

[0180] Reference Figure 14 The display substrate provided in this embodiment can be prepared by the following steps:

[0181] Step 21: forming a patterned first conductive layer M1 on the substrate 10, such as Figure 15 As shown, the first conductive layer M1 includes the data line DL and the first common electrode EC1, and may also include a shielding pattern (not shown in the figure), the orthographic projection of the shielding pattern on the substrate 10 covers the channel region CH.

[0182] Step 22: A buffer layer BF and a patterned semiconductor layer ACT are sequentially formed on the side of the first conductive layer M1 facing away from the substrate 10, as shown in FIG. Figure 16 As shown, the semiconductor layer ACT is a transparent material and includes semiconductor patterns located in different sub-pixels PX. The semiconductor patterns overlap with the orthographic projection of the data line DL on the substrate 10. The semiconductor patterns include a source connection region S, a first conductive region DT1, a second conductive region DT2, a channel region CH, a drain connection region D, and a sixth conductive region DT6, which are arranged and sequentially connected along a first direction f1. The sixth conductive region DT6 constitutes the first pixel electrode EP1 and overlaps with the first common electrode EC1.

[0183] Step 23: forming a patterned first insulating layer GI on the side of the semiconductor layer ACT facing away from the substrate 10, such as Figure 17 As shown, a first via hole H1 and a third via hole H3 are provided on the first insulating layer GI. The first via hole H1 exposes a portion of the data line DL, the source connection area S and the first conductive area DT1 . The third via hole H3 is located in the area of ​​the first common electrode EC1 .

[0184] Step 24: forming a patterned second conductive layer M2 on the side of the first insulating layer GI facing away from the substrate 10, as shown in FIG. Figure 17 As shown, the second conductive layer M2 includes a scan line GL, a gate G, a first transfer pattern ZJ1 and a third transfer pattern ZJ3. The gate G is connected to one side of the scan line GL, and the gate G overlaps with the channel region CH. The first transfer pattern ZJ1 half covers the first via hole H1 and is respectively connected to the data line DL and the source connection region S. The third transfer pattern ZJ3 fully covers the third via hole H3 and is connected to the first common electrode EC1.

[0185] After the second conductive layer M2 is formed, the first insulating layer GI can be etched again using the second conductive layer M2 as a mask, and then the semiconductor material in the exposed regions (such as the first conductorization region DT1, the second conductorization region DT2, the region between the channel region CH and the drain connection region D, and the sixth conductorization region DT6) of the semiconductor layer ACT can be conductorized using a self-alignment process using the second conductive layer M2 as a mask. The conductorization process can use a dry etching device or an ion implantation device to inject plasma (such as plasma containing at least one of helium, oxygen, nitrogen, chlorine, hydrogen, boron, and phosphorus elements) into the semiconductor material, or an ion doping process to dope any one or more of the above elements into the semiconductor material to achieve conductorization. The semiconductor material can be conductorized using a dry etching device simultaneously with the second etching process of the first insulating layer GI, thereby simplifying the process.

[0186] Step 25: A second insulating material is deposited on the side of the second conductive layer M2 away from the substrate 10 to form a second insulating material layer, and then an organic insulating material is coated to form an organic insulating material layer. Then, the organic insulating material layer is patterned to form an organic insulating layer RS, as shown in Figure 18 The organic insulating layer RS is provided with two organic vias, a first organic via RH1 and a second organic via RH2. The first organic via RH1 is located in the region of the third transfer pattern ZJ3, and the first organic via RH1 is arranged along the second direction f2 with the third via H3. The second organic via RH2 is located in the region of the first pixel electrode EP1, such as the region of the second sub-electrode 112.

[0187] Step 26: The second insulating material layer is patterned to form a second insulating layer PVX1, as shown in Figure 19 The second insulating layer PVX1 is provided with two vias, a via PH1 and a via PH2. The via PH1 is arranged in the first organic via RH1, and the via PH2 is arranged in the second organic via RH2.

[0188] Exemplarily, as shown in Figure 20 The via PH1 is arranged in the first organic via RH1, and the via PH2 is arranged in the second organic via RH2. The via PH1 and the via PH2 are arranged along the first direction f1.

[0189] Step 27: A patterned third conductive layer M3 is formed on the side of the organic insulating layer RS away from the substrate 10, as shown in Figure 21As shown, the third conductive layer M3 includes a second common electrode EC2 and a fourth transition pattern ZJ4, which are separated from each other. The second common electrode EC2 covers a via hole RH1 located on the third transition pattern ZJ3, communicating with the third transition pattern ZJ3 and, in turn, with the first common electrode EC1. The fourth transition pattern ZJ4 covers a via hole RH2 located on the first pixel electrode EP1 and communicates with the first pixel electrode EP1.

[0190] Step 28: Form a patterned third insulating layer PVX2 on the side of the third conductive layer M3 facing away from the substrate 10, as shown in FIG. Figure 21 As shown, a via hole H4 is provided on the third insulating layer PVX2 . The via hole H4 is located in the region of the second organic via hole RH2 and is used to expose the fourth transfer pattern ZJ4 .

[0191] Step 29: forming a patterned transparent conductive layer TD on the side of the third insulating layer PVX2 facing away from the substrate 10, as shown in FIG. Figure 21 As shown, the transparent conductive layer TD includes a second pixel electrode EP2 located in a different sub-pixel PX. The second pixel electrode EP2 covers the via hole located on the fourth switching pattern ZJ4 and is connected to the fourth switching pattern ZJ4 and further connected to the first pixel electrode EP1.

[0192] In a third exemplary embodiment, Figure 21 As shown, the display substrate includes: a substrate 10, and a first conductive layer M1, a buffer layer BF, a semiconductor layer ACT, a first insulating layer GI, a second conductive layer M2, a second insulating layer PVX1, an organic insulating layer RS, a third conductive layer M3, a third insulating layer PVX2 and a transparent conductive layer TD stacked in sequence on one side of the substrate 10, and the first conductive layer M1 is arranged close to the substrate 10.

[0193] like Figure 21 As shown, the first conductive layer M1 includes a data line DL, the semiconductor layer ACT includes a semiconductor pattern, the semiconductor pattern includes a source connection area S, a first conductor area DT1, a second conductor area DT2, a channel area CH, a fourth conductor area DT4, a third conductor area DT3, a drain connection area D and a fifth conductor area DT5 (i.e., a first pixel electrode EP1) arranged along a first direction f1 and connected in sequence, the second conductive layer M2 includes a scan line GL, a gate G, a first transfer pattern ZJ1 and a second transfer pattern ZJ2, the third conductive layer M3 includes a common electrode EC, i.e., a first common electrode EC1 and a second common electrode EC2, and the transparent conductive layer TD includes a second pixel electrode EP2.

[0194] like Figures 22 to 29 As shown, the first transfer pattern ZJ1 is connected to the data line DL and the source connection region S through a first via hole H1 half-overlappingly provided on the first insulating layer GI.

[0195] As shown in Figure 22 , the first pixel electrode EP1 is arranged in the same layer as the drain connection region D and is connected to the drain connection region D, and the second pixel electrode EP2 is connected to the drain connection region D through a second transfer pattern ZJ2. Specifically, the second transfer pattern ZJ2 is connected to the drain connection region D through a second via H2 arranged on the first insulating layer GI in a half-lap joint manner, and the second pixel electrode EP2 is connected to the second transfer pattern ZJ2 through a via arranged on the second insulating layer PVX1, the organic insulating layer RS, and the third insulating layer PVX2.

[0196] As shown in Figure 23 , the first common electrode EC1 and the first pixel electrode EP1 constitute two plates of a first storage capacitor Cst1, and the organic insulating layer RS above the first pixel electrode EP1 is removed to thin the dielectric layer between the two plates to the second insulating layer PVX1. The second common electrode EC2 and the second pixel electrode EP2 constitute two plates of a second storage capacitor Cst2, and the dielectric layer between the two plates includes the third insulating layer PVX2.

[0197] Referring to Figure 24 , the display substrate provided by the embodiment can be prepared by the following steps:

[0198] Step 31: forming a patterned first conductive layer M1 on the substrate 10, as shown in Figure 25 , the first conductive layer M1 includes a data line DL and can also include a shielding pattern (not shown in the figure), and the orthographic projection of the shielding pattern on the substrate 10 covers the channel region CH.

[0199] Step 32: sequentially forming a buffer layer BF and a patterned semiconductor layer ACT on the side of the first conductive layer M1 away from the substrate 10, as shown in Figure 26 . The semiconductor layer ACT is a transparent material and includes semiconductor patterns located in different sub-pixels PX, the semiconductor patterns have an overlap with the orthographic projection of the data line DL on the substrate 10, and the semiconductor patterns include a source connection region S, a first conductive region DT1, a second conductive region DT2, a channel region CH, a fourth conductive region DT4, a third conductive region DT3, a drain connection region D, and a fifth conductive region DT5 (i.e., a first pixel electrode EP1) arranged in the first direction f1 and sequentially connected, and the fifth conductive region DT5 constitutes the first pixel electrode EP1 and has an overlap with the first common electrode EC1.

[0200] Step 33: forming a patterned first insulating layer GI on the side of the semiconductor layer ACT away from the substrate 10, as shown in Figure 27As shown, the first insulating layer GI is provided with a first via H1 and a second via H2, the first via H1 and the second via H2 are located on both sides of the channel region CH, the first via H1 exposes a part of the data line DL, the source connection region S and the first conductor region DT1, and the second via H2 exposes the drain connection region D.

[0201] Step 34: forming a patterned second conductive layer M2 on the side of the first insulating layer GI away from the substrate 10, as shown in FIG. 4B. Figure 28 As shown, the second conductive layer M2 includes a scan line GL, a gate G, a first transfer pattern ZJ1 and a second transfer pattern ZJ2, the gate G is connected to one side of the scan line GL, the gate G overlaps the channel region CH, the first transfer pattern ZJ1 half covers the first via H1 and is in communication with the data line DL and the source connection region S respectively, and the second transfer pattern ZJ2 half covers the second via H2 and is in communication with the drain connection region D.

[0202] After the second conductive layer M2 is formed, the first insulating layer GI can be etched again using the second conductive layer M2 as a mask, and then the exposed regions (such as the first conductor region DT1, the second conductor region DT2, the third conductor region DT3, the fourth conductor region DT4 and the fifth conductor region DT5) in the semiconductor layer ACT can be conductive using a self-alignment process, for example, a dry etching device or an ion implantation device can be used to inject plasma (such as plasma containing at least one of helium, oxygen, nitrogen, chlorine, hydrogen, boron, phosphorus elements) into the semiconductor material, or an ion doping process can be used to dope any one or more of the above elements into the semiconductor material to realize the conductive process. Among them, the dry etching device for conductive semiconductor material can be carried out synchronously with the second etching process of the first insulating layer GI, so as to simplify the process.

[0203] Step 35: sequentially depositing a second insulating material on the side of the second conductive layer M2 away from the substrate 10 to form a second insulating material layer, and then coating an organic insulating material to form an organic insulating material layer. Then, the organic insulating material layer is patterned to form an organic insulating layer RS, as shown in FIG. 4D. Figure 29 As shown, the organic insulating layer RS is provided with an opening RH3, and the opening RH3 is used to expose the first pixel electrode EP1 and the second transfer pattern ZJ2 above the first pixel electrode EP1.

[0204] Step 36: forming a patterned third conductive layer M3 on the side of the organic insulating layer RS away from the substrate 10, as shown in FIG. 4E. Figure 31 As shown, the third conductive layer M3 includes a common electrode EC of a first common electrode EC1 and a second common electrode EC2, and the common electrode EC does not overlap the second transfer pattern ZJ2.

[0205] Step 37: a patterned third insulating layer PVX2 is formed on the side of the third conductive layer M3 away from the substrate 10, as shown. Figure 32 As shown, the third insulating layer PVX2 is provided with a via H5, which penetrates the second insulating layer PVX1, for exposing the second transfer pattern ZJ2.

[0206] Step 38: a patterned transparent conductive layer TD is formed on the side of the third insulating layer PVX2 away from the substrate 10, as shown. ​ As shown, the transparent conductive layer TD includes second pixel electrodes EP2 located at different sub-pixels PX, the second pixel electrodes EP2 cover the vias on the second transfer pattern ZJ2 and communicate with the second transfer pattern ZJ2, and further communicate with the first pixel electrodes EP1.

[0207] The present disclosure provides a display device, as shown. ​ The display device includes an opposed substrate 171, an electrophoretic solution 172, and a display substrate 173 provided by any of the embodiments, the electrophoretic solution 172 is located between the opposed substrate 171 and the display substrate 173, and the second conductive layer M2 is located on the side of the substrate 10 close to the electrophoretic solution.

[0208] The electrophoretic solution 172 includes target particles LZ. The target particles can be electrophoretic particles, such as two-color particles, three-color particles, or four-color particles, etc.; or liquid crystal molecules.

[0209] Those skilled in the art can understand that the display device provided by the present disclosure has the advantages of the display substrate 173 described above.

[0210] The display device provided by the present disclosure can be: electronic paper, electronic price tags, electronic badges, display modules, mobile phones, tablet computers, televisions, monitors, notebook computers, digital photo frames, vehicle-mounted display devices, smart watches, fitness wristbands, personal digital assistants, etc. Any product or component with display function.

[0211] Exemplarily, the opposed substrate 171 includes: an opposed substrate 1711, and an opposed electrode 1712 provided on the side of the opposed substrate 1711 close to the electrophoretic solution 172, the opposed electrode 1712 and the pixel electrode EP1 / EP2 together form an electric field for driving the target particles LZ to move.

[0212] Exemplarily, the electrophoretic solution 172 can be an electronic paper film.

[0213] Exemplarily, as shown. ​ The display device can further include a driving chip IC bound to the non-display area NA of the display substrate 173, and the driving chip IC is connected to the driving circuit board 182 through the flexible circuit board 181.

[0214] In the process of displaying a picture, the driving chip IC can be started by the driving circuit board 182, the driving chip IC inputs a scanning signal into the scanning line GL and inputs a data signal into the data line DL, the thin film transistor is turned on, the pixel electrode EP1 / EP2 of the sub-pixel PX obtains the voltage required by the picture, a pressure difference is formed with the upper layer of the counter electrode 1712, the white particles and the black particles in the electrophoretic solution 172 are separated, and different display gray scale states are formed.

[0215] In the present disclosure, the terms "upper", "lower", and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present disclosure.

[0216] In the present disclosure, the relationship terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between the entities or operations.

[0217] In the present specification, "electrically connected" and "coupled" include the case where the constituent elements are connected together through an element having a certain electrical effect. The element having a certain electrical effect is not particularly limited as long as it can perform the transmission and reception of electrical signals between the connected constituent elements. Examples of the element having a certain electrical effect include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, other elements having various functions, and the like.

[0218] In the present disclosure, the meaning of "a plurality of" is two or more, and the meaning of "at least one" is one or more, unless specifically limited otherwise. "At least one of A, B, and C" has the same meaning as "at least one of A, B, or C", and includes the following combinations of A, B, and C: only A, only B, only C, a combination of A and B, a combination of A and C, a combination of B and C, and a combination of A, B, and C. "A and / or B" includes the following three combinations: only A, only B, and a combination of A and B.

[0219] In the present disclosure, the use of "for" or "configured to" means open and inclusive language that does not exclude devices that are adapted to perform additional tasks or steps.

[0220] As used in the present disclosure, "about", "approximately", or "around" includes the stated value and the average value within an acceptable range of deviation from the specific value, as determined by a person of ordinary skill in the art taking into account the measurement being discussed and the error associated with the measurement of the specific quantity (i.e., the limitations of the measurement system).

[0221] As used in the present disclosure, "parallel," "perpendicular," "equal," "flush" include the recited condition and conditions approximating the recited condition within an acceptable deviation range, as determined by one of ordinary skill in the art taking into account the measurement being discussed and the error associated with the particular measurement (i.e., limitations of the measurement system). For example, "parallel" includes absolute parallel and near parallel, where near parallel can have an acceptable deviation range of, for example, 10° or 5° or less; "perpendicular" includes absolute perpendicular and near perpendicular, where near perpendicular can also have an acceptable deviation range of, for example, 10° or 5° or less.

[0222] "Equal" includes absolute equality and near equality, where near equality can have an acceptable deviation range of, for example, less than or equal to 5% of the difference between the two being equal. "Flush" includes absolute flush and near flush, where near flush can have an acceptable deviation range of, for example, less than or equal to 5% of the distance between the two being flush.

[0223] It should be understood that when a layer or element is referred to as being "on" another layer or substrate, it can be directly on the other layer or substrate, or intervening layers can also be present.

[0224] The present disclosure describes example embodiments with reference to cross-sectional and / or plan view illustrations that are schematic illustrations of idealized embodiments. In the drawings, the thickness of layers and regions are exaggerated for clarity. Accordingly, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, the example embodiments should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched region illustrated as a rectangle will typically have rounded or curved features. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the precise shape of a region of a device and are not intended to limit the scope of the example embodiments.

[0225] Finally, it should be noted that the above-mentioned embodiments are merely intended for describing and illustrating, not limiting the technical solutions of the present disclosure; even though the present disclosure has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacements to part of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present disclosure.

Claims

1. A display substrate, comprising a display area and a non-display area surrounding the display area, the display area comprising a plurality of sub-pixels, the sub-pixel comprising a thin film transistor; The display substrate comprises: a substrate, and a first conductive layer, a semiconductor layer, a first insulating layer and a second conductive layer sequentially stacked on one side of the substrate, the first conductive layer being arranged close to the substrate, the first conductive layer comprising a data line, the semiconductor layer comprising a plurality of semiconductor patterns in different sub-pixels, the semiconductor pattern comprising a source connection region, a first conductorization region and a channel region of the thin film transistor, the source connection region, the first conductorization region and the channel region being arranged along a first direction and sequentially connected, the second conductive layer comprising a first transfer pattern, a scan line and a gate of the thin film transistor; wherein the first insulating layer is provided with a first via hole, the first via hole exposing a part of the data line, the source connection region and the first conductorization region, the data line and the source connection region being respectively overlapped with the first transfer pattern through the first via hole, and a projection of the first transfer pattern on the substrate does not overlap with the first conductorization region. 2.The display substrate of claim 1, wherein, The semiconductor pattern further comprises: a second conductorization region connected between the first conductorization region and the channel region, a thickness of the first conductorization region being less than a thickness of the second conductorization region, the thickness of the first conductorization region being less than or equal to a thickness of the source connection region, and the thickness of the second conductorization region being less than or equal to a thickness of the channel region. 3.The display substrate of claim 1, wherein, The semiconductor pattern further comprises: a drain connection region, a third conductorization region and a fourth conductorization region of the thin film transistor, the channel region, the fourth conductorization region, the third conductorization region and the drain connection region being arranged along the first direction and sequentially connected, and a thickness of the third conductorization region being less than a thickness of the fourth conductorization region. The second conductive layer further comprises a second transfer pattern, the second transfer pattern being located on a side of the gate away from the first transfer pattern, the first insulating layer is further provided with a second via hole, the second via hole exposing the drain connection region and the third conductorization region, the second transfer pattern being overlapped with the drain connection region through the second via hole, and a projection of the second transfer pattern on the substrate does not overlap with the third conductorization region. 4.The display substrate of claim 3, wherein, The sub-pixel further comprises a common electrode and a first pixel electrode, a projection of the second transfer pattern on the substrate overlaps with the common electrode, and the second transfer pattern constitutes the first pixel electrode. 5.The display substrate of claim 3, wherein, The sub-pixel further comprises a common electrode and a first pixel electrode, a projection of the second transfer pattern on the substrate does not overlap with the common electrode. The semiconductor pattern further comprises: a fifth conductorization region located on a side of the drain connection region away from the channel region and connected with the drain connection region, a projection of the fifth conductorization region on the substrate overlaps with the common electrode, and the fifth conductorization region constitutes the first pixel electrode. 6.The display substrate according to any one of claims 1 to 5, wherein The sub-pixel further comprises a first common electrode, a first pixel electrode, a second common electrode and a second pixel electrode, the first pixel electrode is located in the semiconductor layer or the second conductive layer, the first common electrode is located in a layer different from the first pixel electrode and has an overlapping area with the first pixel electrode in the orthographic projection on the substrate, and the display substrate further comprises: a third conductive layer located on a side of the second conductive layer away from the substrate and comprising the second common electrode; and a transparent conductive layer located on a side of the third conductive layer away from the substrate and comprising the second pixel electrode, the second pixel electrode and the second common electrode have an overlapping area in the orthographic projection on the substrate, the second pixel electrode is connected to the first pixel electrode through a via, and the first pixel electrode is further connected to the drain connection area of the thin film transistor. 7.The display substrate of claim 6, wherein, The first pixel electrode comprises a plurality of sub-electrodes arranged along a second direction and connected in sequence, the second direction intersects the first direction, and the widths of different sub-electrodes along the first direction are different. 8.The display substrate of claim 7, wherein, In the direction away from the channel area along the second direction, the widths of the plurality of sub-electrodes along the first direction increase in sequence. 9.The display substrate of claim 7, wherein, In the orthographic projection on the substrate, the edges of the plurality of sub-electrodes away from the channel area are substantially aligned. 10.The display substrate of claim 7, wherein, The first common electrode is located in the first conductive layer, and the first common electrode is located between two adjacent data lines. The second conductive layer further comprises a third transfer pattern located on a side of the first transfer pattern and the gate electrode away from the scan line, the second common electrode and the first common electrode are connected to the third transfer pattern through vias, and the third transfer pattern has no overlapping area with the first pixel electrode in the orthographic projection on the substrate. 11.The display substrate of claim 10, wherein, The plurality of sub-electrodes comprise a first sub-electrode, a second sub-electrode and a third sub-electrode connected in sequence, the first sub-electrode is connected to the drain connection area of the thin film transistor and located on a side of the drain connection area away from the channel area. In the orthographic projection on the substrate, the second sub-electrode and the third transfer pattern are arranged along the first direction, the first common electrode has overlapping areas with the second sub-electrode and the third sub-electrode, and the first common electrode has no overlapping area with the first sub-electrode. 12.The display substrate of claim 11, wherein, The third conductive layer further comprises: a fourth transfer pattern, the fourth transfer pattern is arranged separately from the second common electrode, the second sub-electrode and the second pixel electrode are connected to the fourth transfer pattern through vias, and in the orthographic projection on the substrate, the fourth transfer pattern is located in the area of the second sub-electrode. 13.The display substrate of claim 7, wherein, The first common electrode is located in the third conductive layer, and the first common electrode shares the same electrode with the second common electrode. The second conductive layer further comprises a second transfer pattern located on a side of the gate electrode away from the first transfer pattern, and the second transfer pattern is used for connecting the first pixel electrode and the second pixel electrode. In orthographic projection onto the substrate, the same electrode covers the first via pattern and the gate electrode, and has no overlap with the second via pattern. 14.The display substrate of claim 13, wherein, The first pixel electrode is located on the semiconductor layer, the plurality of sub-electrodes include a fourth sub-electrode and a fifth sub-electrode connected in sequence, the fourth sub-electrode is connected with the drain electrode connection region of the thin film transistor, and is located on the side of the drain electrode connection region away from the channel region. In orthographic projection onto the substrate, the second via pattern is located within the range of the fourth sub-electrode, and the same electrode has overlap with the edge of the fourth sub-electrode close to the channel region and the fifth sub-electrode, respectively. 15.The display substrate of claim 13, wherein, The display substrate comprises: a second insulating layer disposed between the second conductive layer and the third conductive layer; and an organic insulating layer disposed between the second insulating layer and the third conductive layer, the orthographic projection of the organic insulating layer and the first pixel electrode on the substrate has at least partial overlap. 16.The display substrate of claim 6, wherein, In orthographic projection onto the substrate, the first pixel electrode and the second pixel electrode have no overlap with the scan line, respectively, the first pixel electrode is located within the region of the second pixel electrode, the gap width between the second pixel electrodes of adjacent two sub-pixels is greater than or equal to 5 microns and less than or equal to 15 microns. 17.The display substrate of claim 6, wherein, In orthographic projection onto the substrate, the first common electrode and the second common electrode have no overlap with the data line, respectively, the second common electrode has an overlapping region with the scan line, and the width of the overlapping region along the first direction is less than the width of the non-overlapping region along the first direction.

18. A display device comprising: The display substrate as claimed in any one of claims 1 to 17, the electrophoretic solution is located between the display substrate and the opposite substrate, and the second conductive layer is located on the side of the substrate close to the electrophoretic solution.

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