Reset control circuit with counter

Abstract

The utility model relates to a reset control circuit with a counter, which comprises a CPU (Central Processing Unit), a first power supply module, a watchdog, the counter and a second power supply module, the CPU outputs a control signal, the first power supply module supplies power to the CPU, the watchdog is in communication connection with the CPU and sends a reset signal to the CPU, the counter is in communication connection with the watchdog and the first power supply module, and the second power supply module supplies power to the second power supply module. The second power supply module supplies power to the counter, the counter is in communication connection with the first power supply module and the watchdog, and when the number of reset times of the watchdog is too large, it is represented that the reset cannot be completed even if a fault occurs. At the moment, the counter sends a power-off signal to the first power supply module, the whole system is closed, and the condition of crash is avoided.

Description

Technical Field

[0001] This application relates to the field of circuit control technology, and in particular to a reset control circuit with a counter. Background Technology

[0002] Most embedded control systems currently have internal or external watchdog circuits in their controllers. These watchdog circuits require the controller to periodically send a "feed" signal; otherwise, the watchdog circuit will reset the controller via a reset signal. This function is used to reset a controller that has crashed, preventing it from remaining in a frozen state for an extended period.

[0003] like Figure 3 As shown, the conventional watchdog reset method is only suitable for resetting controller crashes caused by occasional software errors or occasional external interference. For systems with hardware faults or frequent software errors, this watchdog reset method will result in frequent system resets that repeat continuously in a loop. Continuous and repeated resets can easily cause system crashes or even damage in some system controls, especially in applications with high-power loads; therefore, continuous and repeated system resets should be avoided. Utility Model Content

[0004] In view of this, this application proposes a reset control circuit with a counter to avoid the system from repeatedly resetting.

[0005] According to one aspect of this application, a reset control circuit with a counter is provided, comprising: a CPU that outputs control signals;

[0006] The first power supply module supplies power to the CPU;

[0007] The watchdog timer communicates with the CPU and sends a reset signal to the CPU.

[0008] The counter is communicatively connected to the watchdog timer and the first power module, receives the reset signal from the watchdog timer, and sends a power-off signal to the first power module.

[0009] The second power supply module supplies power to the counter.

[0010] In one possible implementation, the counter is a decimal counter.

[0011] In one possible implementation, pin 9 of the counter is an output pin.

[0012] In one possible implementation, the watchdog timer simultaneously sends a reset signal to both the CPU and the counter;

[0013] When the counter counts to 9, a power-off signal is sent to the first power module.

[0014] In one possible implementation, the counter includes: a U1 chip;

[0015] The control pin of the U1 chip is grounded;

[0016] The reset pin of the U1 chip is grounded.

[0017] In one possible implementation, pin 9 of the U1 chip is electrically connected to a transmission circuit;

[0018] The input terminal of the transmission circuit is electrically connected to pin 9, and the output terminal is electrically connected to the first power module.

[0019] The transmission circuit includes: capacitor C2, resistor R3 and field-effect transistor Q1;

[0020] The capacitor C2 is connected in parallel with the resistor R3, the resistor R3 is connected in series with the gate of the field-effect transistor Q1, and the capacitor C2 is connected in series with pin 9 of the U1 chip, and the drain of the field-effect transistor Q1 is connected in series.

[0021] The beneficial effects of the reset control circuit with counter in this application embodiment are as follows: The reset control circuit with counter allows the watchdog timer to enable the controller to attempt a restart recovery function within a specified number of attempts. After reaching the limit, the system will shut down the controller's power supply, avoiding repeated system resets that could damage the system in some high-power load applications. Alternatively, in some redundant devices, if a control system crashes and still cannot function properly after a limited number of reset attempts, the backup device will take over completely. Specifically, the counter is communicatively connected to both the first power module and the watchdog timer. When the watchdog timer's reset count exceeds a certain limit, indicating a fault that cannot be resolved, the counter will send a power-off signal to the first power module, shutting down the entire system and preventing a system crash.

[0022] Other features and aspects of this application will become clear from the following detailed description of exemplary embodiments with reference to the accompanying drawings. Attached Figure Description

[0023] The accompanying drawings, which are included in and form part of this specification, illustrate exemplary embodiments, features, and aspects of this application together with the specification and serve to explain the principles of this application.

[0024] Figure 1 A schematic diagram of a reset control circuit with a counter according to an embodiment of this application is shown;

[0025] Figure 2 A schematic diagram showing the counter circuit connection according to an embodiment of this application is provided.

[0026] Figure 3 A conventional schematic diagram of a reset control circuit with a counter according to an embodiment of this application is shown. Detailed Implementation

[0027] Various exemplary embodiments, features, and aspects of this application will now be described in detail with reference to the accompanying drawings. The same reference numerals in the drawings denote elements that have the same or similar functions. Although various aspects of the embodiments are shown in the drawings, they are not necessarily drawn to scale unless specifically indicated otherwise.

[0028] It should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", and "circumferential" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this utility model or simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this utility model.

[0029] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this utility model, "a plurality of" means two or more, unless otherwise explicitly specified.

[0030] The term “exemplary” as used herein means “serving as an example, embodiment, or illustration.” Any embodiment illustrated herein as “exemplary” is not necessarily to be construed as superior to or better than other embodiments.

[0031] Furthermore, to better illustrate this application, numerous specific details are provided in the following detailed embodiments. Those skilled in the art should understand that this application can be implemented without certain specific details. In some instances, methods, means, components, and circuits well-known to those skilled in the art have not been described in detail in order to highlight the main points of this application.

[0032] Figure 1 A schematic diagram of the main structure according to an embodiment of this application is shown. Figure 1As shown, the reset control circuit with counter in this embodiment includes: CPU 200, first power module 100, watchdog 300, counter 400, and second power module 500. CPU 200 is responsible for outputting various control signals to drive other components to operate according to predetermined logic. First power module 100 provides power to CPU 200. Watchdog 300 is communicatively connected to CPU 200 and constantly monitors the operating status of CPU 200. Once an abnormality or deadlock is detected in CPU 200, watchdog 300 will immediately send a reset signal to attempt to restore the CPU. To ensure the normal operation of CPU200, counter 400 is communicatively connected to watchdog 300 and the first power module 100. Counter 400 and CPU200 simultaneously receive reset signals sent by watchdog 300, and counter 400 counts according to the frequency or number of reset signals. When the count reaches a preset value, counter 400 sends a power-off signal to the first power module 100 to forcibly shut down the power supply to CPU200, thereby preventing the system from deteriorating further due to continuous abnormalities. The second power module 500 provides power to counter 400 to ensure that it is not affected by the state of the first power module 100.

[0033] In this specific embodiment, the reset control circuit with counter 400 allows watchdog 300 to attempt to restart and restore the controller within a specified number of attempts. After the limit is reached, the system will shut down the controller's power supply, preventing repeated system resets from damaging the system in applications with high-power loads. Alternatively, in redundant equipment, if a control system crashes and still fails to function properly after a limited number of reset attempts, the backup equipment will take over completely. Specifically, counter 400 is communicatively connected to both the first power module 100 and watchdog 300. When the watchdog 300 has attempted too many resets, indicating a fault that cannot be resolved, counter 400 will send a power-off signal to the first power module 100, shutting down the entire system and preventing a crash.

[0034] In one specific embodiment, the counter 400 is a decimal counter 400. When the count reaches 9, the counter 400 will trigger a power-off signal and send it to the first power module 100 to shut down the entire system.

[0035] Furthermore, in this specific embodiment, pin 9 of counter 400 is an output pin used to send a power-off signal to the first power module 100.

[0036] In one specific embodiment, the watchdog 300 simultaneously sends a reset signal to the CPU 200 and the counter 400. The CPU 200 is used for reset, ensuring that when the CPU 200 malfunctions, the counter 400 can synchronously record the number of reset signals. When the count reaches 9 times, the counter 400 will send a power-off signal through its output pin to further protect the system.

[0037] In one specific embodiment, such as Figure 2 As shown, the counter 400 includes a U1 chip. The control pin of the U1 chip is grounded, and the reset pin of the U1 chip is grounded to ensure stable operation and to receive a reset signal from the watchdog 300. Further, in this specific embodiment, pin 9 of the U1 chip is electrically connected to a transmission circuit. The input terminal of the transmission circuit is electrically connected to pin 9, and the output terminal is electrically connected to the first power module 100. The transmission circuit includes a capacitor C2, a resistor R3, and a field-effect transistor Q1. Capacitor C2 and resistor R3 are connected in parallel, resistor R3 is connected in series with the gate of the field-effect transistor Q1, and capacitor C2 is connected in series with pin 9 of the U1 chip, and the drain of the field-effect transistor Q1 is connected in series. Specifically, pin 9 of the U1 chip is connected to the first power module 100 through the transmission circuit, which includes capacitor C2, resistor R3, and the field-effect transistor Q1. When pin 9 of the U1 chip outputs a power-off signal, this signal is transmitted to the gate of the field-effect transistor Q1 through capacitor C2 and resistor R3, turning it on, thereby transmitting the power-off signal to the first power module 100. The drain of the field-effect transistor Q1 is connected in series in the circuit to amplify and transmit signals, ensuring that the power-off signal can be transmitted to the first power supply module 100.

[0038] According to the above embodiment, in this circuit, the CPU200 and watchdog 300 are powered by the first power module 100, and the counter 400 is powered by the second power module 500. The enable of the first power module 100 is controlled by the inverted output of the counter 400. Upon initial power-up, if the counter 400 does not reach the set count value, it defaults to a low-level output, allowing the power module to be enabled and powered normally. After the CPU200 starts, if it outputs a watchdog signal within the watchdog 300's specified watchdog cycle, the watchdog 300 will not output a reset signal, the CPU200 will continue to operate normally, and the counter 400 will not count as there is no input. If the CPU200 freezes for some reason, it will stop outputting the watchdog signal. If the watchdog 300 does not receive the watchdog signal within the specified time, it will output a reset signal to reset the CPU200. Simultaneously, the reset signal is collected and counted by the counter 400. If CPU200 still fails to function properly after a reset (i.e., cannot input the watchdog signal), the watchdog 300 will output a reset signal again in the next reset cycle, resetting CPU200 and incrementing the counter 400. If CPU200 still fails to function properly after multiple resets, it indicates an unrecoverable fault, such as hardware damage or a serious software error. When counter 400 reaches its preset count value, it will output a high level. Inverting this high level outputs to the power module enable pin, shutting down the power supply to CPU200 and watchdog 300, completely shutting down the system. The count value of counter 400 can be configured via hardware. When a decimal counter 400 is selected, with the reset signal input via the CP pin, and the counter 400 output connected to its 9th bit output pin, the counter 400 will output a POWER_OFF# signal when its value reaches 9, shutting down the first power module 100.

[0039] The model of counter 400 can be selected according to the actual situation.

[0040] The various embodiments of this application have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical application, or improvement of the technology in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A reset control circuit with a counter, characterized in that, include: CPU outputs control signals; The first power supply module supplies power to the CPU; The watchdog timer communicates with the CPU and sends a reset signal to the CPU. The counter is communicatively connected to the watchdog timer and the first power module, receives the reset signal from the watchdog timer, and sends a power-off signal to the first power module. The second power supply module supplies power to the counter.

2. The reset control circuit with counter according to claim 1, characterized in that, The counter is a decimal counter.

3. The reset control circuit with counter according to claim 2, characterized in that, Pin 9 of the counter is the output pin.

4. The reset control circuit with counter according to any one of claims 1-3, characterized in that, The watchdog simultaneously sends a reset signal to the CPU and the counter; When the counter counts to 9, a power-off signal is sent to the first power module.

5. The reset control circuit with counter according to any one of claims 1-3, characterized in that, The counter includes: a U1 chip; The control pin of the U1 chip is grounded; The reset pin of the U1 chip is grounded.

6. The reset control circuit with counter according to claim 5, characterized in that, Pin 9 of the U1 chip is electrically connected to a transmission circuit; The input terminal of the transmission circuit is electrically connected to pin 9, and the output terminal is electrically connected to the first power module. The transmission circuit includes: capacitor C2, resistor R3 and field-effect transistor Q1; The capacitor C2 is connected in parallel with the resistor R3, the resistor R3 is connected in series with the gate of the field-effect transistor Q1, and the capacitor C2 is connected in series with pin 9 of the U1 chip, and the drain of the field-effect transistor Q1 is connected in series.

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