Cascode cascade device

Abstract

The embodiment of the utility model discloses a cascode cascade device which is applied to the technical field of semiconductor manufacturing. In a cascode cascade device, a source electrode and a grid electrode of a low-voltage enhanced field effect transistor are respectively used as a source electrode end and a grid electrode end of the cascade device, and a drain electrode of a high-voltage enhanced field effect transistor is used as a drain electrode end of the cascade device, so that a balancing circuit and an adjusting circuit can be integrated on the low-voltage enhanced field effect transistor; and the balancing circuit and the adjusting circuit only relate to the resistor and the diode, and when the resistor and the diode are integrated on the low-voltage enhanced field effect transistor, only one mask needs to be added, so that the process cost is relatively low. And redundant devices do not need to be integrated on the high-voltage field-effect tube in the cascade device, so that the area of the high-voltage field-effect tube is saved, and the overall cost of the cascade device is relatively low.

Description

Technical Field

[0001] This utility model relates to the field of semiconductor manufacturing technology, and in particular to a common source cascade device. Background Technology

[0002] Common-source cascaded gallium nitride devices generally include low-voltage silicon carbide metal-oxide field-effect transistors (Si-MOSFETs) and high-voltage gallium nitride electron mobility transistors (GaN HEMTs). The drain of the high-voltage GaN HEMT is the drain of the cascaded device, the source of the high-voltage GaN HEMT is the source of the cascaded device, and the gate of the low-voltage Si-MOSFET is the gate of the cascaded device. The cascaded device also includes a balancing circuit for balancing leakage current and an adjustment circuit for adjusting the switching speed of the cascaded device.

[0003] In existing cascaded gallium nitride devices using the two electrodes of a high-voltage GaN HEMT as corresponding electrodes of the cascaded device, a large amount of gallium nitride chip area is occupied, leading to an increase in the cost of the cascaded device. Utility Model Content

[0004] This utility model provides a common source cascade device, which reduces the manufacturing cost of common source cascade devices.

[0005] One embodiment of this utility model provides a common-source cascaded device, comprising: a low-voltage enhancement-mode MOSFET and a high-voltage MOSFET, wherein:

[0006] The low-voltage enhancement-mode field-effect transistor includes a gate, a source, a drain, a circuit connection point, a balancing circuit, and an adjustment circuit.

[0007] The gate of the low-voltage enhancement-mode field-effect transistor is the gate terminal of the cascaded device, the source of the low-voltage enhancement-mode field-effect transistor is the source terminal of the cascaded device, and the drain of the high-voltage field-effect transistor is the drain terminal of the cascaded device.

[0008] The source of the high-voltage field-effect transistor is connected to the drain of the low-voltage enhancement-mode field-effect transistor, and the gate of the high-voltage field-effect transistor is connected to the circuit connection point of the low-voltage enhancement-mode field-effect transistor.

[0009] The balancing circuit is provided between the drain and source of the low-voltage enhancement-mode field-effect transistor to balance the leakage current of the low-voltage enhancement-mode field-effect transistor and the high-voltage field-effect transistor.

[0010] An adjustment circuit is provided between the source of the low-voltage enhancement-mode MOSFET and the circuit connection point to adjust the switching speed of the cascaded device.

[0011] As can be seen, in the cascaded device of this embodiment, the source and gate of the low-voltage enhancement-mode MOSFET are used as the source and gate terminals of the cascaded device, respectively, while the drain of the high-voltage enhancement-mode MOSFET is used as the drain terminal. This allows for the integration of balancing and adjustment circuits on the low-voltage enhancement-mode MOSFET. Since the balancing and adjustment circuits only involve resistors and diodes, integrating resistors and diodes on the low-voltage enhancement-mode MOSFET only requires adding a mask, resulting in lower manufacturing costs. Furthermore, the high-voltage MOSFET in the cascaded device does not require the integration of additional components, saving area and thus reducing the overall cost of the cascaded device. Attached Figure Description

[0012] To more clearly illustrate the technical solutions in the embodiments of this utility model or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0013] Figure 1 This is a schematic diagram of the logic structure of a common-source cascade device provided in an embodiment of this utility model;

[0014] Figure 2 This is a circuit diagram of a common-source cascaded device provided in an embodiment of this utility model;

[0015] Figure 3 This is a schematic diagram of the logic structure of another common-source cascade device provided in an embodiment of this utility model;

[0016] Figure 4a This is a schematic diagram of the connection between the resistor and the source of the low-voltage enhancement-mode field-effect transistor in an embodiment of this utility model;

[0017] Figure 4b This is another schematic diagram of the connection between the resistor and the source of the low-voltage enhancement-mode field-effect transistor in this embodiment of the present invention;

[0018] Figure 5 This is a schematic diagram of the connection between the diode and the source of the low-voltage enhancement-mode field-effect transistor in an embodiment of this utility model;

[0019] Figure 6 This is a schematic diagram of the logic structure of another common-source cascade device provided in an embodiment of this utility model;

[0020] Figure 7 This is a schematic diagram of the logic structure of another common-source cascade device provided in this embodiment of the present invention. Detailed Implementation

[0021] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present utility model.

[0022] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification, claims, and accompanying drawings of this utility model are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of the utility model described herein can be implemented, for example, in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0023] This utility model embodiment provides a common-source cascaded device, such as a common-source cascaded enhancement-mode GaN device, the logic structure of which is shown in the figure below. Figure 1 As shown, it includes: a low-voltage enhancement-mode field-effect transistor 10 and a high-voltage field-effect transistor 11, wherein:

[0024] The low-voltage enhancement-mode field-effect transistor includes: gate 110, source 120, drain 130, circuit connection point 140, balancing circuit 12, and adjustment circuit 13.

[0025] The gate 110 of the low-voltage enhancement-mode field-effect transistor 10 is the gate terminal of the cascaded device, the source 120 of the low-voltage enhancement-mode field-effect transistor 10 is the source terminal of the cascaded device, and the drain 131 of the high-voltage field-effect transistor 11 is the drain terminal of the cascaded device.

[0026] The source 121 of the high-voltage field-effect transistor 11 is connected to the drain 130 of the low-voltage enhancement-mode field-effect transistor 10, and the gate 111 of the high-voltage field-effect transistor 11 is connected to the circuit connection point 140 of the low-voltage enhancement-mode field-effect transistor 10.

[0027] A balancing circuit 12 is provided between the drain 130 and the source 120 of the low-voltage enhancement-mode field-effect transistor 10 to balance the leakage current of the low-voltage enhancement-mode field-effect transistor 10 and the high-voltage field-effect transistor 11.

[0028] An adjustment circuit 13 is provided between the source 120 of the low-voltage enhancement-mode MOSFET 10 and the circuit connection point 140 to adjust the switching speed of the cascaded devices.

[0029] Specifically, the aforementioned low-voltage enhancement-mode field-effect transistor 10 can be a low-voltage Si-MOSFET, such as Trench MOS, LDMOS, LV MOS, etc., while the high-voltage field-effect transistor 11 can be a GaN HEMT, etc.

[0030] In specific embodiments, such as Figure 2 As shown, the aforementioned balancing circuit 12 may specifically include a first resistor 112, which balances the leakage current of the high-voltage MOSFET 11 and the low-voltage enhancement-mode MOSFET 10 to pass the long-term high-voltage reverse bias test. The adjustment circuit 13 includes a second resistor 113 and a diode 123 connected in parallel, which reduces the turn-on speed of the cascaded common-source device and ensures fast turn-off.

[0031] In forming the cascaded device of this embodiment, a balancing circuit 12 and an adjustment circuit 13 need to be integrated on the low-voltage enhancement-mode MOSFET 10. The balancing circuit 12 and the adjustment circuit 13 only involve resistors and diodes. Integrating resistors and diodes on the low-voltage enhancement-mode MOSFET 10 only requires adding a mask, resulting in lower process costs. Furthermore, no extra components need to be integrated on the high-voltage MOSFET 11 in the cascaded device, saving area on the high-voltage MOSFET 11 and thus reducing the overall cost of the cascaded device. Specifically:

[0032] (1) When integrating resistors on the low-voltage enhancement-mode field-effect transistor 10, it can be mainly achieved through the following polysilicon deposition, patterning, doping, interconnection and packaging processes, specifically:

[0033] Polysilicon deposition: A polysilicon layer is deposited in a specific area. In this embodiment, a polysilicon layer is deposited in the blank area of ​​the low-voltage enhancement-mode field-effect transistor 10, which is typically achieved by chemical vapor deposition (CVD). The polysilicon layer will be used to form structures such as gates and resistors.

[0034] Patterning: The polysilicon layer is patterned using photolithography and etching techniques to form resistors of a specific shape and size.

[0035] Doping: Depending on the resistivity requirements of the resistor, the polycrystalline silicon layer can be doped through ion implantation or diffusion processes to achieve the required resistance value, thereby forming a polycrystalline silicon resistor.

[0036] Interconnection and packaging: Through the interconnection and packaging process of the metal layer, one end of the first resistor 112 in the balancing circuit 12 is connected to the source 120 of the low-voltage enhancement field-effect transistor 10, and the other end of the first resistor 112 is connected to the drain 130 of the low-voltage enhancement field-effect transistor 10 to achieve interconnection; and one end of the second resistor 113 in the adjustment circuit 13 is connected to the source 120 of the low-voltage enhancement field-effect transistor 10, and the other end of the second resistor 113 is connected to the circuit connection point 140 of the low-voltage enhancement field-effect transistor 10, where the circuit connection point 140 is specifically an independent pad.

[0037] (2) When integrating a diode on a low-voltage enhancement-mode field-effect transistor 10, it can be achieved mainly through the following processes: oxidation, photolithography, diffusion or ion implantation, removal of oxide layer, formation of drift region, and metal interconnection. Specifically:

[0038] Oxidation: An oxide layer is grown on the surface of the low-voltage enhancement field-effect transistor 10, which can act as a mask to prevent impurities from spreading to unwanted areas during subsequent diffusion.

[0039] Photolithography: The PN junction region of a diode is defined on an oxide layer using photolithography technology.

[0040] Diffusion or ion implantation: P-type and N-type semiconductors are formed in a defined region by diffusion or ion implantation, thereby creating a PN junction.

[0041] Oxide layer removal: After the PN junction is formed, the photoresist and oxide layer are removed to expose the PN junction area.

[0042] Formation of drift region: A drift region is formed on one side of the PN junction, which can be achieved by diffusion or ion implantation of impurities with a high doping concentration.

[0043] Metal interconnect: Metal contacts are formed at both ends of the PN junction, such as... Figure 2 As shown, the N-region is connected to the source 120 of the low-voltage enhancement-mode MOSFET 10, and the P-region is connected to the circuit connection point 140 of the aforementioned polysilicon resistor, i.e., an independent pad. This achieves the connection of the N-region of diode 123 in the adjustment circuit 13 to the source 120 of the low-voltage enhancement-mode MOSFET 10, and the connection of the P-region of diode 123 to the circuit connection point 140 of the low-voltage enhancement-mode MOSFET 10.

[0044] As can be seen, in the cascaded device of this embodiment, the source and gate of the low-voltage enhancement-mode MOSFET are used as the source and gate terminals of the cascaded device, respectively, while the drain of the high-voltage enhancement-mode MOSFET is used as the drain terminal. This allows for the integration of balancing and adjustment circuits on the low-voltage enhancement-mode MOSFET. Since the balancing and adjustment circuits only involve resistors and diodes, integrating resistors and diodes on the low-voltage enhancement-mode MOSFET only requires adding a mask, resulting in lower manufacturing costs. Furthermore, the high-voltage MOSFET in the cascaded device does not require the integration of additional components, saving area and thus reducing the overall cost of the cascaded device.

[0045] Another embodiment of this utility model provides a common-source cascaded device, such as a common-source cascaded enhancement-mode GaN device, the logic structure of which is shown in the figure below. Figure 3 As shown, it includes: a gate copper interface 20, a source copper interface 21, a drain copper interface 22, and a main structure 23, wherein:

[0046] The gate copper interface 20 serves as the gate terminal of the cascaded device, the source copper interface 21 serves as the source terminal of the cascaded device, and the drain copper interface 22 serves as the drain terminal of the cascaded device.

[0047] The main structure 23 includes a main frame 231, which is a metal frame connected to the source copper interface 21. The main frame 231 has a high-voltage MOSFET region and a low-voltage enhancement-mode MOSFET region. The high-voltage MOSFET region includes a high-voltage MOSFET 2311, and the low-voltage enhancement-mode MOSFET region includes a low-voltage enhancement-mode MOSFET 2312. A balance circuit 2313 and an adjustment circuit 2314 are disposed on the low-voltage enhancement-mode MOSFET 2312. Wherein:

[0048] The drain D of the high-voltage MOSFET 2311 is connected to the drain copper interface 22 via a connecting wire. The source S2 of the high-voltage MOSFET 2311 is connected to the drain D1 of the low-voltage enhancement-mode MOSFET 2312 via a connecting wire. The gate G of the high-voltage MOSFET 2311 is connected to the circuit connection point G2 of the low-voltage enhancement-mode MOSFET 2312 via a connecting wire. The connecting wires can be gold, silver, copper, or various alloy wires.

[0049] The gate G of the low-voltage enhancement-mode field-effect transistor 2312 is connected to the gate copper interface 20 via a connecting line, and the source S of the low-voltage enhancement-mode field-effect transistor 2312 is connected to the source copper interface 21. A balancing circuit 2313 is provided between the drain D1 and the source S of the low-voltage enhancement-mode field-effect transistor 2312, and an adjustment circuit 2314 is provided between the source S of the low-voltage enhancement-mode field-effect transistor 2312 and the circuit connection point G2.

[0050] It should be noted that the high-voltage MOSFET region and the low-voltage enhancement-mode MOSFET region mentioned above can be set separately and independently in the main frame 23, which facilitates the setting of the high-voltage MOSFET 2311 and the low-voltage enhancement-mode MOSFET 2312.

[0051] Furthermore, since the source S, gate G, and drain D1 of the low-voltage enhancement-mode field-effect transistor 2312 can be arranged in various ways, the arrangement of the low-voltage enhancement-mode field-effect transistor 2312 on the main frame 231 can also be arranged in various ways. Specifically, in this embodiment, the arrangement of the low-voltage enhancement-mode field-effect transistor 2312 on the main frame 231 mainly adopts the following method: In the low-voltage enhancement-mode field-effect transistor region, the main frame 231 is arranged from bottom to top as follows: an insulating ceramic pad 2316 with a copper-clad area 2315 and a low-voltage enhancement-mode field-effect transistor 2312 on the copper-clad area 2315. The source S, gate G, and circuit connection point G2 of the low-voltage enhancement-mode field-effect transistor 2312 are arranged at the top, while the drain D1 of the low-voltage enhancement-mode field-effect transistor 2312 is arranged at the bottom, and the source S of the low-voltage enhancement-mode field-effect transistor 2312 is connected to the main frame 231 through a connecting line.

[0052] In this case, the drain D1 located at the bottom of the low-voltage enhancement-mode MOSFET 2312 is connected to the copper-clad region 2315, and the copper-clad region 2315 is equivalent to the drain D1 of the low-voltage enhancement-mode MOSFET 2312.

[0053] Furthermore, in a specific embodiment, the aforementioned balancing circuit 2313 may include a first resistor, and the adjustment circuit 2314 includes a second resistor and a diode connected in parallel. Both the first and second resistors can be polysilicon resistors, and the diode can be a polysilicon diode, etc. Specifically, the first resistor, the second resistor, and the diode are all positioned on top of the low-voltage enhancement-mode MOSFET 2312.

[0054] One end of the first resistor is connected to the source S of the low-voltage enhancement-mode MOSFET 2312 via a connecting wire or metal interconnect wiring, and the other end of the first resistor is connected to the copper-clad area 2315 on the insulating ceramic pad 2316 via a connecting wire or metal interconnect wiring. Here, metal interconnect wiring refers to the metal traces inside the device.

[0055] It should be noted that when connecting the first resistor, one end of the first resistor can be connected to the source S of the low-voltage enhancement-mode MOSFET 2312 via a connecting wire or metal interconnect wiring, and the other end of the first resistor can be connected as described above. Figure 4a As shown, it is connected to the drain D1 of the low-voltage enhancement-mode MOSFET 2312 through a metal via, or, as described above. Figure 4bThe other end of the first resistor is connected to the copper-clad region 2315 via a connecting line or metal interconnect. The metal via penetrates the substrate of the low-voltage enhancement-mode field-effect transistor 2312 and reaches the drain D1 of the low-voltage enhancement-mode field-effect transistor 2312. Further, one end of the second resistor is connected to the source S of the low-voltage enhancement-mode field-effect transistor 2312 via a connecting line or metal interconnect, and the other end of the second resistor is connected to the circuit connection point G2 of the low-voltage enhancement-mode field-effect transistor 2312 via a connecting line or metal interconnect; as shown... Figure 5 As shown, the N-region of the diode is connected to the source S of the low-voltage enhancement-mode MOSFET 2312 via a connecting line, while the P-region of the diode is connected to the circuit connection point G2 of the low-voltage enhancement-mode MOSFET 2312 via a connecting line or metal interconnect wiring, i.e., an independent Pad.

[0056] Another embodiment of this utility model provides a common-source cascaded device, such as a common-source cascaded enhancement-mode GaN device, the logic structure of which is shown in the figure below. Figure 6 As shown, the cascaded device in this embodiment is similar to the one described above. Figure 3 The cascaded devices shown are similar, except that the low-voltage enhancement-mode MOSFET 3312 is arranged in a different manner on the main frame 331. Specifically, it includes: a gate copper interface 30, a source copper interface 31, a drain copper interface 32, and a main structure 33, wherein:

[0057] The gate copper interface 30 serves as the gate terminal of the cascaded device, the source copper interface 31 serves as the source terminal of the cascaded device, and the drain copper interface 32 serves as the drain terminal of the cascaded device.

[0058] The main structure 33 includes a main frame 331, which is a metal frame connected to the source copper interface 31. The main frame 331 has a high-voltage field-effect transistor (FET) region and a low-voltage enhancement-mode field-effect transistor (EMT) region. The high-voltage FET region includes a high-voltage FET 3311, and the low-voltage EMT region includes a low-voltage EMT 3312. A balance circuit 3313 and an adjustment circuit 3314 are disposed on the low-voltage EMT 3312. Wherein:

[0059] The drain D of the high-voltage field-effect transistor 3311 is connected to the drain copper interface 32 via a connecting wire. The source S2 of the high-voltage field-effect transistor 3311 is connected to the drain D1 of the low-voltage enhancement-mode field-effect transistor 3312 via a connecting wire. The gate G of the high-voltage field-effect transistor 3311 is connected to the circuit connection point G2 of the low-voltage enhancement-mode field-effect transistor 3312 via a connecting wire.

[0060] The gate G of the low-voltage enhancement-mode field-effect transistor 3312 is connected to the gate copper interface 30 via a connecting line, and the source S of the low-voltage enhancement-mode field-effect transistor 3312 is connected to the source copper interface 31. A balancing circuit 3313 is provided between the drain D1 and the source S of the low-voltage enhancement-mode field-effect transistor 3312, and an adjustment circuit 3314 is provided between the source S of the low-voltage enhancement-mode field-effect transistor 3312 and the circuit connection point G2.

[0061] Specifically, in this embodiment, the low-voltage enhancement-mode field-effect transistor 3312 is arranged on the main frame 331 in the following manner: In the low-voltage enhancement-mode field-effect transistor region, the low-voltage enhancement-mode field-effect transistor 3312 can be directly arranged on the main frame 331, wherein the drain S, gate D1 and circuit connection point G2 of the low-voltage enhancement-mode field-effect transistor 3312 are arranged at the top, while the source S of the low-voltage enhancement-mode field-effect transistor 3312 is arranged at the bottom.

[0062] In this case, the source S of the low-voltage enhancement-mode field-effect transistor 3312 located at the bottom is directly connected to the main frame 331, and the main frame 331 is equivalent to the source S of the low-voltage enhancement-mode field-effect transistor 3312.

[0063] Further, in this embodiment, the balancing circuit 3313 may include a first resistor, and the adjustment circuit 3314 includes a second resistor and a diode connected in parallel. The first resistor, the second resistor, and the diode are all disposed on top of the low-voltage enhancement-mode MOSFET 3312. Specifically:

[0064] When setting the first resistor, one end of the first resistor can be connected to the drain D1 of the low-voltage enhancement-mode field-effect transistor 3312 via a connecting wire or metal interconnect wiring, and the other end of the first resistor can be connected to the source S of the low-voltage enhancement-mode field-effect transistor 3312 via a metal via, or the other end of the first resistor can be connected to the main frame 331 via a connecting wire or metal interconnect wiring. The metal via is a metal that penetrates the substrate of the low-voltage enhancement-mode field-effect transistor 3312 and reaches the source S of the low-voltage enhancement-mode field-effect transistor 3312. When setting the second resistor, one end of the second resistor can be connected to the circuit connection point G2 of the low-voltage enhancement-mode field-effect transistor 3312 via a connecting wire or metal interconnect wiring, and the other end of the second resistor can be connected to the source S of the low-voltage enhancement-mode field-effect transistor 3312 via a metal via, or the other end of the second resistor can be connected to the main frame 331 via a connecting wire or metal interconnect wiring.

[0065] When setting up the diode, the P-region of the diode can be connected to the circuit connection point G2 of the low-voltage enhancement-mode field-effect transistor 3312 through a connecting line or metal interconnect wiring, and the N-region of the diode can be connected to the source S of the low-voltage enhancement-mode field-effect transistor 3312 through a metal via, or the N-region of the diode can be connected to the main frame 331 through a connecting line or metal interconnect wiring.

[0066] Compared to Figure 3 The cascaded device shown in this embodiment has a simpler structure, does not require additional insulating ceramic gaskets, and the connection line between the low-voltage enhancement-mode MOSFET and the high-voltage MOSFET is easier to set because there is no height difference.

[0067] Another embodiment of this utility model provides a common-source cascaded device, such as a common-source cascaded enhancement-mode GaN device, the logic structure of which is shown in the figure below. Figure 7 As shown, the cascaded device in this embodiment is similar to the one described above. Figure 3 and Figure 6 The cascaded devices shown are similar, except that the low-voltage enhancement-mode MOSFET 4312 is arranged in a different manner on the main frame 431. Specifically, it includes: a gate copper interface 40, a source copper interface 41, a drain copper interface 42, and a main structure 43, wherein:

[0068] The gate copper interface 40 serves as the gate terminal of the cascaded device, the source copper interface 41 serves as the source terminal of the cascaded device, and the drain copper interface 42 serves as the drain terminal of the cascaded device.

[0069] The main structure 43 includes a main frame 431, which is a metal frame connected to the source copper interface 41. The main frame 431 has a high-voltage field-effect transistor (FET) region and a low-voltage enhancement-mode field-effect transistor (EMT) region. The high-voltage FET region includes a high-voltage FET 4311, and the low-voltage EMT region includes a low-voltage EMT 4312. A balance circuit 4313 and an adjustment circuit 4314 are disposed on the low-voltage EMT 4312. Wherein:

[0070] The drain D of the high-voltage field-effect transistor 4311 is connected to the drain copper interface 42 via a connecting wire. The source S2 of the high-voltage field-effect transistor 4311 is connected to the drain D1 of the low-voltage enhancement-mode field-effect transistor 4312 via a connecting wire. The gate G of the high-voltage field-effect transistor 4311 is connected to the circuit connection point G2 of the low-voltage enhancement-mode field-effect transistor 4312 via a connecting wire.

[0071] The gate G of the low-voltage enhancement-mode field-effect transistor 4312 is connected to the gate copper interface 40 via a connecting line. The source S1 of the low-voltage enhancement-mode field-effect transistor 4312 is connected to the source copper interface 41. A balancing circuit 4313 is provided between the drain D1 and the source S1 of the low-voltage enhancement-mode field-effect transistor 4312. An adjustment circuit 4314 is provided between the source S1 and the circuit connection point G2 of the low-voltage enhancement-mode field-effect transistor 4312.

[0072] Specifically, in this embodiment, the low-voltage enhancement-mode field-effect transistor 4312 is arranged on the main frame 431 in the following way: In the low-voltage enhancement-mode field-effect transistor region, the low-voltage enhancement-mode field-effect transistor 4312 can be directly arranged on the main frame 431, wherein the source S1, drain D1, gate G and circuit connection point G2 of the low-voltage enhancement-mode field-effect transistor 4312 are all arranged at the top, and the source S1 of the low-voltage enhancement-mode field-effect transistor 4312 is connected to the main frame 431 through a connecting line.

[0073] In this configuration, since the source S1 of the low-voltage enhancement-mode MOSFET 4312 is connected to the main frame 431 via a connecting line, the main frame 431 is equivalent to the source S1 of the low-voltage enhancement-mode MOSFET 4312. In a practical implementation, an adjustment circuit 4314 can be provided between the circuit connection point G2 of the low-voltage enhancement-mode MOSFET 4312 and the main frame 431, thereby realizing the provision of the adjustment circuit 4314 between the circuit connection point G2 and the source S1 of the low-voltage enhancement-mode MOSFET 4312. A balancing circuit 4313 can be provided between the drain D1 of the low-voltage enhancement-mode MOSFET 4312 and the main frame 431, thereby realizing the provision of the balancing circuit 4313 between the drain D1 and the source S1 of the low-voltage enhancement-mode MOSFET 4312.

[0074] In another specific implementation, the balancing circuit 4313 may include a first resistor, and the adjusting circuit 4314 may include a second resistor and a diode connected in parallel, wherein the first resistor, the second resistor, and the diode are all positioned on top of the low-voltage enhancement-mode MOSFET 4312. Thus:

[0075] One end of the first resistor can be connected to the drain D1 of the low-voltage enhancement-mode MOSFET 4312 via a connecting wire or metal interconnect, and the other end of the first resistor can be connected to the source S1 of the low-voltage enhancement-mode MOSFET 4312 via a connecting wire or metal interconnect; one end of the second resistor can be connected to the source S1 of the low-voltage enhancement-mode MOSFET 4312 via a connecting wire or metal interconnect, and the other end of the second resistor can be connected to the circuit connection point G2 of the low-voltage enhancement-mode MOSFET 4312 via a connecting wire or metal interconnect; the N-region of the diode is connected to the source S1 of the low-voltage enhancement-mode MOSFET 4312 via a connecting wire or metal interconnect, and the P-region of the diode is connected to the circuit connection point G2 of the low-voltage enhancement-mode MOSFET 4312 via a connecting wire or metal interconnect.

[0076] Compared to Figure 6 The cascaded device shown in this embodiment has its source, drain, and gate all located on the same surface, further simplifying the internal wiring.

[0077] In this cascaded common-source cascode device, the source and gate of the low-voltage enhancement-mode MOSFET are used as the source and gate terminals of the cascaded device, respectively, while the drain of the high-voltage enhancement-mode MOSFET is used as the drain terminal. This allows for the integration of balancing and adjustment circuits on the low-voltage enhancement-mode MOSFET. Since these circuits only involve resistors and diodes, integrating them on the low-voltage enhancement-mode MOSFET requires only an additional photomask, resulting in lower manufacturing costs. Furthermore, the high-voltage MOSFET does not require additional components, saving area and thus reducing the overall cost of the cascaded device.

[0078] The foregoing has provided a detailed description of a common-source cascade device provided by the embodiments of this utility model. Specific examples have been used to illustrate the principle and implementation of this utility model. The description of the above embodiments is only for the purpose of helping to understand the method and core idea of ​​this utility model. At the same time, for those skilled in the art, there will be changes in the specific implementation and application scope based on the idea of ​​this utility model. Therefore, the content of this specification should not be construed as a limitation of this utility model.

Claims

1. A common-source, common-gate cascaded device, characterized in that, include: Low-voltage enhancement-mode MOSFETs and high-voltage MOSFETs, among which: The low-voltage enhancement-mode field-effect transistor includes a gate, a source, a drain, a circuit connection point, a balancing circuit, and an adjustment circuit. The gate of the low-voltage enhancement-mode field-effect transistor is the gate terminal of the cascaded device, the source of the low-voltage enhancement-mode field-effect transistor is the source terminal of the cascaded device, and the drain of the high-voltage field-effect transistor is the drain terminal of the cascaded device. The source of the high-voltage field-effect transistor is connected to the drain of the low-voltage enhancement-mode field-effect transistor, and the gate of the high-voltage field-effect transistor is connected to the circuit connection point of the low-voltage enhancement-mode field-effect transistor. The balancing circuit is provided between the drain and source of the low-voltage enhancement-mode field-effect transistor to balance the leakage current of the low-voltage enhancement-mode field-effect transistor and the high-voltage field-effect transistor. An adjustment circuit is provided between the source of the low-voltage enhancement-mode MOSFET and the circuit connection point to adjust the switching speed of the cascaded device.

2. The cascaded device as described in claim 1, characterized in that, The balancing circuit includes a first resistor, and the adjusting circuit includes a second resistor and a diode connected in parallel, wherein: One end of the first resistor is connected to the source of the low-voltage enhancement-mode field-effect transistor, and the other end of the first resistor is connected to the drain of the low-voltage enhancement-mode field-effect transistor. One end of the second resistor is connected to the source of the low-voltage enhancement-mode field-effect transistor, and the other end of the second resistor is connected to the circuit connection point of the low-voltage enhancement-mode field-effect transistor. The N-region of the diode is connected to the source of the low-voltage enhancement-mode field-effect transistor, and the P-region of the diode is connected to the circuit connection point of the low-voltage enhancement-mode field-effect transistor.

3. The common-source, common-gate cascaded device according to claim 1, characterized in that, The common-source, common-gate cascaded device further includes: The drain copper interface serves as the drain terminal of cascaded devices; A gate copper interface serves as the gate terminal of the cascaded device; The source copper interface serves as the source terminal of the cascaded device; The main structure includes a main frame connected to the source copper interface, and the main frame is provided with a high voltage field-effect transistor region and a low voltage enhancement-mode field-effect transistor region. The high voltage field-effect transistor region includes a high voltage field-effect transistor, the low voltage enhancement-mode field-effect transistor region includes a low voltage enhancement-mode field-effect transistor, and a balance circuit and an adjustment circuit disposed on the low voltage enhancement-mode field-effect transistor. The drain of the high-voltage field-effect transistor is connected to the drain copper interface via a connecting line, the source of the high-voltage field-effect transistor is connected to the drain of the low-voltage enhancement-mode field-effect transistor via a connecting line, and the gate of the high-voltage field-effect transistor is connected to the circuit connection point of the low-voltage enhancement-mode field-effect transistor via a connecting line. The gate of the low-voltage enhancement-mode field-effect transistor is connected to the gate copper interface via a connecting line, the source of the low-voltage enhancement-mode field-effect transistor is connected to the source copper interface, the balancing circuit is provided between the drain and source of the low-voltage enhancement-mode field-effect transistor, and the adjustment circuit is provided between the source of the low-voltage enhancement-mode field-effect transistor and the circuit connection point.

4. The cascaded device as described in claim 3, characterized in that, In the low-voltage enhancement-mode field-effect transistor (LVFET) region, the main frame is provided with, from bottom to top, an insulating ceramic pad with a copper-clad area and a LVFET on the copper-clad area, wherein the source, gate, and circuit connection point of the LVFET are located at the top, and the drain of the LVFET is located at the bottom. The source of the low-voltage enhancement-mode MOSFET is connected to the main frame via a connecting wire.

5. The cascaded device as described in claim 4, characterized in that, The balancing circuit includes a first resistor, which is disposed on top of the low-voltage enhancement-mode MOSFET. Then: One end of the first resistor is connected to the source of the low-voltage enhancement-mode field-effect transistor via a connecting line or metal interconnect wiring, and the other end of the first resistor is connected to the drain of the low-voltage enhancement-mode field-effect transistor via a metal via, or the other end of the first resistor is connected to the copper-clad area via a connecting line or metal interconnect wiring. The metal via is a metal that penetrates the substrate of the low-voltage enhancement-mode field-effect transistor and reaches the drain of the low-voltage enhancement-mode field-effect transistor.

6. The cascaded device as described in claim 4, characterized in that, The adjustment circuit includes a second resistor and a diode, both of which are positioned on top of the low-voltage enhancement-mode MOSFET. One end of the second resistor is connected to the source of the low-voltage enhancement-mode field-effect transistor via a connecting wire or metal interconnect wiring, and the other end of the second resistor is connected to the circuit connection point of the low-voltage enhancement-mode field-effect transistor via a connecting wire or metal interconnect wiring. One end of the N-region of the diode is connected to the source of the low-voltage enhancement-mode field-effect transistor via a connecting line or metal interconnect wiring, and one end of the P-region of the diode is connected to the circuit connection point of the low-voltage enhancement-mode field-effect transistor via a connecting line or metal interconnect wiring.

7. The cascaded device as described in claim 3, characterized in that, In the low-voltage enhancement-mode field-effect transistor (LVFET) region, the LVFET is disposed on the main frame, wherein the drain, gate, and circuit connection point of the LVFET are disposed at the top, and the source of the LVFET is disposed at the bottom.

8. The cascaded device as described in claim 7, characterized in that, The balancing circuit includes a first resistor, and the adjusting circuit includes a second resistor and a diode. The first resistor, the second resistor, and the diode are all positioned on top of the low-voltage enhancement-mode MOSFET. Then: One end of the first resistor is connected to the drain of the low-voltage enhancement-mode field-effect transistor (LVFET) via a connecting wire or metal interconnect wiring, and the other end of the first resistor is connected to the source of the LVFET via a metal via, or the other end of the first resistor is connected to the main frame via a connecting wire or metal interconnect wiring; wherein, the metal via is a metal that penetrates the substrate in the LVFET and reaches the source of the LVFET; One end of the second resistor is connected to the circuit connection point of the low-voltage enhancement-mode field-effect transistor via a connecting line or metal interconnect wiring, and the other end of the second resistor is connected to the source of the low-voltage enhancement-mode field-effect transistor via a metal via, or the other end of the second resistor is connected to the main frame via a connecting line or metal interconnect wiring. The P-region of the diode is connected to the circuit connection point of the low-voltage enhancement-mode MOSFET via a connecting line or metal interconnect wiring, and the N-region of the diode is connected to the source of the low-voltage enhancement-mode MOSFET via a metal via, or the N-region of the diode is connected to the main frame via a connecting line or metal interconnect wiring.

9. The cascaded device as described in claim 3, characterized in that, In the low-voltage enhancement-mode field-effect transistor (LVFET) region, the LVFET is disposed on the main frame, wherein the source, drain, gate, and circuit connection point of the LVFET are all disposed at the top, and the source of the LVFET is connected to the main frame through a connecting line or metal interconnect wiring.

10. The cascaded device as described in claim 9, characterized in that, The balancing circuit includes a first resistor, and the adjusting circuit includes a second resistor and a diode. The first resistor, the second resistor, and the diode are all positioned on top of the low-voltage enhancement-mode MOSFET. Then: One end of the first resistor is connected to the source of the low-voltage enhancement-mode field-effect transistor via a connecting line or metal interconnect wiring, and the other end of the first resistor is connected to the drain of the low-voltage enhancement-mode field-effect transistor via a connecting line or metal interconnect wiring. One end of the second resistor is connected to the source of the low-voltage enhancement-mode field-effect transistor via a connecting line or metal interconnect wiring, and the other end of the second resistor is connected to the circuit connection point of the low-voltage enhancement-mode field-effect transistor via a connecting line or metal interconnect wiring. One end of the N-region of the diode is connected to the source of the low-voltage enhancement-mode field-effect transistor via a connecting line or metal interconnect wiring, and one end of the P-region of the diode is connected to the circuit connection point of the low-voltage enhancement-mode field-effect transistor via a connecting line or metal interconnect wiring.

Images