Latch circuit, RS trigger, motor control circuit and vehicle
By designing the power-on timing of the first input circuit to lag behind that of the second input circuit in the latching circuit, the problem of power-on competition hazards in RS flip-flops is solved, enabling accurate capture and latching of sensitive fault signals and ensuring the normal operation of the motor control circuit.
Patent Information
- Application Number
- CN202422633615.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-29
- Publication Date
- 2025-11-07
- Estimated Expiration
- 2034-10-29
AI Technical Summary
In vehicle motor control circuits, RS flip-flops are prone to being falsely triggered during power-on due to timing issues related to power-on race conditions, which can affect the capture and latching of sensitive fault signals.
Design a latching circuit in which the power-on timing of the first input circuit lags behind that of the second input circuit. By configuring the RC value and power supply timing, ensure that the latching circuit avoids false triggering during power-on and achieves accurate capture and latching of sensitive fault signals.
It effectively eliminates the timing problems of power-on competition hazards, ensures that the latching circuit captures and latches real sensitive fault signals, and guarantees the normal operation of the motor control circuit.
Smart Images
Figure CN223528052U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of electronic circuits, and in particular to a latch circuit, an RS flip-flop, a motor control circuit and a vehicle. BACKGROUND
[0002] At present, for some sensitive fault signals (such as overcurrent, overvoltage and the like) in the motor control circuit of a vehicle, it is hoped that the RS flip-flop (reset / set flip-flop) can be latched as soon as the sensitive fault signals occur, and the latching can be cleared only by resetting the RS flip-flop, so as to prevent the sensitive fault signals from recovering and affecting the normal operation of the subsequent circuit. In the related art, the RS flip-flop and the peripheral circuit outside the RS flip-flop need to be powered on before the motor control circuit is operated. During the power-on process of the RS flip-flop and the peripheral circuit outside the RS flip-flop, the RS flip-flop is easily mis-triggered to be latched due to the timing problem of power-on race, thereby affecting the capture and latching of the RS flip-flop on the real sensitive fault signals after the RS flip-flop and the peripheral circuit outside the RS flip-flop are powered on. SUMMARY
[0003] Therefore, it is necessary to provide a latch circuit, an RS flip-flop, a motor control circuit and a vehicle to solve the timing problem of power-on race of the RS flip-flop and to ensure the capture and latching of the RS flip-flop on the real sensitive fault signals.
[0004] In a first aspect, an embodiment of the present application provides a latch circuit, comprising a first logic circuit, a second logic circuit, a first input circuit and a second input circuit; two input ends of the first logic circuit are connected with an output end of the second logic circuit and the first input circuit respectively, two input ends of the second logic circuit are connected with an output end of the first logic circuit and the second input circuit respectively; a level of an output end of the second logic circuit is opposite to a level of an output end of the first logic circuit.
[0005] In the power-on process of the latch circuit, a timing of the first input circuit being powered on to a target level is later than a timing of the second input circuit being powered on to the target level.
[0006] In one of the embodiments, the first input circuit comprises a first power-on timing unit and a first power supply; the first power-on timing unit is connected with the first power supply.
[0007] The peripheral circuit outside the latch circuit comprises a second power-on timing unit, and the second input circuit is connected with the second power-on timing unit.
[0008] In the power-on process of the latch circuit, a timing of the first input circuit being powered on to a target level is later than a timing of the second input circuit being powered on to the target level.
[0009] In one embodiment, the first power-on timing unit comprises a first resistance unit and a first capacitance unit;
[0010] The first end of the first resistance unit is connected to the first power supply, and the second end of the first resistance unit is connected to an input end of the first logic circuit;
[0011] The first end of the first capacitance unit is grounded, and the second end of the first capacitance unit is connected to the second end of the first resistance unit;
[0012] The RC value corresponding to the first input circuit is greater than the RC value corresponding to the second input circuit accessed by the peripheral circuit outside the latch circuit, and the RC value represents the product of the resistance value of the resistance unit and the capacitance value of the capacitance unit.
[0013] In one embodiment, the first resistance unit comprises a first resistor, and the first capacitance unit comprises a first capacitor;
[0014] The first end of the first resistor is connected to the first power supply, and the second end of the first resistor is connected to an input end of the first logic circuit;
[0015] The first end of the first capacitor is grounded, and the second end of the first capacitor is connected to the second end of the first resistor.
[0016] In one embodiment, the first input circuit comprises a second resistance unit and a second power supply;
[0017] The first end of the second resistance unit is connected to the second power supply, and the second end of the second resistance unit is connected to an input end of the first logic circuit;
[0018] The power-on timing of the second power supply lags behind the power-on timing of the power supply of the second input circuit.
[0019] In one embodiment, the second resistance unit comprises a second resistor;
[0020] The first end of the second resistor is connected to the second power supply, and the second end of the second resistor is connected to an input end of the first logic circuit.
[0021] In one embodiment, the first input circuit comprises a third resistance unit;
[0022] The first end of the third resistance unit is grounded, and the second end of the third resistance unit is connected to an input end of the first logic circuit;
[0023] The second end of the third resistance unit is further connected with a peripheral circuit outside the latch circuit, and in the case that the second input circuit is powered to the target level, the second end of the third resistance unit receives a pull-up signal output by the peripheral circuit and powered to the target level.
[0024] In one of the embodiments, the third resistance unit comprises a third resistance.
[0025] The first end of the third resistance is grounded, and the second end of the third resistance is connected with an input end of the first logic circuit.
[0026] In one of the embodiments, the first logic circuit comprises a first AND gate and a first inverter.
[0027] Two input ends of the first AND gate are respectively connected with an output end of the second logic circuit and the first input circuit, and an output end of the first AND gate is connected with an input end of the first inverter.
[0028] In one of the embodiments, the second logic circuit comprises a second AND gate and a second inverter.
[0029] Two input ends of the second AND gate are respectively connected with an output end of the first logic circuit and the second input circuit, and an output end of the second AND gate is connected with an input end of the second inverter.
[0030] In the second aspect, the embodiments of the present application further provide an RS flip-flop comprising the latch circuit of the first aspect.
[0031] In the third aspect, the embodiments of the present application further provide a motor control circuit comprising a peripheral circuit and the RS flip-flop of the second aspect, and the peripheral circuit at least comprises a third power supply, a fourth resistance unit and a second capacitance unit; wherein a first end of the fourth resistance unit is connected with the third power supply, a second end of the fourth resistance unit is connected with the second input circuit, a first end of the second capacitance unit is connected with the second input circuit, and a second end of the second capacitance unit is grounded.
[0032] In the fourth aspect, the embodiments of the present application further provide a vehicle comprising a motor and the motor control circuit of the third aspect, and the motor is connected with the motor control circuit.
[0033] The aforementioned latch circuit, RS flip-flop, motor control circuit, and vehicle include a first logic circuit, a second logic circuit, a first input circuit, and a second input circuit. The two input terminals of the first logic circuit are respectively connected to the output terminal of the second logic circuit and the first input circuit. The two input terminals of the second logic circuit are respectively connected to the output terminal of the first logic circuit and the second input circuit. The output level of the second logic circuit is opposite to the output level of the first logic circuit. In this embodiment, the second input circuit is used to connect to peripheral circuits outside the latch circuit. Because the timing of the first input circuit powering up to the target level lags behind the timing of the second input circuit powering up to the target level during the power-on process of the latch circuit and the peripheral circuits outside the latch circuit (the target level is, for example, a high level), the timing problem of the power-on competition hazard of the second input circuit is eliminated. This prevents the latch circuit from being falsely triggered due to the second input circuit lags behind the first input circuit powering up to the target level, thereby ensuring that the latch circuit captures and latches the true sensitive fault signal after the latch circuit and the peripheral circuits outside the latch circuit are powered on. Attached Figure Description
[0034] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0035] Figure 1 This is a schematic diagram of the structure of a latch circuit according to one embodiment;
[0036] Figure 2A for Figure 1 A schematic diagram of one structure of the first input circuit in the circuit;
[0037] Figure 2B for Figure 1 Another schematic diagram of the first input circuit in the circuit;
[0038] Figure 3 for Figure 2B A schematic diagram of one structure of the first input circuit in the circuit;
[0039] Figure 4A for Figure 3 A color diagram of a simulation diagram of a latch circuit in operation;
[0040] Figure 4B for Figure 4A grayscale image;
[0041] Figure 5 for Figure 1 Another schematic diagram of the first input circuit in the circuit;
[0042] Figure 6 for Figure 5 A schematic diagram of one structure of the first input circuit in the circuit;
[0043] Figure 7A for Figure 6 A color diagram of a simulation diagram of a latch circuit in operation;
[0044] Figure 7B for Figure 7A grayscale image;
[0045] Figure 8 for Figure 1 Another schematic diagram of the first input circuit in the circuit;
[0046] Figure 9 for Figure 8 A schematic diagram of one structure of the first input circuit in the circuit;
[0047] Figure 10A for Figure 9 A color diagram of a simulation diagram of a latch circuit in operation;
[0048] Figure 10B for Figure 10A grayscale image;
[0049] Figure 11 for Figure 1 A schematic diagram of a structure of the first logic circuit in the middle;
[0050] Figure 12 for Figure 1 A schematic diagram of a second logic circuit.
[0051] Explanation of reference numerals in the attached figures:
[0052] 110 - First logic circuit, 120 - Second logic circuit, 210 - First input circuit, 220 - Second input circuit, 211 - First power supply, Tcon1 - First power-on timing unit, 212 - First resistor unit, 213 - First capacitor unit, R1 - First resistor, C1 - First capacitor, 214 - Second power supply, 215 - Second resistor unit, R2 - Second resistor, 216 - Third resistor unit, R3 - Third resistor, 111 - First AND gate, 112 - First inverter, 121 - Second AND gate, 122 - Second inverter, Tcon2 - Second power-on timing unit in the peripheral circuit, 311 - Power supply from the peripheral circuit to the second input circuit, 312 - Resistor unit connected to the second input circuit from the peripheral circuit, 313 - Capacitor unit connected to the second input circuit from the peripheral circuit. Detailed Implementation
[0053] For the purpose of understanding the present application, the present application will be described in more detail with reference to the attached drawings. The embodiments of the present application are shown in the drawings. However, the present application can be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and fully convey the scope of the application to those skilled in the art.
[0054] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the application pertains. The terminology used in the description herein is for describing particular embodiments only and is not intended to be limiting of the application.
[0055] It is to be understood that the terms "first", "second", and the like, used herein do not connote any hierarchy or order, but are used to distinguish one element from another. For example, a first element can be termed a second element, and, similarly, a second element can be termed a first element, without departing from the scope of the present application.
[0056] It is to be understood that, in the following embodiments, "connected" or "coupled" or "linked" or the like means that the circuit, module, unit, or the like, connected or coupled or linked with each other can transmit or exchange electrical signal or data.
[0057] It is to be understood that "at least one" means one or more, and "multiple" means two or more. "At least part of an element" means part or all of the element.
[0058] As used herein, the singular forms "a", "an" and "the" include plural referents unless the context clearly indicates otherwise. It is also to be understood that the term "comprising" or "including" or "having" or the like, means the presence of stated features, integers, steps, operations, components, parts, or combinations thereof, but does not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof.
[0059] In one exemplary embodiment, referring to Figure 1 , a latch circuit is provided, which includes a first logic circuit 110, a second logic circuit 120, a first input circuit 210, and a second input circuit 220.
[0060] The two input terminals of the first logic circuit 110 are connected with the output terminal of the second logic circuit 120 and the first input circuit 210 respectively, and the two input terminals of the second logic circuit 120 are connected with the output terminal of the first logic circuit 110 and the second input circuit 220 respectively. For example, the operation logic of the first logic circuit 110 and the second logic circuit 120 is logical NAND.
[0061] The level of the output terminal of the second logic circuit 120 is opposite to the level of the output terminal of the first logic circuit 110. For example, if the output terminal of the first logic circuit 110 outputs high level, the output terminal of the second logic circuit 120 outputs low level, and if the output terminal of the first logic circuit 110 outputs low level, the output terminal of the second logic circuit 120 outputs high level.
[0062] In the embodiment of the application, when the state of the first input circuit 210 is high level and the state of the second input circuit 220 is high level, the latch circuit is in the state to be latched; the second input circuit 220 is used to connect the peripheral circuit outside the latch circuit, for example, when the sensitive fault signal occurs in the peripheral circuit, the state of the first input circuit 210 is high level and the state of the second input circuit 220 will jump from high level to low level, at this time, the latch circuit can latch the low level, and the sensitive fault signal can be latched once it occurs; when the state of the first input circuit 210 jumps from high level to low level, the reset of the latch circuit is realized, and the latching of the low level is cleared; when the state of the first input circuit 210 is low level and the state of the second input circuit 220 is low level, the latch circuit is in the uncertain state, and the latch circuit will not generally appear in the uncertain state when working; wherein, the high level is logical level "1", and the low level is logical level "0".
[0063] Based on this, in the embodiment of the present application, during the power-on process of the latch circuit and the peripheral circuit outside the latch circuit, the timing of the first input circuit 210 powering on to the target level, for example, high level, lags behind the timing of the second input circuit 220 powering on to the target level, so that during the power-on process of the latch circuit and the peripheral circuit, only the case that the state of the first input circuit 210 is low level and the state of the second input circuit 220 is high level, or the case that the state of the first input circuit 210 is high level and the state of the second input circuit 220 is high level, can occur, and the case that the state of the first input circuit 210 is high level and the state of the second input circuit 220 is low level cannot occur, that is, the corresponding latch circuit can only appear in the reset state or the state to be latched, and cannot appear in the state of latching low level, that is, the latch circuit cannot appear in the case of being mis-triggered (it can be understood that if the latch circuit appears in the state of latching low level during the power-on process, it means that the latch circuit is mis-triggered due to the timing problem of power-on race), the embodiment of the present application thus eliminates the timing problem of power-on race of the second input circuit 220, so that the latch circuit will not be mis-triggered due to the fact that the second input circuit 220 lags behind the first input circuit 210 in powering on to the target level (it can be understood that if the second input circuit 220 lags behind the first input circuit 210 in powering on to high level during the power-on process of the latch circuit, the case that the state of the first input circuit 210 is high level and the state of the second input circuit 220 is low level will occur during the power-on process of the latch circuit, that is, the state of latching low level is appeared, and the latch circuit is mis-triggered), thereby guaranteeing that after the latch circuit and the peripheral circuit outside the latch circuit are powered on, the latch circuit captures and latches the sensitive fault signal that really occurs in the peripheral circuit.
[0064] In one exemplary embodiment, referring to Figure 2A , the first input circuit 210 includes a first power-on timing unit Tcon1 and a first power supply 211; the first power-on timing unit Tcon1 is connected to the first power supply 211; the peripheral circuit outside the latch circuit includes a second power-on timing unit Tcon2 and a power supply 311, the second power-on timing unit Tcon2 is connected to the power supply 311, and the second input circuit 220 is connected to the second power-on timing unit Tcon2.
[0065] In the embodiment of the present application, the first input circuit 210 powers on to the target level under the action of the first power-on timing unit Tcon1 according to the voltage of the first power supply 211; the second input circuit 220 powers on to the target level under the action of the second power-on timing unit Tcon2 according to the voltage of the power supply 311; the power-on timing of the first power-on timing unit Tcon1 lags behind the power-on timing of the second power-on timing unit Tcon2, so that the timing of the first input circuit 210 powering on to the target level lags behind the timing of the second input circuit 220 powering on to the target level.
[0066] In one exemplary embodiment, referring to Figure 2B , the first power-on timing unit Tcon1 includes a first resistance unit 212 and a first capacitance unit 213; a first end of the first resistance unit 212 is connected to the first power supply 211, and a second end of the first resistance unit 212 is connected to an input end of the first logic circuit 110; a first end of the first capacitance unit 213 is grounded, and a second end of the first capacitance unit 213 is connected to the second end of the first resistance unit 212.
[0067] Exemplarily, continuing to refer to Figure 2B , the second input circuit 220 can only include an input end IN, which accesses a peripheral circuit outside the latch circuit, and the peripheral circuit includes the second power-on timing unit Tcon2 and the power supply 311, and the second power-on timing unit Tcon2 can include a resistance unit 312 and a capacitance unit 313. Generally, when the peripheral circuit outside the latch circuit accesses the input end IN, the input end IN accesses the capacitance unit 313 for filtering, and accesses the resistance unit 312 and the power supply 311 for supplying power to the input end IN; thus, in the process of powering up the input end IN to the target level, i.e. in the process of powering up the second input circuit 220 to the target level, the power supply 311 charges the capacitance unit 313 through the resistance unit 312, so as to make the input end IN powered up to the target level.
[0068] In view of this, continuing to refer to Figure 2B , the RC value corresponding to the first input circuit 210 is greater than the RC value corresponding to the second input circuit 220 accessed by the peripheral circuit outside the latch circuit, and the RC value represents the product of the resistance value of the resistance unit and the capacitance value of the capacitance unit.
[0069] That is, the first input circuit 210 comprises the first resistance unit 212, the first power supply 211 and the first capacitance unit 213, and therefore, in the process of powering up the first input circuit 210 to the target level, the first power supply 211 charges the first capacitance unit 213 through the first resistance unit 212, that is, the first input circuit 210 and the second input circuit 220 are both connected to RC charging circuits. In this embodiment, the RC value corresponding to the first input circuit 210 is configured to be greater than the RC value corresponding to the second input circuit 220 connected by the peripheral circuit outside the latch circuit, that is, the product of the resistance value of the first resistance unit 212 and the capacitance value of the first capacitance unit 213 is greater than the product of the resistance value of the resistance unit 312 and the capacitance value of the capacitance unit 313, for example, at least ten times greater than the product of the resistance value of the resistance unit 312 and the capacitance value of the capacitance unit 313, so as to realize that in the process of powering up the latch circuit and the peripheral circuit outside the latch circuit, the timing of powering up the first input circuit 210 to the target level lags behind the timing of powering up the second input circuit 220 to the target level. In addition, the powering up timing of the first power supply 211 and the power supply 311 can be the same or different.
[0070] The first input circuit 210 provided by this embodiment comprises the first resistance unit 212, the first power supply 211 and the first capacitance unit 213, which has simple structure, is easy to implement and has low cost; and does not need to rely on peripheral circuits, but only needs to configure the product of the resistance value of the first resistance unit 212 and the capacitance value of the first capacitance unit 213, so as to further facilitate the implementation of the latch circuit; the powering up timing of the first power supply 211 and the power supply 311 can also be the same, that is, the power supplies of the first input circuit 210 and the second input circuit 220 can be simultaneous timing power supplies, so as to further reduce the cost of the latch circuit.
[0071] In an exemplary embodiment, referring to Figure 3 The first resistance unit 212 comprises a first resistor R1, and the first capacitance unit 213 comprises a first capacitor C1; a first end of the first resistor R1 is connected to the first power supply 211, and a second end of the first resistor R1 is connected to the first input end of the first logic circuit 110; a first end of the first capacitor C1 is grounded, and a second end of the first capacitor C1 is connected to the second end of the first resistor R1; in this way, the cost of the latch circuit is further reduced.
[0072] Referring to FIG. 4, FIG. 4 is a schematic diagram of a latch circuit according to another embodiment of the present application. Figure 3Figure 4 shows a simulation diagram of a latch circuit. The vertical axis represents voltage, and the horizontal axis represents time. The blue line Q_OV represents the output of the latch circuit, the green line S1 represents the power-on of the first input circuit 210 to a high level, and the red line V_BUS_OV represents the power-on of the second input circuit 220 to a high level. As can be seen from Figure 4, the timing of the power-on of the first input circuit 210 to a high level lags behind the timing of the power-on of the second input circuit 220 to a high level.
[0073] In one exemplary embodiment, reference is made to Figure 5 The first input circuit 210 includes a second resistor unit 215 and a second power supply 214; the first end of the second resistor unit 215 is connected to the second power supply 214, and the second end of the second resistor unit 215 is connected to an input terminal of the first logic circuit 110; wherein the power-on timing of the second power supply 214 is later than the power-on timing of the power supply 311 of the second input circuit 220.
[0074] In this embodiment, by setting the power-on timing of the second power supply 214 to be later than that of the power supply 311, the power-on timing of the first input circuit 210 to the target level is later than that of the second input circuit 220 to the target level. For example, the first input circuit 210 only starts to power on to the target level after the second input circuit 220 has been powered on to the target level. Furthermore, the first input circuit 210 in this embodiment only includes the second resistor unit 215 and the second power supply 214, which has a simple structure, is easy to implement, and has low cost.
[0075] In one exemplary embodiment, reference is made to Figure 6 The second resistor unit 215 includes a second resistor R2; the first end of the second resistor R2 is connected to the second power supply 214, and the second end of the second resistor R2 is connected to an input terminal of the first logic circuit 110; thus, the cost of the latch circuit is further reduced.
[0076] Refer to Figure 7, Figure 7 is Figure 6 Figure 7 shows a simulation diagram of a latch circuit. The vertical axis represents voltage, and the horizontal axis represents time. The blue line Q_OV represents the output of the latch circuit, the green line S1 represents the power-on of the first input circuit 210 to a high level, and the red line V_BUS_OV represents the power-on of the second input circuit 220 to a high level. As can be seen from Figure 7, the timing of the power-on of the first input circuit 210 to a high level lags behind the timing of the power-on of the second input circuit 220 to a high level.
[0077] In one exemplary embodiment, reference is made to Figure 8The first input circuit 210 comprises a third resistance unit 216. A first end of the third resistance unit 216 is grounded, and a second end of the third resistance unit 216 is connected with an input end of the first logic circuit 110. The second end of the third resistance unit 216 is also connected with a peripheral circuit outside the latch circuit. In the case that the second input circuit 220 is powered to the target level, the second end of the third resistance unit 216 receives a pull-up signal output by the peripheral circuit and powered to the target level.
[0078] In the embodiment, after the second input circuit 220 is powered to the target level, the second end of the third resistance unit 216 receives the pull-up signal output by the peripheral circuit and powered to the target level, and the timing of the first input circuit 210 powered to the target level is also behind the timing of the second input circuit 220 powered to the target level.
[0079] In an example embodiment, referring to Figure 9 The third resistance unit 216 comprises a third resistance R3. A first end of the third resistance R3 is grounded, and a second end of the third resistance R3 is connected with an input end of the first logic circuit 110. In this way, the cost of the latch circuit is further reduced.
[0080] Referring to FIG. 10, FIG. 10 is a working simulation diagram of the latch circuit in Figure 9 . The vertical axis represents voltage, and the horizontal axis represents time. The blue line Q_OV represents the output of the latch circuit, the green line S1 represents the first input circuit 210 powered to high level, and the red line V_BUS_OV represents the second input circuit 220 powered to high level. As can be seen from FIG. 10, the timing of the first input circuit 210 powered to high level is behind the timing of the second input circuit 220 powered to high level.
[0081] In an example embodiment, referring to Figure 11 The first logic circuit 110 comprises a first AND gate 111 and a first inverter 112. Two input ends of the first AND gate 111 are respectively connected with an output end of the second logic circuit 120 and the first input circuit 210, and an output end of the first AND gate 111 is connected with an input end of the first inverter 112.
[0082] In an example embodiment, the first logic circuit 110 comprises a NAND gate.
[0083] In an example embodiment, referring to Figure 12 The second logic circuit 120 comprises a second AND gate 121 and a second inverter 122. Two input ends of the second AND gate 121 are respectively connected with an output end of the first logic circuit 110 and the second input circuit 220, and an output end of the second AND gate 121 is connected with an input end of the second inverter 122.
[0084] In one example embodiment, the second logic circuit 120 comprises a NAND gate.
[0085] In one example embodiment, the application also provides an RS flip-flop, which comprises the latch circuit provided in any of the above embodiments.
[0086] The RS flip-flop provided by the embodiments of the application and the latch circuit belong to the same utility model concept, can solve the same technical problems, and further achieve the same technical effects, and the repeated contents will not be described here.
[0087] In one example embodiment, the application also provides a motor control circuit, which comprises a peripheral circuit and the RS flip-flop provided in any of the above embodiments, and the peripheral circuit at least comprises a third power supply 311, a fourth resistor unit 312 and a second capacitor unit 313; wherein the first end of the fourth resistor unit 312 is connected to the third power supply 311, the second end of the fourth resistor unit 312 is connected to the second input circuit 220, the first end of the second capacitor unit 313 is connected to the second input circuit 220, and the second end of the second capacitor unit 313 is grounded.
[0088] The motor controller provided by the embodiments of the application and the latch circuit belong to the same utility model concept, can solve the same technical problems, and further achieve the same technical effects, and the repeated contents will not be described here.
[0089] In one example embodiment, the peripheral circuit is, for example, a circuit further comprising a micro control unit (MCU).
[0090] In one example embodiment, the application also provides a vehicle, which comprises a motor and the motor control circuit provided in any of the above embodiments, the motor is connected to the motor control circuit, and the motor control circuit is used for controlling the motor to work.
[0091] The vehicle provided by the embodiments of the application and the latch circuit belong to the same utility model concept, can solve the same technical problems, and further achieve the same technical effects, and the repeated contents will not be described here.
[0092] In the description of the specification, the description referring to the terms “some embodiments”, “other embodiments”, and the like means that the specific features, structures, materials or characteristics described in combination with the embodiments or examples are contained in at least one embodiment or example of the application. In the specification, the illustrative description of the above terms does not necessarily mean the same embodiment or example.
[0093] Any combination of the technical features in the above-described embodiments can be made, and for the sake of brevity, not all possible combinations are described, however, it is to be understood that the application encompasses all such possible combinations.
[0094] The above-described embodiments only express several implementation manners of the present application, and the description is relatively specific and detailed, but it should not be understood as a limitation on the scope of the present application. It should be pointed out that, for ordinary skilled persons in the art, several modifications and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the appended claims.
Claims
1. A latch circuit, characterized by, The latch circuit comprises a first logic circuit, a second logic circuit, a first input circuit and a second input circuit; two input ends of the first logic circuit are connected with an output end of the second logic circuit and the first input circuit respectively; two input ends of the second logic circuit are connected with an output end of the first logic circuit and the second input circuit respectively; A level of the output end of the second logic circuit is opposite to a level of the output end of the first logic circuit; In a power-on process of the latch circuit, a time sequence of the first input circuit being powered on to a target level is later than a time sequence of the second input circuit being powered on to the target level.
2. The latch circuit of claim 1, wherein, The first input circuit comprises a first power-on time sequence unit and a first power supply; the first power-on time sequence unit is connected with the first power supply; A peripheral circuit outside the latch circuit comprises a second power-on time sequence unit, and the second input circuit is connected with the second power-on time sequence unit; The power-on time sequence of the first power-on time sequence unit is later than the power-on time sequence of the second power-on time sequence unit.
3. The latch circuit of claim 2, wherein, The first power-on time sequence unit comprises a first resistance unit and a first capacitance unit; A first end of the first resistance unit is connected with the first power supply, and a second end of the first resistance unit is connected with an input end of the first logic circuit; A first end of the first capacitance unit is grounded, and a second end of the first capacitance unit is connected with the second end of the first resistance unit.
4. The latch circuit of claim 3, wherein, The first resistance unit comprises a first resistance, and the first capacitance unit comprises a first capacitance; A first end of the first resistance is connected with the first power supply, and a second end of the first resistance is connected with an input end of the first logic circuit; A first end of the first capacitance is grounded, and a second end of the first capacitance is connected with the second end of the first resistance.
5. The latch circuit of claim 1, wherein, The first input circuit comprises a second resistance unit and a second power supply; A first end of the second resistance unit is connected with the second power supply, and a second end of the second resistance unit is connected with an input end of the first logic circuit; The power-on time sequence of the second power supply is later than the power-on time sequence of a power supply of the second input circuit.
6. The latch circuit of claim 5, wherein, The second resistance unit comprises a second resistance; A first end of the second resistance is connected with the second power supply, and a second end of the second resistance is connected with an input end of the first logic circuit.
7. The latch circuit of claim 1, wherein, The first input circuit comprises a third resistance unit; A first end of the third resistance unit is grounded, and a second end of the third resistance unit is connected with an input end of the first logic circuit; The second end of the third resistance unit is also connected with a peripheral circuit outside the latch circuit, and in the case that the second input circuit is powered on to the target level, the second end of the third resistance unit receives a pull-up signal output by the peripheral circuit and is powered on to the target level.
8. The latch circuit of claim 7, wherein, The third resistance unit comprises a third resistance; A first end of the third resistance is grounded, and a second end of the third resistance is connected with an input end of the first logic circuit.
9. The latch circuit of any one of claims 1-8, wherein, The first logic circuit comprises a first AND gate and a first inverter; The two input ends of the first AND gate are connected with the output end of the second logic circuit and the first input circuit respectively, and the output end of the first AND gate is connected with the input end of the first inverter.
10. The latch circuit of any one of claims 1-8, wherein, The second logic circuit comprises a second AND gate and a second inverter. The two input ends of the second AND gate are connected with the output end of the first logic circuit and the second input circuit respectively, and the output end of the second AND gate is connected with the input end of the second inverter.
11. An RS flip-flop, characterized by, The latch circuit comprises the latch circuit according to any one of claims 1-10.
12. An electric motor control circuit, characterized by The RS flip-flop comprises the RS flip-flop according to claim 11 and a peripheral circuit, wherein the peripheral circuit comprises at least a third power supply, a fourth resistance unit and a second capacitance unit; the first end of the fourth resistance unit is connected with the third power supply, the second end of the fourth resistance unit is connected with the second input circuit, the first end of the second capacitance unit is connected with the second input circuit, and the second end of the second capacitance unit is grounded.
13. A vehicle characterized by comprising: The motor control circuit comprises the motor control circuit according to claim 12 and a motor.