Semiconductor structure and memory

Abstract

The embodiment of the utility model provides a semiconductor structure and a memory. The semiconductor structure comprises a substrate; the gate structure is arranged on one side of the substrate and comprises a gate conductive layer and a gate dielectric layer arranged between the substrate and the gate conductive layer; the isolation structures are arranged on the two opposite sides of the gate structure, each isolation structure comprises a first cavity, a second cavity and an isolation layer arranged between the first cavity and the second cavity, and the first cavity is arranged between the gate structure and the isolation layer and exposes the side wall of the gate structure.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the technical field of semiconductor technology, and specifically relate to a semiconductor structure and a memory. BACKGROUND

[0002] At present, Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) structures are widely used in semiconductor devices. With the development of semiconductor industry technology, the density of semiconductor devices per unit area is getting higher and higher, the size of semiconductor devices is constantly shrinking, the parasitic capacitance and resistance-capacitance delay (RC Delay) in semiconductor devices are constantly increasing, which poses a challenge to the performance of semiconductor devices.

[0003] Therefore, how to reduce the parasitic capacitance in semiconductor devices and improve the resistance-capacitance delay to improve the performance of semiconductor devices has become a technical problem to be solved. CONTENT OF THE UTILITY MODEL

[0004] Therefore, embodiments of the present application provide a semiconductor structure and a memory.

[0005] In a first aspect, embodiments of the present application provide a semiconductor structure, which comprises: a substrate; a gate structure provided on one side of the substrate, the gate structure comprising a gate conductive layer and a gate dielectric layer provided between the substrate and the gate conductive layer; an isolation structure provided on opposite sides of the gate structure, the isolation structure comprising a first cavity, a second cavity, and an isolation layer provided between the first cavity and the second cavity, the first cavity being provided between the gate structure and the isolation layer and exposing a sidewall of the gate structure.

[0006] In some embodiments, the semiconductor structure further comprises: a first dielectric layer provided on one side of the substrate and on opposite sides of the gate structure, the isolation structure being provided between the gate structure and the first dielectric layer, and the second cavity being provided between the isolation layer and the first dielectric layer.

[0007] In some embodiments, the gate conductive layer, the isolation layer, and the first dielectric layer are flush with the surface of the substrate away from the substrate.

[0008] In some embodiments, the semiconductor structure further comprises: a second dielectric layer provided on the side of the gate structure, the isolation structure, and the first dielectric layer away from the substrate, the second dielectric layer being used to seal the first cavity and the second cavity.

[0009] In some embodiments, the second dielectric layer includes a first portion, a second portion and a third portion, the first portion and the first dielectric layer, the gate conductive layer are all in contact; the second portion is in contact with the first portion and is arranged between the gate structure and the isolation layer, and the second portion is used for sealing the first cavity; the third portion is in contact with the first portion and is arranged between the isolation layer and the first dielectric layer, and the third portion is used for sealing the second cavity.

[0010] In some embodiments, the semiconductor structure further includes: source and drain regions arranged in the substrate and respectively arranged on opposite sides of the gate structure.

[0011] In some embodiments, the semiconductor structure further includes: a first conductive column extending through the second dielectric layer and the first dielectric layer and in contact with the source region; and a second conductive column extending through the second dielectric layer and the first dielectric layer and in contact with the drain region.

[0012] In some embodiments, the semiconductor structure further includes: first and second doped regions arranged in the substrate and respectively arranged on opposite sides of the gate structure, the first doped region and the source region are arranged on the same side of the gate structure, and the doping concentration of the first doped region is less than that of the source region; and the second doped region and the drain region are arranged on the same side of the gate structure, and the doping concentration of the second doped region is less than that of the drain region.

[0013] In some embodiments, the first dielectric layer and the second dielectric layer are of the same material.

[0014] In a second aspect, the embodiments of the utility model provide a memory, the memory includes: the semiconductor structure in the above technical scheme.

[0015] The embodiments of the utility model provide a semiconductor structure and a memory. In the embodiments of the utility model, the side wall of the gate structure is provided with an isolation structure, the isolation structure includes a first cavity, a second cavity and an isolation layer arranged between the first cavity and the second cavity, the first cavity is arranged between the gate structure and the isolation layer and exposes the side wall of the gate structure, the risk of collapse of the semiconductor structure with the cavity can be reduced while the size of the cavity is increased, thereby the parasitic capacitance can be effectively reduced, the resistance-capacitance delay is improved, and the performance of the semiconductor structure can be improved. ACCURATE DRAWINGS

[0016] Figure 1 The utility model provides a semiconductor structure's cross section schematic view for the embodiments of the utility model;

[0017] Figures 2 to 13The sectional view schematic diagram of the semiconductor structure in a manufacturing process is provided for the embodiment of the utility model.

[0018] Figure 14 The block diagram of the memory is provided for the embodiment of the utility model. DETAILED DESCRIPTION

[0019] The technical scheme in the embodiment of the utility model will be clearly and completely described below in combination with the embodiment of the utility model and the drawings. Obviously, the described embodiment is only a part of the embodiment of the utility model, rather than all the embodiments. Based on the embodiment of the utility model, all the other embodiments obtained by the person skilled in the art without creative labor fall within the protection scope of the utility model.

[0020] In the following description, a large number of specific details are given in order to provide a more thorough understanding of the utility model. However, it is obvious for the person skilled in the art that the utility model can be implemented without one or more of these details. In other examples, in order to avoid confusion with the utility model, some technical features known in the art are not described; that is, all the features of the actual embodiment are not described here, and the known functions and structures are not described in detail.

[0021] In the drawings, the size of the layer, region, element and its relative size can be exaggerated for clarity. The same reference signs represent the same elements throughout.

[0022] It should be understood that when an element or layer is referred to as being "on", "adjacent", "connected to", or "coupled to" another element or layer, it can be directly on, adjacent, connected or coupled to the other element or layer, or intervening elements or layers can be present. In contrast, when an element is referred to as being "directly on", "directly adjacent", "directly connected to", or "directly coupled to" another element or layer, then there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present application. Similarly, a second element, component, region, layer or section discussed below could be termed a first element, component, region, layer or section without departing from the teachings of the present application.

[0023] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0024] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of the invention. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0025] To fully understand this utility model, detailed steps and structures will be presented in the following description to illustrate the technical solution of this utility model. Preferred embodiments of this utility model are described in detail below; however, in addition to these detailed descriptions, this utility model may have other embodiments.

[0026] Before introducing the embodiments of this utility model, the various directions that may be involved below are defined. An intersecting X-direction and Y-direction are defined in the plane containing the substrate. The X-direction and Y-direction can be perpendicular to each other or form a certain angle. The direction perpendicular to the substrate is defined as the Z-direction. In some embodiments, any two of the X-direction, Y-direction, and Z-direction are perpendicular to each other.

[0027] refer to Figure 1 , Figure 1 This is a cross-sectional schematic diagram of a semiconductor structure provided for an embodiment of the present invention. Figure 1As shown, the semiconductor structure 100 includes: a substrate 102; a gate structure 110 arranged on one side of the substrate 102 along the Z direction, that is, the gate structure 110 is arranged on the substrate 102, and the gate structure 110 includes a gate conductive layer 106 and a gate dielectric layer 104 arranged between the substrate 102 and the gate conductive layer 106; and an isolation structure 150 arranged on opposite sides of the gate structure 110 along the X direction, the isolation structure 150 includes a first cavity 132, a second cavity 134, and a second isolation layer 118 arranged between the first cavity 132 and the second cavity 134, and the first cavity 132 is arranged between the gate structure 110 and the second isolation layer 118 and exposes the sidewall of the gate structure 110.

[0028] Here, the substrate 102 can include a semiconductor substrate; specifically, at least one single-element semiconductor material (for example, a silicon (Si) substrate or a germanium (Ge) substrate, etc.), at least one III-V compound semiconductor material (for example, a gallium nitride (GaN) substrate, a gallium arsenide (GaAs) substrate, or an indium phosphide (InP) substrate, etc.), at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art, and can also include other semiconductor-containing substrates, such as a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GeOI) substrate, a polycrystalline semiconductor layer on an insulating layer, or a silicon germanium substrate, etc.

[0029] Here, the gate structure 110 can include the gate dielectric layer 104 and the gate conductive layer 106 arranged in sequence on the substrate 102. The gate dielectric layer 104 can include but is not limited to a silicon oxide material, and the gate conductive layer 106 can include a conductive material, for example, a metal material.

[0030] Here, the isolation structure 150 is arranged on the substrate 102, and the isolation structure 150 is arranged on opposite sides of the gate structure 110 along the X direction. From the direction close to the gate structure 110 to the direction away from the gate structure 110, the isolation structure 150 includes the first cavity 132, the second isolation layer 118, and the second cavity 134 in sequence. In other words, the first cavity 132 is arranged between the gate structure 110 and the second isolation layer 118, the second isolation layer 118 is arranged between the first cavity 132 and the second cavity 134, and the second isolation layer 118 is used to separate the first cavity 132 and the second cavity 134; wherein the first cavity 132 exposes the sidewall of the gate structure 110.

[0031] In the embodiment of the utility model, the second isolation layer can play a supporting role, avoiding the cavity formed after the first cavity and the second cavity are connected in communication, which has a relatively large size, leading to the risk of collapse of the semiconductor structure.

[0032] Here, the second isolation layer 118 can include, but is not limited to, a silicon nitride material, a silicon oxide material, or a silicon oxynitride material.

[0033] In the embodiment of the utility model, the side wall of the gate structure is provided with an isolation structure, the isolation structure includes a first cavity, a second cavity and a second isolation layer arranged between the first cavity and the second cavity, the first cavity is arranged between the gate structure and the second isolation layer and exposes the side wall of the gate structure, the cavity size is increased while the risk of collapse of the semiconductor structure with the cavity is reduced, thereby the parasitic capacitance can be effectively reduced, the resistance-capacitance delay is improved, and the performance of the semiconductor structure is improved.

[0034] In some embodiments, the semiconductor structure 100 further includes: a first dielectric layer 130 arranged on one side of the substrate 102 along the Z direction and arranged on opposite sides of the gate structure 110 along the X direction, the isolation structure 150 is arranged between the gate structure 110 and the first dielectric layer 130, and the second cavity 134 is arranged between the second isolation layer 118 and the first dielectric layer 130. Here, the gate structure 110, the isolation structure 150 and the first dielectric layer 130 are arranged on the same side of the substrate 102 along the Z direction.

[0035] Here, the first cavity 132 is arranged between the gate structure 110 and the second isolation layer 118, and the gate structure 110 and the second isolation layer 118 can form the side wall of the first cavity 132. The first cavity 132 has a top surface and a bottom surface opposite along the Z direction, and the substrate 102 can form the bottom surface of the first cavity 132. The second cavity 134 is arranged between the second isolation layer 118 and the first dielectric layer 130, and the second isolation layer 118 and the first dielectric layer 130 can form the side wall of the second cavity 134. The second cavity 134 has a top surface and a bottom surface opposite along the Z direction, and the substrate 102 can form the bottom surface of the second cavity 134.

[0036] Here, the height of the first cavity 132 and the second cavity 134 along the Z direction is less than the height of the second isolation layer 118 along the Z direction, that is, the top surface of the first cavity 132 and the top surface of the second cavity 134 are lower than the surface of the gate structure 110 away from the substrate 102, that is, the top surface of the first cavity 132 and the top surface of the second cavity 134 are lower than the top surface of the gate conductive layer 106.

[0037] Here, the first dielectric layer 130 can include, but is not limited to, a silicon oxide material.

[0038] In some embodiments, the surfaces of the gate conductive layer 106, the second isolation layer 118 and the first dielectric layer 130 away from the substrate 102 are flush. Here, the surfaces of the gate conductive layer 106, the second isolation layer 118 and the first dielectric layer 130 away from the substrate 102 can be formed after planarization treatment.

[0039] Here, the phrase that the gate conductive layer 106, the second isolation layer 118 and the first dielectric layer 130 are flush with the surface of the substrate 102 away from the substrate 102 means that the height difference of the gate conductive layer 106, the second isolation layer 118 and the first dielectric layer 130 away from the surface of the substrate 102 along the Z direction is 0, or the height difference of the gate conductive layer 106, the second isolation layer 118 and the first dielectric layer 130 away from the surface of the substrate 102 along the Z direction is within an acceptable range of process error.

[0040] Figure 1 The dashed line in the middle indicates the interface between the first dielectric layer 130 and the second dielectric layer 136, which is only used to illustrate the relative position relationship between the first dielectric layer 130 and the second dielectric layer 136, and does not mean that there is an actual interface between the first dielectric layer 130 and the second dielectric layer 136. It should be noted that the materials of the first dielectric layer 130 and the second dielectric layer 136 can be the same or different. In some embodiments, the materials of the first dielectric layer 130 and the second dielectric layer 136 are the same, that is, Figure 1 The filled patterns of the first dielectric layer 130 and the second dielectric layer 136 are the same, and there is no actual interface between the first dielectric layer 130 and the second dielectric layer 136. In other embodiments, the materials of the first dielectric layer 130 and the second dielectric layer 136 are different, that is, there is an actual interface between the first dielectric layer 130 and the second dielectric layer 136 of different materials.

[0041] In some embodiments, the semiconductor structure 100 further comprises: a second dielectric layer 136 disposed on the side of the gate structure 110, the isolation structure 150 and the first dielectric layer 130 away from the substrate 102, the second dielectric layer 136 being used to seal the first cavity 132 and the second cavity 134. Here, the gate structure 110, the isolation structure 150 and the first dielectric layer 130 are all disposed between the substrate 102 and the second dielectric layer 136. The second dielectric layer 136 can form the top surface of the first cavity 132, and the second dielectric layer 136 can also form the top surface of the second cavity 134.

[0042] In some embodiments, the second dielectric layer 136 comprises a first portion 136a, a second portion 136b (as shown by the solid square box in the middle) and a third portion 136c (as shown by the solid circle box in the middle), the first portion 136a contacts the first dielectric layer 130, the gate conductive layer 106 and the second isolation layer 118; the second portion 136b contacts the first portion 136a and is disposed between the gate structure 110 and the second isolation layer 118, the second portion 136b being used to seal the first cavity 132; the third portion 136c contacts the first portion 136a and is disposed between the second isolation layer 118 and the first dielectric layer 130, the third portion 136c being used to seal the second cavity 134. Figure 1 Figure 1 In some embodiments, the second dielectric layer 136 comprises a first portion 136a, a second portion 136b (as shown by the solid square box in the middle) and a third portion 136c (as shown by the solid circle box in the middle), the first portion 136a contacts the first dielectric layer 130, the gate conductive layer 106 and the second isolation layer 118; the second portion 136b contacts the first portion 136a and is disposed between the gate structure 110 and the second isolation layer 118, the second portion 136b being used to seal the first cavity 132; the third portion 136c contacts the first portion 136a and is disposed between the second isolation layer 118 and the first dielectric layer 130, the third portion 136c being used to seal the second cavity 134.​

[0043] Here, the first portion 136a contacts the surface of the substrate 102 away from the first dielectric layer 130, the first portion 136a also contacts the surface of the substrate 102 away from the second isolation layer 118 in the isolation structure 150, and the first portion 136a also contacts the surface of the substrate 102 away from the gate conductive layer 106 in the gate structure 110.

[0044] Here, the sum of the height of the first cavity 132 and the second portion 136b along the Z direction is the same as the height of the second isolation layer 118 along the Z direction. The sum of the height of the second cavity 134 and the third portion 136c along the Z direction is the same as the height of the second isolation layer 118 along the Z direction.

[0045] In some embodiments, the semiconductor structure 100 further comprises: the source region 126 and the drain region 128 are respectively arranged on the opposite sides of the gate structure 110 along the X direction in the substrate 102.

[0046] Here, the semiconductor structure 100 can comprise a transistor structure, and the transistor structure can comprise the source region 126, the drain region 128, a channel region arranged between the source region 126 and the drain region 128, and the gate structure 110 arranged on one side of the channel region. In some embodiments, the semiconductor structure 100 can comprise an N-type metal oxide semiconductor (NMOS) transistor, and the source region 126 and the drain region 128 comprise N-type doped ions. In other embodiments, the semiconductor structure 100 can also comprise a P-type metal oxide semiconductor (PMOS) transistor, and the source region 126 and the drain region 128 comprise P-type doped ions.

[0047] In the utility model, the isolation structure is arranged between the gate structure and the source region (or the drain region), which can reduce the parasitic capacitance between the gate structure and the source region (or the drain region) in the transistor structure.

[0048] In some embodiments, the semiconductor structure 100 further comprises: the first doped region 114 and the second doped region 116 are respectively arranged on the opposite sides of the gate structure 110 along the X direction in the substrate 102, the first doped region 114 and the source region 126 are arranged on the same side of the gate structure 110, and the doping concentration of the first doped region 114 is less than the doping concentration of the source region 126; the second doped region 116 and the drain region 128 are arranged on the same side of the gate structure 110, and the doping concentration of the second doped region 116 is less than the doping concentration of the drain region 128.

[0049] Here, the first doped region 114 and the second doped region 116 can be referred to as a lightly doped region, the doping type of the lightly doped region is the same as the doping type of the source region 126 / the drain region 128, the doping concentration of the lightly doped region is less than the doping concentration of the source region 126 / the drain region 128, and the doping depth of the lightly doped region is less than the doping depth of the source region 126 / the drain region 128. Here, the lightly doped region can form a region with a reduced doping concentration gradient, thereby reducing the electric field intensity near the drain region and moving the electric field peak position towards the channel end, so that the leakage current caused by high electric field intensity can be alleviated, thereby improving the reliability and performance of the transistor structure.

[0050] In some embodiments, the semiconductor structure 100 further includes: a third doped region 120 and a fourth doped region 122 disposed in the substrate 102 and on opposite sides of the gate structure 110 along the X direction, respectively, which can be referred to as a pocket implant, the doping type of the pocket implant is different from the doping type of the source region 126 / the drain region 128, and the doping depth of the pocket implant is between the doping depth of the lightly doped region and the doping depth of the source region 126 / the drain region 128, i.e., the doping depth of the pocket implant is greater than the doping depth of the lightly doped region and the doping depth of the pocket implant is less than the doping depth of the source region 126 / the drain region 128. Here, the pocket implant can reduce the degree of depletion of the depletion region to produce a smaller punch-through current.

[0051] In some embodiments, the semiconductor structure 100 further includes: a first conductive column 138 extending through the second dielectric layer 136 and the first dielectric layer 130 and in contact with the source region 126; and a second conductive column 140 extending through the second dielectric layer 136 and the first dielectric layer 130 and in contact with the drain region 128.

[0052] Here, the semiconductor structure 100 can include: a first lead-out structure 146 for electrically leading out the source region 126; and a second lead-out structure 148 for electrically leading out the drain region 128. The first lead-out structure 146 includes the first conductive column 138 extending along the Z direction and the first conductive layer 142 disposed in the second dielectric layer 136, the first conductive column 138 includes a first end and a second end on opposite sides along the Z direction, the first end of the first conductive column 138 is in contact with the source region 126, and the second end of the first conductive column 138 is in contact with the first conductive layer 142. The second lead-out structure 148 includes the second conductive column 140 extending along the Z direction and the second conductive layer 144 disposed in the second dielectric layer 136, the second conductive column 140 includes a third end and a fourth end on opposite sides along the Z direction, the third end of the second conductive column 140 is in contact with the drain region 128, and the fourth end of the second conductive column 140 is in contact with the second conductive layer 144.

[0053] In the embodiment of the utility model, the isolation structure is arranged between the gate structure and the first conductive column (or the second conductive column), so that the parasitic capacitance between the gate structure and the first conductive column (or the second conductive column) in the semiconductor structure can be reduced, that is, the parasitic capacitance between the gate structure and the source lead-out structure (or the drain lead-out structure) in the semiconductor structure can be reduced.

[0054] Reference Figure 2 to 13 , Figures 2 to 13 The sectional view of the semiconductor structure in the manufacturing process is provided in the embodiment of the utility model. The manufacturing method of the semiconductor structure provided in the embodiment of the utility model will be described in detail below. Figures 2 to 13

[0055] Reference Figure 2 As shown in the figure, the substrate 102 is provided.

[0056] Here, the substrate 102 can include a semiconductor material, for example, a silicon material.

[0057] Reference Figure 3 As shown in the figure, the gate dielectric material layer 104a, the gate conductive material layer 106a and the protection material layer 108a are sequentially formed on the substrate 102.

[0058] Here, the gate dielectric material layer 104a can include but is not limited to a silicon oxide material; the gate conductive material layer 106a can include a conductive material, for example, a metal material; and the protection material layer 108a can include but is not limited to a silicon nitride material.

[0059] Here, the process of forming the gate dielectric material layer 104a, the gate conductive material layer 106a and the protection material layer 108a can include but is not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or any combination thereof.

[0060] Reference Figure 4 As shown in the figure, the protection material layer 108a, the gate conductive material layer 106a and the gate dielectric material layer 104a are etched in the Z direction in sequence to form the initial gate structure 110a; wherein the etched protection material layer 108a forms the protection layer 108, the etched gate conductive material layer 106a forms the gate conductive layer 106, the etched gate dielectric material layer 104a forms the gate dielectric layer 104, and the initial gate structure 110a includes the gate dielectric layer 104, the gate conductive layer 106 and the protection layer 108 arranged on the substrate 102 in sequence.

[0061] Still referring to​Figure 4 As shown, a first isolation material layer 112a is formed covering the substrate 102 and the initial gate structure 110a. Here, the first isolation material layer 112a covers the surface of the substrate 102 exposed by the initial gate structure 110a, and the first isolation material layer 112a also covers the sidewall of the initial gate structure 110a and the top surface away from the substrate 102.

[0062] Referring back to Figure 5 As shown, part of the first isolation material layer 112a covering the substrate 102 is removed to form a first isolation layer 112. Here, the first isolation layer 112 covers the sidewall of the initial gate structure 110a and the top surface away from the substrate 102.

[0063] Here, the process of removing part of the first isolation material layer 112a can include dry etching.

[0064] Referring back to Figure 6 As shown, ion implantation is performed on the substrate 102 on both sides of the initial gate structure 110a along the X direction to form a first doped region 114 and a second doped region 116, respectively. Here, the first doped region 114 and the second doped region 116 can be referred to as a lightly doped region.

[0065] In the embodiment of the utility model, ion implantation is performed on the substrate on both sides of the initial gate structure along the X direction, the sidewall of the initial gate structure is provided with the first isolation layer, and the first isolation layer can protect the initial gate structure during ion implantation.

[0066] Referring back to Figure 7 As shown, a second isolation material layer 118a is formed covering the substrate 102 and the first isolation layer 112. Here, the second isolation material layer 118a covers the surface of the substrate 102 exposed by the initial gate structure 110a, and the second isolation material layer 118a also covers the surface of the first isolation layer 112.

[0067] Referring back to Figure 8 As shown, part of the second isolation material layer 118a covering the substrate 102 is removed to form a second isolation layer 118. At this time, during the process of removing part of the second isolation material layer 118a covering the surface of the substrate 102, part of the second isolation material layer 118a covering the top surface of the initial gate structure 110a can be removed. Here, the second isolation layer 118 covers the surface of the first isolation layer 112.

[0068] Here, the process of removing part of the second isolation material layer 118a can include dry etching.

[0069] Still referring back to Figure 8As shown, ion implantation is performed on the substrate 102 on both sides of the initial gate structure 110a along the X direction to form a third doped region 120 and a fourth doped region 122, respectively. Here, the third doped region 120 and the fourth doped region 122 can be referred to as pocket ion implantation regions.

[0070] In the embodiments of the present application, ion implantation is performed on the substrate on both sides of the initial gate structure along the X direction, and the sidewall of the initial gate structure is provided with a first isolation layer and a second isolation layer. The first isolation layer and the second isolation layer can protect the initial gate structure during ion implantation.

[0071] Referring to Figure 9 As shown, a third isolation material layer 124a covering the substrate 102 and the second isolation layer 118 is formed. Here, the third isolation material layer 124a covers the surface of the substrate 102 exposed by the initial gate structure 110a, and the third isolation material layer 124a also covers the surface of the second isolation layer 118.

[0072] Referring to Figure 10 As shown, the third isolation material layer 124a covering the substrate 102 is removed to form a third isolation layer 124. At this time, in the process of removing part of the third isolation material layer 124a covering the surface of the substrate 102, part of the third isolation material layer 124a covering the top surface of the initial gate structure 110a can be removed. Here, the third isolation layer 124 covers the surface of the second isolation layer 118.

[0073] Here, the process of removing part of the third isolation material layer 124a can include dry etching.

[0074] Here, the process of forming the first isolation material layer 112a, the second isolation material layer 118a and the third isolation material layer 124a can include but is not limited to CVD, PVD, ALD or any combination thereof.

[0075] In some embodiments, the materials of the first isolation layer 112 and the third isolation layer 124 can be the same or different. Here, the materials of the first isolation layer 112 and the second isolation layer 118 are different, and the materials of the third isolation layer 124 and the second isolation layer 118 are different.

[0076] Still referring to Figure 10 As shown, ion implantation is performed on the substrate 102 on both sides of the initial gate structure 110a along the X direction to form a source region 126 and a drain region 128, respectively.

[0077] In this embodiment of the invention, ion implantation is performed on the substrates on opposite sides of the initial gate structure along the X direction. The sidewalls of the initial gate structure are provided with a first isolation layer, a second isolation layer, and a third isolation layer. The first isolation layer, the second isolation layer, and the third isolation layer can protect the initial gate structure during the ion implantation process.

[0078] refer to Figure 11 As shown, a first dielectric material layer 130a is formed on the substrate 102, and the first dielectric material layer 130a covers the substrate 102 and the third isolation layer 124. Here, the first dielectric material layer 130a covers the surface of the substrate 102 exposed by the initial gate structure 110a, and the first dielectric material layer 130a also covers the third isolation layer 124.

[0079] refer to Figure 12 As shown, the first dielectric material layer 130a is planarized to form the first dielectric layer 130 and expose the surface of the gate conductive layer 106. During the planarization process, a portion of the first dielectric material layer 130a, a portion of the first isolation layer 112, a portion of the second isolation layer 118, a portion of the third isolation layer 124, and the protective layer 108 need to be removed. After removing the protective layer 108 from the initial gate structure 110a, the gate dielectric layer 104 and the gate conductive layer 106 together form the gate structure 110.

[0080] Here, after planarization, the surfaces of the first dielectric layer 130, the first isolation layer 112, the second isolation layer 118, the third isolation layer 124, and the gate conductive layer 106 that are away from the substrate 102 are basically flush.

[0081] Here, "the surfaces of the first dielectric layer 130, the first isolation layer 112, the second isolation layer 118, and the third isolation layer 124 are basically flush" means that the height difference between the surfaces of the first dielectric layer 130, the first isolation layer 112, the second isolation layer 118, and the third isolation layer 124 along the Z direction is 0, or that the height difference between the surfaces of the first dielectric layer 130, the first isolation layer 112, the second isolation layer 118, and the third isolation layer 124 along the Z direction is within an acceptable range of process error.

[0082] Here, planarization can include, but is not limited to, chemical mechanical polishing (CMP) processing.

[0083] Still referencing Figure 12 As shown, the first isolation layer 112 is removed to expose a portion of the surface of the substrate 102, and the third isolation layer 124 is removed to expose a portion of the surface of the substrate 102, while the second isolation layer 118 is retained.

[0084] Here, the process for removing the first isolation layer 112 and the third isolation layer 124 may include wet etching. During the wet etching process, the removal rates of the first isolation layer 112 (or the third isolation layer 124) and the second isolation layer 118 are different; that is, the removal rate of the first isolation layer 112 (or the third isolation layer 124) is greater than the removal rate of the second isolation layer 118. Therefore, during the removal of the first isolation layer 112 and the third isolation layer 124, the second isolation layer 118 can be retained, and the space originally occupied by the first isolation layer 112 forms a first cavity, while the space originally occupied by the third isolation layer 124 forms a second cavity.

[0085] In this embodiment of the invention, ion implantation is performed first, and then the first isolation layer and the third isolation layer are removed to form the first cavity and the second cavity, respectively. This can protect the gate structure during the ion implantation process using the first isolation layer, the second isolation layer and the third isolation layer, and also reduce parasitic capacitance and resistive capacitance delay after the semiconductor structure is formed.

[0086] refer to Figure 13 As shown, a second medium layer 136 is formed on the first medium layer 130. The second medium layer 136 is used to seal the first cavity 132 formed by removing the first isolation layer 112, and the second medium layer 136 is also used to seal the second cavity 134 formed by removing the third isolation layer 124. Figure 13 The dashed line indicates the interface between the first dielectric layer 130 and the second dielectric layer 136. This is only used to illustrate the relative positional relationship between the first dielectric layer 130 and the second dielectric layer 136, and does not imply that there is an actual interface between them. The second dielectric layer 136 includes a first portion 136a and a second portion 136b (e.g., ...). Figure 13 (as shown in the box in the middle) and Part 3 136c (as shown in the box in the middle) Figure 13 As shown in the middle circular frame, the second part 136b occupies a portion of the space formed after removing the first isolation layer 112, and the third part 136c occupies a portion of the space formed after removing the third isolation layer 124. In other words, the sum of the space occupied by the second part 136b and the space occupied by the first cavity 132 is the space occupied by the first isolation layer 112, and the sum of the space occupied by the third part 136c and the space occupied by the second cavity 134 is the space occupied by the third isolation layer 124. A portion of the second dielectric layer 136 (i.e., the second part 136b of the second dielectric layer) extends into the space formed after removing the first isolation layer 112, and a portion of the second dielectric layer 136 (i.e., the third part 136c of the second dielectric layer) extends into the space formed after removing the third isolation layer 124.

[0087] Still referring to Figure 13 As shown, the second dielectric layer 136 and the first dielectric layer 130 are etched in sequence along the Z direction to form a first conductive hole exposing the source region 126 and a second conductive hole exposing the drain region 128; and a conductive material is filled in the first conductive hole and the second conductive hole to form a first conductive column 138 and a second conductive column 140, respectively.

[0088] In some embodiments, the second dielectric layer 136 can also be etched along the Z direction to form a first recess exposing the first conductive column 138 and a second recess exposing the second conductive column 140; and a conductive material is filled in the first recess and the second recess to form a first conductive layer 142 and a second conductive layer 144, respectively; wherein the first conductive column 138 and the first conductive layer 142 together form a first lead-out structure 146, and the second conductive column 140 and the second conductive layer 144 together form a second lead-out structure 148. The first lead-out structure 146 can be referred to as a source lead-out structure, and the second lead-out structure 148 can be referred to as a drain lead-out structure.

[0089] In some embodiments, the second dielectric layer 136 can also be etched along the Z direction to form a third conductive hole exposing the gate conductive layer 106; a conductive material is filled in the third conductive hole to form a third conductive column; the second dielectric layer 136 is etched along the Z direction to form a third recess exposing the third conductive column; and a conductive material is filled in the third recess to form a third conductive layer; wherein the third conductive column and the third conductive layer together form a third lead-out structure, which can be referred to as a gate lead-out structure.

[0090] Reference Figure 14 , Figure 14 The utility model provides a block diagram of memory. As Figure 14 Shown, the utility model discloses a kind of memory, and the memory 200 includes: semiconductor structure 100 in the above technical solution.

[0091] Here, the memory 200 can include a cell array region and a peripheral circuit region located on at least one side of the cell array region. Here, the cell array region refers to a region for forming a cell array, for example, a region forming a memory cell array. The peripheral circuit region is provided on at least one side of the cell array region, for example, a side or a peripheral side. The peripheral circuit region refers to a region for forming a peripheral circuit.

[0092] In some embodiments, the memory 200 can include a dynamic random access memory (DRAM). A cell array region in the DRAM can include a plurality of memory cells including a transistor structure and a storage capacitor. A peripheral circuit region in the DRAM can include a plurality of transistor structures and other electronic elements (e.g., a capacitor or a resistor, etc.).

[0093] The semiconductor structure and the memory are provided in the embodiments of the present application. In the embodiments of the present application, the side wall of the gate structure is provided with an isolation structure, the isolation structure comprises a first cavity, a second cavity and an isolation layer arranged between the first cavity and the second cavity, the first cavity is arranged between the gate structure and the isolation layer and exposes the side wall of the gate structure, the risk of collapse of the semiconductor structure with the cavity can be reduced while the size of the cavity is increased, thereby the parasitic capacitance can be effectively reduced, the resistance-capacitance delay is improved, and the performance of the semiconductor structure is improved.

[0094] It should be understood that every technical feature mentioned in the specification refers to a specific feature, structure or property related to the embodiment, which is included in at least one embodiment of the present application. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or properties can be combined in one or more embodiments in any suitable manner. It should be understood that in various embodiments of the present application, the size of the sequence number of each process does not mean the order of execution, and the execution order of each process should be determined according to its function and inherent logic, and should not constitute any limitation on the implementation process of the embodiments of the present application. The sequence number of the above embodiments of the present application is only for description, not representing the advantages and disadvantages of the embodiments.

[0095] The above only describes the preferred embodiments of the present application, and does not limit the patent scope of the present application. Any equivalent structural transformation or direct / indirect application in other related technical fields within the concept of the present application, including the contents of the present application specification and drawings, is included in the patent protection scope of the present application.

Claims

1. A semiconductor structure, characterized by, The semiconductor structure comprises: a substrate; a gate structure disposed on one side of the substrate, the gate structure comprising a gate conductive layer and a gate dielectric layer disposed between the substrate and the gate conductive layer; an isolation structure disposed on opposite sides of the gate structure, the isolation structure comprising a first cavity, a second cavity, and an isolation layer disposed between the first cavity and the second cavity, the first cavity being disposed between the gate structure and the isolation layer and exposing a sidewall of the gate structure.

2. The semiconductor structure of claim 1, wherein, The semiconductor structure further comprises: a first dielectric layer disposed on one side of the substrate and on opposite sides of the gate structure, the isolation structure being disposed between the gate structure and the first dielectric layer, the second cavity being disposed between the isolation layer and the first dielectric layer.

3. The semiconductor structure of claim 2, wherein, The gate conductive layer, the isolation layer, and the first dielectric layer are flush with a surface of the substrate.

4. The semiconductor structure of claim 2, wherein, The semiconductor structure further comprises: a second dielectric layer disposed on a side of the gate structure, the isolation structure, and the first dielectric layer away from the substrate, the second dielectric layer being configured to seal the first cavity and the second cavity.

5. The semiconductor structure of claim 4, wherein, The second dielectric layer comprises a first portion, a second portion, and a third portion, the first portion being in contact with the first dielectric layer and the gate conductive layer; the second portion being in contact with the first portion and disposed between the gate structure and the isolation layer, the second portion being configured to seal the first cavity; the third portion being in contact with the first portion and disposed between the isolation layer and the first dielectric layer, the third portion being configured to seal the second cavity.

6. The semiconductor structure of claim 4, wherein, The semiconductor structure further comprises: a source region and a drain region disposed in the substrate and on opposite sides of the gate structure, respectively.

7. The semiconductor structure of claim 6, wherein, The semiconductor structure further comprises: a first conductive pillar extending through the second dielectric layer and the first dielectric layer and in contact with the source region; a second conductive pillar extending through the second dielectric layer and the first dielectric layer and in contact with the drain region.

8. The semiconductor structure of claim 6, wherein, The semiconductor structure further comprises: a first doped region and a second doped region disposed in the substrate and on opposite sides of the gate structure, respectively, the first doped region and the source region being disposed on a same side of the gate structure, a doping concentration of the first doped region being less than a doping concentration of the source region; the second doped region and the drain region being disposed on a same side of the gate structure, a doping concentration of the second doped region being less than a doping concentration of the drain region.

9. The semiconductor structure of claim 4, wherein, The first dielectric layer and the second dielectric layer are of a same material.

10. A memory, comprising: The memory comprises the semiconductor structure of any one of claims 1 to 9.

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