Phase change memory

Abstract

The utility model provides a phase change memory. The phase change memory comprises a phase change memory unit; the first barrier layer covers the side wall of the phase change storage unit; the second barrier layer covers one side, far away from the phase change memory unit, of the first barrier layer; at least one of the first barrier layer and the second barrier layer is of a laminated structure; the laminated structure comprises a first sub-barrier layer, a second sub-barrier layer and a thermal insulation layer located between the first sub-barrier layer and the second sub-barrier layer, and the thermal conductivity of the thermal insulation layer is smaller than that of the first sub-barrier layer and that of the second sub-barrier layer. The first barrier layer and the second barrier layer are used for protecting the side wall of the phase change memory unit, meanwhile, the first sub-barrier layer and / or the second sub-barrier layer with relatively high thermal conductivity are / is used for dissipating heat of the phase change memory unit, and the thermal insulation layer with relatively low thermal conductivity is used for insulating heat, so that the thermal field distribution uniformity of the phase change memory is improved, and the performance of the phase change memory is improved. Therefore, the problems of thermal crosstalk or write interference and the like caused by local crystallization or non-crystallization inversion are solved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, and particularly relates to a phase change memory. BACKGROUND

[0002] The phase change memory (PCM) relies on the current Joule heat to operate the phase change of the storage unit material between the crystalline state low resistance and the amorphous state high resistance, so as to realize the SET-RESET switching and complete the data storage. In order to ensure the complete reset of different units, a larger reset current is usually used, which is easy to cause the temperature increase of the adjacent units in the storage array in the process of RESET, and further cause the local crystallization or amorphization reversal of the phase change storage material, and cause the write interference.

[0003] It can be seen that the local crystallization or amorphization reversal caused by the uneven heat distribution is a problem to be solved for the phase change memory. CONTENT OF THE UTILITY MODEL

[0004] The present application aims to provide a phase change memory, and aims to improve the local crystallization or amorphization reversal caused by the uneven heat distribution of the phase change memory.

[0005] In order to solve the above problems, the technical scheme of the present application provides a phase change memory, comprising: a phase change storage unit; a first barrier layer covering the sidewall of the phase change storage unit; a second barrier layer covering one side of the first barrier layer away from the phase change storage unit; at least one of the first barrier layer and the second barrier layer is a laminated structure; the laminated structure comprises a first sub-barrier layer, a second sub-barrier layer and a heat insulation layer between the first sub-barrier layer and the second sub-barrier layer, and the thermal conductivity of the heat insulation layer is less than the thermal conductivity of the first sub-barrier layer and the second sub-barrier layer.

[0006] In some embodiments, the electrical conductivity of the heat insulation layer is less than the electrical conductivity of the first sub-barrier layer and the second sub-barrier layer.

[0007] In some embodiments, the heat insulation layer is a silicon carbonitride layer.

[0008] In some embodiments, the first sub-barrier layer is a silicon nitride layer; and the second sub-barrier layer is a silicon oxide layer.

[0009] In some embodiments, the distance from the first sub-barrier layer to the sidewall of the phase change storage unit is less than the distance from the second sub-barrier layer to the sidewall of the phase change storage unit.

[0010] In some embodiments, the phase change storage unit comprises a gating layer and a phase change storage layer arranged in a stack, and the first barrier layer covers the sidewall of the phase change storage layer.

[0011] In some embodiments, the phase change memory cell further comprises a second electrode layer between the gating layer and the phase change memory layer, a third electrode layer on a side of the phase change memory layer away from the second electrode layer, and a fourth conductive layer on a side of the third electrode layer away from the phase change memory layer; the first barrier layer is further on sidewalls of the second electrode layer, the third electrode layer and the fourth conductive layer.

[0012] In some embodiments, the third barrier layer covers the surface of the first barrier layer and the sidewall of the gating layer.

[0013] In some embodiments, the phase change memory cell further comprises a first conductive layer on a side of the gating layer away from the second electrode layer, and a first electrode layer between the gating layer and the first conductive layer; the second barrier layer is further on sidewalls of the first conductive layer and the first electrode layer.

[0014] In some embodiments, the phase change memory cell further comprises a third barrier layer covering the sidewall of the gating layer, and the second barrier layer is on the surface of the sidewall of the third barrier layer.

[0015] The present application provides a phase change memory, which uses a first barrier layer and a second barrier layer to protect the sidewall of a phase change memory cell from damage caused by etching process and subsequent processes. Meanwhile, at least one of the first barrier layer and the second barrier layer is a laminated structure, and the thermal conductivity of a thermal insulation layer in the laminated structure is lower than that of a first sub-barrier layer and a second sub-barrier layer. The phase change memory cell is cooled by the first sub-barrier layer and the second sub-barrier layer with relatively high thermal conductivity. Meanwhile, the phase change memory cell is thermally insulated by the thermal insulation layer with relatively low thermal conductivity, which can reduce the heat diffusion of the phase change memory cell to the outside, thereby helping the heat to diffuse along the first sub-barrier layer and the second sub-barrier layer. Thus, the thermal field distribution uniformity of the phase change memory can be further improved, thereby improving the problems of thermal crosstalk or write interference caused by local crystallization or amorphization reversal.

[0016] Other features and advantages of the present application will be described in detail in the following detailed description. BRIEF DESCRIPTION OF DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0018] For a more complete understanding of the present application and the advantages thereof, reference is now made to the following descriptions taken in connection with the accompanying drawings in which:

[0019] Figure 1 is a schematic diagram of a cross-sectional structure of a phase change memory according to an embodiment of the present application;

[0020] Figure 2 is a schematic diagram of a cross-sectional structure of another phase change memory according to some embodiments of the present application;

[0021] Figure 3 is a schematic diagram of a cross-sectional structure of yet another phase change memory according to some embodiments of the present application;

[0022] Figure 4 is a schematic diagram of a structure of a memory system according to some embodiments of the present application.

[0023] Legend of reference numerals:

[0024] 10, phase change memory cell; 11, first sub-blocking layer; 12, thermal isolation layer; 13, second sub-blocking layer;

[0025] 100, phase change memory; 101, first blocking layer; 102, second blocking layer; 103, gating layer; 104, phase change memory layer; 105, second electrode layer; 106, third electrode layer; 107, fourth conductive layer; 108, third conductive layer; 109, second adhesive layer; 110, first conductive layer; 111, first electrode layer; 112, first adhesive layer; 113, second conductive layer; 114, third blocking layer;

[0026] 200, controller;

[0027] 300, memory system. DETAILED DESCRIPTION

[0028] As described in the background section, local crystallization or amorphization reversal due to uneven heat distribution is a problem to be solved for phase change memories.

[0029] In the reset operation of the phase change memory, a large current is usually required to melt the phase change material into an amorphous state. When the phase change material in the phase change memory cell is in the amorphous state, the temperature is very high. At this time, due to heat diffusion, it is inevitable to cause the temperature of the phase change memory cell adjacent to the phase change memory cell in the amorphous state to rise, thereby causing the thermal disturbance (TDB) or write disturbance (WD) phenomenon. In addition, the phase change material in the phase change memory cell has the characteristic of low thermal conductivity, which will make the heat transfer in the phase change material uneven, causing the temperature of some areas to exceed the phase change point, but the temperature of other areas has not reached the phase change point, thereby affecting the overall heat storage or heat release efficiency of the phase change memory cell. If the phase change memory has the above uneven heat distribution for a long time, it may also accelerate the aging speed of the phase change medium in some parts of the phase change memory.

[0030] To solve the above problems, the embodiments of the present application provide a phase change memory and a storage system, so as to at least partially improve the above problems.

[0031] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor are within the protection scope of the present application.

[0032] In the description of the present application, it should be understood that the terms "upper", "lower" and the like indicate the orientation or positional relationship shown in the drawings, and are only for the purpose of facilitating the description of the present application and simplifying the description, and do not indicate or imply that the devices or elements indicated must have a particular orientation, be constructed and operated in a particular orientation, therefore cannot be understood as a limitation on the present application. In addition, the terms "first", "second" are only for the purpose of description, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features limited by "first", "second" can explicitly or implicitly include one or more of the features. In the description of the present application, the meaning of "multiple" is two or more, unless otherwise specifically limited.

[0033] As used herein, the term "layer" refers to a portion of material that includes a region having a thickness. A layer can extend over an entire underlying or overlying structure, or can have an area less than the area of the underlying or overlying structure. Further, a layer can be a region of a uniform or non-uniform continuous structure having a thickness that is less than the thickness of the continuous structure. For example, a layer can be between any set of horizontal planes between a top surface and a bottom surface of a continuous structure or at the top and bottom surfaces. Layers can extend horizontally, vertically, and / or along a tapered surface. A substrate can be a layer, which can include one or more layers, and / or can have one or more layers on, above and / or below it. A layer can include multiple layers. For example, an interconnect layer can include one or more electrically conductive layers and contact layers, and one or more dielectric layers.

[0034] It should be noted that the diagrams in the embodiments of the present application only schematically illustrate the basic concepts of the present application, and although only the components related to the present application are shown in the diagrams, the actual implementation is not drawn according to the number, shape and size of the components, and the actual implementation of each component can be arbitrarily changed in shape, number and proportion, and the layout pattern of the components can be more complex.

[0035] Please refer to Figure 1 , Figure 1 is a cross-sectional structure schematic diagram of a phase change memory provided by an embodiment of the present application. The phase change memory 100 can be applied to communication products, consumer electronic products, automotive products, aerospace products, artificial intelligence products or big data, etc. The consumer electronic products include, but are not limited to, mobile phones, computers, tablets, cameras, smart glasses or game products, etc.

[0036] The phase change memory 100 includes: a phase change memory cell 10; a first barrier layer 101 covering the sidewall of the phase change memory cell 10; a second barrier layer 102 covering one side of the first barrier layer 101 away from the phase change memory cell 10; at least one of the first barrier layer 101 and the second barrier layer 102 is a laminated structure; the laminated structure includes a first sub-barrier layer 11, a second sub-barrier layer 13, and a thermal insulation layer 12 between the first sub-barrier layer 11 and the second sub-barrier layer 13, the thermal conductivity of the thermal insulation layer 12 is less than the thermal conductivity of the first sub-barrier layer 11 and the second sub-barrier layer 13.

[0037] The application sets the first barrier layer 101 and the second barrier layer 102 in sequence on the sidewall of the phase change memory cell 10, protects the sidewall of the phase change memory cell 10 by the first barrier layer 101 and the second barrier layer 102, so as to avoid damage caused by etching process and subsequent process. Meanwhile, at least one of the first barrier layer 101 and the second barrier layer 102 is a laminated structure, and the thermal conductivity of the heat insulation layer 12 in the laminated structure is less than that of the first sub-barrier layer 11 and the second sub-barrier layer 13. In this way, the first sub-barrier layer 11 and / or the second sub-barrier layer 13 with relatively high thermal conductivity can be used to dissipate heat of the phase change memory cell 10; meanwhile, the heat insulation layer 12 with relatively low thermal conductivity can be used for heat insulation, which can reduce the heat diffusion of the phase change memory cell 10 to the outside, thereby helping to diffuse heat along the first sub-barrier layer 11 and the second sub-barrier layer 13. Thus, the thermal field distribution uniformity of the phase change memory 100 can be further improved, so as to improve the problems of thermal crosstalk or write interference caused by local crystallization or amorphization reversal.

[0038] In addition, in the embodiment of the application, the heat insulation layer 12 is located between the first sub-barrier layer 11 and the second sub-barrier layer 13, which not only can dissipate heat generated by the phase change memory cell 10 in time by the first sub-barrier layer 11, but also can dissipate heat transmitted through the heat insulation layer 12 by the second sub-barrier layer 13, or dissipate heat generated by the phase change memory cell 10 in time by the second sub-barrier layer 13 and dissipate heat transmitted through the heat insulation layer 12 by the first sub-barrier layer 11, both of which can achieve the effect of double heat dissipation.

[0039] The application will be described in detail below with reference to the accompanying drawings.

[0040] Please continue to refer to Figure 1 In the embodiment, the second barrier layer 102 is the laminated structure, and the first barrier layer 101 is a non-laminated structure. The first barrier layer 101 is used to prevent the phase change material in the phase change memory cell 10 from diffusing and evaporating during the heating process, and to dissipate heat of the phase change memory cell 10 to a certain extent. Meanwhile, the first sub-barrier layer 11 and the second sub-barrier layer 13 in the second barrier layer 102 are used for heat dissipation. In addition, the heat insulation layer 12 is arranged between the first sub-barrier layer 11 and the second sub-barrier layer 13, which can be used for heat insulation. On the one hand, it can reduce the heat transferred to the adjacent phase change memory cell 10, and on the other hand, it can help to diffuse heat along the first sub-barrier layer 11 and the second sub-barrier layer 13, thereby improving the situation of local crystallization or amorphization reversal caused by uneven heat distribution.

[0041] In some embodiments of the application, the electrical conductivity of the heat insulation layer 12 is less than that of the first sub-barrier layer 11 and the second sub-barrier layer 13.

[0042] In the phase change memory 100, the first sub-blocking layer 11 and the second sub-blocking layer 13 mainly function to control the resistance value of the phase change memory cell 10, and thus the electrical conductivity of the first sub-blocking layer 11 and the second sub-blocking layer 13 is closely related to the performance of the phase change memory 100. In the embodiments of the present application, the electrical conductivity of the thermal insulation layer 12 is made to be less than that of the first sub-blocking layer 11 and the second sub-blocking layer 13, so that in the un-changed phase state, the resistance of the first sub-blocking layer 11 and the second sub-blocking layer 13 is low, and it is easier to form a low impedance state, and when phase change occurs, for example, from a solid state to a lattice structure with lower resistance, the electrical conductivity of the first sub-blocking layer 11 and the second sub-blocking layer 13 is enhanced, while the thermal insulation layer 12, due to its low electrical conductivity, plays a role in stabilizing the phase change region during the phase change process, and prevents excessive current loss. In this way, the phase change process can be triggered by a small change in voltage, and the reading and writing of information of the phase change memory 100 can be effectively controlled. In addition, the relatively high electrical conductivity of the first sub-blocking layer 11 and the second sub-blocking layer 13 also helps to reduce power consumption and improve the overall performance of the storage device.

[0043] Please continue to refer to Figure 1 In some embodiments of the present application, the distance from the first sub-blocking layer 11 to the sidewall of the phase change memory cell 10 is less than the distance from the second sub-blocking layer 13 to the sidewall of the phase change memory cell 10.

[0044] In some embodiments of the present application, the thermal conductivity of the first sub-blocking layer 11 is greater than the thermal conductivity of the second sub-blocking layer 13.

[0045] The thermal conductivity of a material is closely related to its heat dissipation effect, and a material with high thermal conductivity can more effectively transfer heat from one location to another, thereby improving heat dissipation performance. In the embodiments of the present application, the thermal conductivity of the first sub-blocking layer 11 is made to be greater than that of the second sub-blocking layer 13, so that the heat generated by the phase change memory cell 10 can be quickly dissipated by the first sub-blocking layer 11 with high thermal conductivity, thereby avoiding or reducing the impact on adjacent phase change memory cells 10. Since the thermal insulation layer 12 is provided between the first sub-blocking layer 11 and the second sub-blocking layer 13, the heat transferred from the first sub-blocking layer 11 to the second sub-blocking layer 13 through the thermal insulation layer 12 is already small, and thus the second sub-blocking layer 13 does not need to use a material with high thermal conductivity, and can use a material with relatively low thermal conductivity.

[0046] In some embodiments of the present application, the electrical conductivity of the first sub-blocking layer 11 is greater than the electrical conductivity of the second sub-blocking layer 13.

[0047] In the embodiments of the present application, the first barrier layer 101 is arranged on the sidewall of the phase change memory cell 10, and the first barrier layer 101 comprises a first sub-barrier layer 11. Therefore, by using the first sub-barrier layer 11 with relatively high conductivity, the solid-liquid conversion of the phase change material can be quickly responded and accurately adjusted. When data needs to be written, the high conductivity can help to activate the phase change process, so that the material enters a low resistance state. The second sub-barrier layer 13 has a conductivity smaller than that of the first sub-barrier layer 11, which can protect the phase change layer from external current, keep the phase change point stable, and prevent unnecessary heat accumulation, thereby ensuring long-term storage of the stored information.

[0048] In the phase change memory 100, the first barrier layer 101 and the second barrier layer 102 are arranged on the sidewall of the phase change memory cell 10 stack structure. The main function is to protect the phase change memory 100 and / or the oscillation threshold switch, prevent the phase change memory 100 and / or the oscillation threshold switch from being oxidized, and perform heat insulation or rapid heat dissipation. In the SET-RESET process of the phase change memory 100, unreasonable heat field distribution will cause write interference. Therefore, the selection of the material of the first barrier layer 101 and the second barrier layer 102 is crucial.

[0049] In some embodiments of the present application, the heat insulation layer 12 is a silicon carbonitride layer.

[0050] The thermal conductivity and electrical conductivity of silicon carbonitride are both small, and it has high thermal stability. The mass change is stable under high temperature conditions (1200℃), which can improve the poor heat dissipation effect of the phase change memory 100 in the related art, and the poor heat insulation effect of the first barrier layer 101 and the second barrier layer 102 in the phase change memory 100.

[0051] It can be understood that the material of the heat insulation layer 12 in the above embodiments is silicon carbonitride, which is only an example. The material of the heat insulation layer 12 in the present application is not limited to this.

[0052] In some embodiments of the present application, the first sub-barrier layer 11 is a silicon nitride layer, and the second sub-barrier layer 13 is a silicon oxide layer.

[0053] The thermal conductivity of silicon nitride and silicon oxide is relatively large, which can quickly dissipate the heat generated in the phase change memory 100. In addition, the electrical conductivity of silicon nitride and silicon oxide is also relatively large, which can help to transmit the current to the phase change material, improve the heating efficiency, and also reduce the heat diffused to the electrode, thereby retaining more heat for heating the phase change material, reducing the write energy consumption, and improving the performance of the phase change memory 100.

[0054] It can be understood that the material of the first sub-blocking layer 11 and the material of the second sub-blocking layer 13 in the above embodiments are silicon nitride and silicon oxide respectively, which are only examples, and the materials of the first sub-blocking layer 11 and the second sub-blocking layer 13 in the present application are not limited thereto.

[0055] Please continue to refer to Figure 1 In some embodiments of the present application, the phase change memory cell 10 comprises a selection layer 103 and a phase change layer 104 which are arranged in a stack.

[0056] In the phase change memory 100, the function of the selection layer 103 is to select or read a specific memory cell in the memory array. The opening and closing process of the selection layer 103 is roughly as follows: the opening and closing of the selection layer 103 is controlled by an electrical signal, when the electrical signal is applied to the selection layer 103, the selection layer 103 changes from a high resistance state to a low resistance state, at this time the selection layer 103 is in an open state; when the electrical signal is removed, the selection layer 103 changes from a low resistance state to a high resistance state, and the selection layer 103 is in a closed state. In the embodiments of the present application, the material of the selection layer 103 includes an Ovonic Threshold Switch (OTS) material, such as ZnxTey, GexTey, NbxOy or SixAsyTez. The Ovonic Threshold Switch material can realize the switching between the high resistance state and the low resistance state under the control of the electrical signal, thereby realizing the switching control of the current.

[0057] Please continue to refer to Figure 1 In some embodiments of the present application, the first blocking layer 101 covers the sidewall of the phase change layer 104.

[0058] The basic principle of the phase change memory 100 is to use the Joule heat generated under the action of electricity to make the phase change material convert between amorphous state (high resistance) and polycrystalline state (low resistance), and to record information by using the different resistance values in the two states. Therefore, the conversion between the amorphous state and the polycrystalline state of the phase change material is crucial to the phase change memory 100. In the embodiments of the present application, the first blocking layer 101 is arranged on the sidewall of the phase change layer 104, which can prevent the phase change material from diffusing or evaporating during the heating process, protect the integrity of the phase change material, and thus protect the stability of the performance of the phase change memory 100.

[0059] Please continue to refer to Figure 1In some embodiments of the present application, the phase change memory cell 10 further comprises a second electrode layer 105 between the gating layer 103 and the phase change memory layer 104, a third electrode layer 106 on the side of the phase change memory layer 104 away from the second electrode layer 105, and a fourth conductive layer 107 on the side of the third electrode layer 106 away from the phase change memory layer 104; the first barrier layer 101 is further on the sidewalls of the second electrode layer 105, the third electrode layer 106 and the fourth conductive layer 107.

[0060] In the embodiments of the present application, the first barrier layer 101 is arranged on the sidewalls of the second electrode layer 105, the third electrode layer 106 and the fourth conductive layer 107 in the phase change memory 100, and the first barrier layer 101 is used to prevent the phase change substance from diffusing uncontrollably to the electrode layer or the surrounding environment under the action of temperature fluctuation or stress, and meanwhile, the subsequent process of the sidewalls of the second electrode layer 105, the third electrode layer 106 and the fourth conductive layer 107 is prevented from damaging the sidewalls and affecting the performance of the phase change memory 100.

[0061] Please continue to refer to Figure 1 In some embodiments of the present application, the phase change memory cell 10 further comprises a third conductive layer 108 between the phase change memory layer 104 and the third electrode layer 106, and a second adhesive layer 109 between the third electrode layer 106 and the fourth conductive layer 107; the first barrier layer 101 is further on the sidewalls of the third conductive layer 108 and the second adhesive layer 109.

[0062] In the embodiments of the present application, the second adhesive layer 109 is arranged between the third electrode layer 106 and the fourth conductive layer 107 to make the third electrode layer 106 and the fourth conductive layer 107 adhere more closely, and the second barrier layer 102 is arranged on the sidewalls of the third conductive layer 108 and the second adhesive layer 109 to protect the sidewalls of the third conductive layer 108 and the second adhesive layer 109, so as to prevent the sidewalls from being damaged in the subsequent process and affecting the performance of the phase change memory 100.

[0063] Please continue to refer to Figure 1 In some embodiments of the present application, the second barrier layer 102 covers the surface of the first barrier layer 101 and the sidewalls of the gating layer 103. In this way, the sidewalls of the gating layer 103 can be protected by the second barrier layer 102, so as to prevent the sidewalls from being damaged in the subsequent process and affecting the performance of the phase change memory 100.

[0064] Please continue to refer to Figure 1In some embodiments of the present application, the phase change memory cell 10 further comprises a first conductive layer 110 located on the side of the gating layer 103 away from the second electrode layer 105, and a first electrode layer 111 located between the gating layer 103 and the first conductive layer 110; the second barrier layer 102 is further located on the sidewall of the first conductive layer 110 and the sidewall of the first electrode layer 111. In this way, the sidewall of the first conductive layer 110 and the first electrode layer 111 can be protected by the second barrier layer 102, so as to avoid damage to the sidewall of the first conductive layer 110 and the first electrode layer 111 in subsequent processes, and affect the performance of the phase change memory 100.

[0065] In the embodiments of the present application, the phase change memory 100 comprises the first electrode layer 111, the second electrode layer 105 and the third electrode layer 106, and the materials of the first electrode layer 111, the second electrode layer 105 and the third electrode layer 106 can be the same or different, and can be selected from one or more of C, Ta, TiN, TaC, TaN, Co, W, Pt, Au, Ti, Al, Ag, Cu and Ni.

[0066] Please continue to refer to Figure 1 In some embodiments of the present application, the phase change memory cell 10 further comprises a first adhesive layer located between the first electrode layer 111 and the first conductive layer 110, and a second conductive layer 113 located between the phase change memory layer 104 and the second electrode layer 105; the second barrier layer 102 is further located on the sidewall of the first adhesive layer 112, and the first barrier layer 101 is further located on the sidewall of the second conductive layer 113.

[0067] In the embodiments of the present application, the first electrode layer 111 and the first conductive layer 110 are adhered more closely by setting the first adhesive layer 112 between the first electrode layer 111 and the first conductive layer 110. The sidewall of the first adhesive layer 112 is provided with the second barrier layer 102, so as to protect the sidewall by the second barrier layer 102, avoid damage to the sidewall in subsequent processes, and affect the performance of the phase change memory 100. The first barrier layer 101 is provided on the sidewall of the second conductive layer 113, and details are not described herein.

[0068] In the embodiments of the present application, the phase change memory 100 comprises the first adhesive layer 112 and the second adhesive layer 109, and the materials of the first adhesive layer 112 and the second adhesive layer 109 can be metal materials, such as tungsten silicon nitride (WSiN), but are not limited thereto.

[0069] The embodiments of the present application further provide another phase change memory, please refer to Figure 2 , Figure 2is another schematic diagram of a cross-sectional structure of a phase change memory provided by some embodiments of the present application. In the present embodiment, the first barrier layer 101 is the stacked structure.

[0070] In the present embodiment, the first barrier layer 101 is the stacked structure, while the second barrier layer 102 is a non-stacked structure. The first barrier layer 101 is closer to the phase change memory cell 10 than the second barrier layer 102, and therefore, the first barrier layer 101 has a better heat dissipation effect than the second barrier layer 102 which is the stacked structure. Similarly, the heat insulation effect of the heat insulation layer 12 arranged between the first sub-barrier layer 11 and the second sub-barrier layer 13 is also better, which can effectively reduce the heat transferred to the adjacent phase change memory cell 10, and help more heat to diffuse along the first sub-barrier layer 11 and the second sub-barrier layer 13, thereby improving the situation of local crystallization or amorphization reversal caused by uneven heat distribution.

[0071] Please refer to Figure 3 , Figure 3 is another schematic diagram of a cross-sectional structure of a phase change memory provided by some embodiments of the present application. In the present embodiment, the first barrier layer 101 and the second barrier layer 102 are both the stacked structure.

[0072] With such a scheme, not only can the first sub-barrier layer 11 and the second sub-barrier layer 13 in the first barrier layer 101 be used for heat dissipation, but also the first sub-barrier layer 11 and the second sub-barrier layer 13 in the second barrier layer 102 can be used for heat dissipation, achieving fourfold heat dissipation and good heat dissipation effect. In addition, the heat insulation layer 12 in the first barrier layer 101 and the heat insulation layer 12 in the second barrier layer 102 achieve double heat insulation, which can effectively reduce the heat transferred to the adjacent phase change memory cell 10, thereby improving the situation of local crystallization or amorphization reversal caused by uneven heat distribution.

[0073] In some embodiments of the present application, a fourth barrier layer (not shown in the figure) is arranged between the first barrier layer 101 and the second barrier layer 102, and the fourth barrier layer covers the side of the first barrier layer 101 away from the phase change memory cell 10. In the stacking direction of the phase change memory cell 10, the fourth barrier layer has the same height as the first barrier layer 101.

[0074] Please continue to refer to Figure 3 In some embodiments of the present application, the phase change memory cell 10 further comprises a third barrier layer 114 covering the sidewall of the selection layer 103, and the second barrier layer 102 is located on the sidewall surface of the third barrier layer 114.

[0075] In the embodiments of the present application, the third barrier layer 114 is arranged on the sidewall of the gating layer 103, and the third barrier layer 114 can be used to block the outward diffusion of elements in the gating layer 103. Meanwhile, the second barrier layer 102 is arranged on the sidewall of the third barrier layer 114, so that the coverage performance of the second barrier layer 102 is enhanced.

[0076] Please refer to Figure 4 , Figure 4 is a structural schematic diagram of a storage system provided by some embodiments of the present application. The storage system 300 includes a plurality of phase change memories 100 and a controller 200. The phase change memories 100 can be any of the phase change memories in the above embodiments. The controller 200 is connected with the phase change memories 100 and is configured to control the phase change memories 100 to store data. The phase change memories 100 can perform the operation of storing data based on the control of the controller 200.

[0077] In some embodiments of the present application, the storage system 300 can be implemented as a universal flash storage (UFS) device, a solid state disk (SSD), a multimedia card in the form of an RS-MMC, an eMMC, an MMC, a micro-SD, a secure digital card in the form of an SD, a mini-SD or a micro-SD, a storage device in the form of a personal computer memory card international association (PCMCIA) card, a storage device in the form of a peripheral component interconnect (PCI), a storage device in the form of a high-speed PCI (PCI-E), a compact flash (CF) card, a smart media card or a memory stick, etc.

[0078] In the description of the present application, the terms “first” and “second” are only used for the purpose of description and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined with “first” and “second” can explicitly or implicitly include one or more features. In the description of the present application, the meaning of “a plurality of” is two or more, unless otherwise specifically limited.

[0079] In the above embodiments, the description of each embodiment is focused on, and the parts not described in detail in a certain embodiment can be referred to the related description of other embodiments.

[0080] The embodiments, implementation manners and related technical features of the present application can be combined or replaced with each other without conflict.

[0081] The above is only the preferred embodiments of the present application, and does not limit the present application in any form. Any simple modification, equivalent change and modification made to the above embodiments based on the technical essence of the present application, without departing from the technical solution of the present application, still falls within the scope of the technical solution of the present application.

Claims

1. A phase change memory, characterized by, The application relates to a phase change memory cell, comprising: a phase change memory cell; a first barrier layer covering the sidewall of the phase change memory cell; a second barrier layer covering one side of the first barrier layer away from the phase change memory cell; at least one of the first barrier layer and the second barrier layer is a laminated structure; the laminated structure comprises a first sub-barrier layer, a second sub-barrier layer and a heat insulation layer between the first sub-barrier layer and the second sub-barrier layer, and the heat conductivity of the heat insulation layer is smaller than that of the first sub-barrier layer and the second sub-barrier layer.

2. The phase change memory of claim 1, wherein, The electrical conductivity of the heat insulation layer is smaller than that of the first sub-barrier layer and the second sub-barrier layer.

3. The phase change memory of claim 1, wherein, The heat insulation layer is a silicon carbon nitride layer.

4. The phase change memory of any one of claims 1 to 3, wherein, The first sub-barrier layer is a silicon nitride layer; and the second sub-barrier layer is a silicon oxide layer.

5. The phase change memory of claim 1, wherein, The distance from the first sub-barrier layer to the sidewall of the phase change memory cell is smaller than that from the second sub-barrier layer to the sidewall of the phase change memory cell.

6. The phase change memory of claim 1, wherein, The phase change memory cell comprises a selection layer and a phase change memory layer arranged in layers, and the first barrier layer covers the sidewall of the phase change memory layer.

7. The phase change memory of claim 6, wherein, The phase change memory cell further comprises a second electrode layer between the selection layer and the phase change memory layer, a third electrode layer on one side of the phase change memory layer away from the second electrode layer, and a fourth conductive layer on one side of the third electrode layer away from the phase change memory layer; and the first barrier layer further covers the sidewall of the second electrode layer, the sidewall of the third electrode layer and the sidewall of the fourth conductive layer.

8. The phase change memory of claim 7, wherein, The second barrier layer covers the surface of the first barrier layer and the sidewall of the selection layer.

9. The phase change memory of claim 7, wherein, The phase change memory cell further comprises a first conductive layer on one side of the selection layer away from the second electrode layer, and a first electrode layer between the selection layer and the first conductive layer; and the second barrier layer further covers the sidewall of the first conductive layer and the sidewall of the first electrode layer.

10. The phase change memory of claim 6, wherein, The phase change memory cell further comprises: a third barrier layer covering the sidewall of the selection layer, and the second barrier layer covers the surface of the sidewall of the third barrier layer.

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