Electronic package
By setting a thermally uniform interlayer on the encapsulation layer and creating a cutout on it, and using a laser beam to transfer heat through the cutout, the problems of overheating and scorching of the encapsulation layer and unwetting of solder are solved, achieving uniform heating of the solder bumps and improving the encapsulation quality.
Patent Information
- Application Number
- CN202423055131.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Priority Date
- 2024-02-27
- Filing Date
- 2024-12-11
- Publication Date
- 2025-11-11
- Estimated Expiration
- 2034-12-11
AI Technical Summary
In existing semiconductor packaging processes using laser-assisted bonding, the packaging layer is prone to overheating and burning, resulting in insufficient heat energy for the solder bumps and causing the solder to fail to wet.
A thermally uniform interlayer is used to cover the encapsulation layer, and a cutout is provided on it to expose electronic components. A laser beam is used to pass through the cutout to transfer heat energy to the solder bumps, and the solder bumps are heated uniformly through the support structure.
This avoids the problem of overheating and burning of the encapsulation layer, ensures uniform heating of the solder bumps, prevents solder from not being wetted, and improves the encapsulation quality.
Smart Images
Figure CN223539590U_ABST
Abstract
Description
Technical Field
[0001] This application relates to a semiconductor device, and more particularly to an electronic package that can improve product yield. Background Technology
[0002] With the evolution of technology, the demand for electronic products is trending towards high-end products with high-density circuitry, high transmission speeds, high stack-up counts, and large-size designs. As chip sizes increase and the number of I / O points grows, these products become more sensitive to thermal responses. Therefore, thermal processes in packaging, such as reflow processes, are highly susceptible to warping due to the different coefficients of thermal expansion (CTE) between materials. Furthermore, the concentration of thermal stress within the structure can lead to reliability issues.
[0003] like Figure 1 As shown, in the existing method for manufacturing a flip-chip semiconductor package 1, a semiconductor chip 11 is first bonded to a circuit structure 10 via multiple conductive bumps 13. Then, an adhesive base 12 is formed between the semiconductor chip 11 and the circuit structure 10 to cover the conductive bumps 13. An encapsulation layer 14 is then formed on the circuit structure 10 to cover the semiconductor chip 11. Subsequently, multiple copper pillars 100 and solder bumps 150 are formed on the underside of the circuit structure 10 to attach the circuit structure 10 to a substrate 15 via the solder bumps 150.
[0004] Currently, the methods for attaching the solder bump 150 include reflow soldering and laser-assisted bonding (LAB). In the LAB method, a laser beam L is mainly used to irradiate the solder bump 150 to transfer energy to it, causing the solder bump 150 to melt immediately and then harden, so that the semiconductor chip 11 is bonded to the substrate 15 through the circuit structure 10.
[0005] Existing LAB processes can selectively heat local areas and have the characteristic of rapid temperature rise, thus reducing the time of thermal processes and reducing the concentration of thermal stress inside the structure. Furthermore, by controlling the laser wavelength and the characteristics of local heating, the degree of warpage can be reduced.
[0006] However, in the existing semiconductor package 1 manufacturing method, during the LAB process, when the laser beam L irradiates the package layer 14, the package layer 14 is prone to overheating and burning. This makes it difficult for the heat energy that the laser beam L intends to transfer to the solder bump 150 below the package layer 14 to be transferred through the circuit structure 10, thus easily causing the disadvantage of insufficient heat energy and solder non-wetting. Figure 1 The peripheral area B shown is experiencing solder shrinkage or empty solder joints.
[0007] Therefore, overcoming the problems of the existing technology has become an urgent issue that needs to be addressed. Utility Model Content
[0008] In view of the various deficiencies of the prior art, this application provides an electronic package, including: a carrier structure; an electronic component disposed on the carrier structure; an encapsulation layer disposed on the carrier structure and covering the electronic component; a thermally uniform interlayer covering the encapsulation layer and at least partially exposing the electronic component; and a substrate that is connected to the carrier structure by a plurality of solder bumps.
[0009] This application also provides a method for manufacturing an electronic package, comprising: providing a carrier structure having an electronic component and a packaging layer surrounding the electronic component; covering the packaging layer with a thermally uniform interlayer, wherein the thermally uniform interlayer at least partially exposes the electronic component; and attaching the carrier structure to a substrate via a plurality of solder bumps, and irradiating the electronic component with a laser beam passing through the cutout portion, so as to transfer the heat energy of the laser beam to the plurality of solder bumps.
[0010] In the aforementioned electronic package and its manufacturing method, the thermally uniform interlayer is a semiconductor material.
[0011] In the aforementioned electronic package and its manufacturing method, the thermally uniform interlayer has at least one cutout corresponding to the electronic component, allowing the electronic component to be exposed through the cutout. For example, the area of the cutout corresponds to the area of the exposed surface of the electronic component. Furthermore, the spacing between the thermally uniform interlayer and the package layer, as well as the size of the cutout, are determined according to the thermal energy of the laser beam irradiating the electronic package and the density of the conductive bumps disposed on the carrier structure for the electronic component.
[0012] In the aforementioned electronic package and its manufacturing method, the thermally uniform interlayer is spaced above the electronic component and the supporting structure.
[0013] As can be seen from the above, in the electronic package and its manufacturing method of this application, the configuration of the thermally uniform interlayer mainly enables the laser beam to irradiate the electronic component and the carrier structure but not the package layer. The heat energy of the laser beam can be transferred to the corresponding area below the package layer through the carrier structure. At the same time, the thermally uniform interlayer absorbs the energy of the laser beam and converts it into radiant heat, which is conducted to the package layer below through the air, thereby uniformly heating the solder bumps. Therefore, compared with the prior art, this application can not only avoid the problem of the package layer being easily burned due to overheating, but also avoid the problem of solder non-wetting on the solder bumps. Attached Figure Description
[0014] Figure 1 This is a cross-sectional schematic diagram of an existing flip-chip semiconductor package.
[0015] Figures 2A to 2C This is a cross-sectional schematic diagram illustrating the manufacturing method of the electronic package of this application.
[0016] Figure 3A for Figure 2A A partial top view diagram.
[0017] Figure 3B for Figure 2B A partial top view diagram.
[0018] Figure 4 This is a cross-sectional schematic diagram of another embodiment of the electronic package of this application.
[0019] Explanation of reference numerals in the attached figures
[0020] 1 Semiconductor package
[0021] 10. Circuit Structure
[0022] 100 bronze pillars
[0023] 11 Semiconductor chips
[0024] 12.22 base rubber
[0025] 13,23,23' Conductive bumps
[0026] 14,24 encapsulation layers
[0027] 15,25 base plate
[0028] 150, 250 solder bumps
[0029] 2 Electronic Packages
[0030] 20 Load-bearing structure
[0031] 200 conductive elements
[0032] 21,21' Electronic components
[0033] 21a Working surface
[0034] 21b Non-operating surface
[0035] 24a First Surface
[0036] 24b Second Surface
[0037] 8,8' Thermally Uniform Intermediate Layer
[0038] 80,80' Openwork section
[0039] L laser beam
[0040] S represents the interval distance. Detailed Implementation
[0041] The following specific embodiments illustrate the implementation of this application. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification.
[0042] It should be understood that the structures, proportions, sizes, etc., depicted in the accompanying drawings are merely for illustrative purposes to aid those skilled in the art in understanding and reading the content disclosed herein, and are not intended to limit the scope of this application. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in proportions, or adjustments to size, without affecting the effectiveness and purpose of this application, should still fall within the scope of the technical content disclosed herein. Furthermore, the terms such as "above," "first," "second," and "one" used in this specification are merely for clarity of description and are not intended to limit the scope of this application. Changes or adjustments to their relative relationships, without substantially altering the technical content, should also be considered within the scope of this application's implementation.
[0043] Figures 2A to 2C This is a cross-sectional schematic diagram illustrating the manufacturing method of the electronic package 2 of this application.
[0044] like Figure 2A As shown, a chip package is provided, which includes a carrier structure 20 and at least one electronic component 21.
[0045] The carrier structure 20 may be, for example, a packaging substrate with a core layer and circuit structure, a packaging substrate with a coreless circuit structure, a silicon interposer (TSI) with through-silicon vias (TSVs), or other board types, comprising at least one insulating layer and at least one circuit layer bonded to the insulating layer, such as at least one fan-out redistribution layer (RDL). It should be understood that the carrier structure 20 may also be other board materials for carrying chips, such as leadframes, wafers, or other boards with metal routing, and is not limited to the above.
[0046] In this embodiment, the carrier board of the supporting structure 20 can be fabricated in various ways. For example, the circuit layer can be fabricated using a wafer fabrication process, and silicon nitride or silicon oxide can be formed as an insulating layer by chemical vapor deposition (CVD). Alternatively, the circuit layer can be formed using a general non-wafer fabrication process, that is, using a low-cost polymer dielectric material as an insulating layer, such as polyimide (PI), polybenzoxazole (PBO), prepreg (PP), molding compound, photosensitive dielectric layer or other materials, etc., formed by coating.
[0047] The electronic component 21 is disposed on the upper side of the support structure 20 and is an active component, a passive component, or a combination thereof, wherein the active component is, for example, a semiconductor chip, and the passive component is, for example, a resistor, a capacitor, and an inductor.
[0048] In this embodiment, the electronic component 21 is a semiconductor chip with opposing active surfaces 21a and non-active surfaces 21b. The electrode pads of the active surface 21a are disposed on the carrier structure 20 via multiple conductive bumps 23, such as solder, metal pillars, or other materials, in a flip-chip manner and electrically connected to the circuit layer of the carrier structure 20. Then, an adhesive base 22 is formed between the electronic component 21 and the carrier structure 20 to cover the conductive bumps 23. Alternatively, the electronic component 21 can be electrically connected to the circuit layer of the carrier structure 20 via multiple bonding wires (not shown) in a wire bonding manner. Or, the electronic component 21 can directly contact the circuit layer of the carrier structure 20. Therefore, a desired type and number of electronic components can be attached to the carrier structure 20 to improve its electrical function, and there are many ways to electrically connect the electronic component 21 to the carrier structure 20, not limited to the above.
[0049] Next, an encapsulation layer 24 is formed on the carrier structure 20 so that the encapsulation layer 24 covers the electronic components 21 and the base adhesive 22.
[0050] In this embodiment, the material forming the encapsulation layer 24 is an insulating material, such as a polyimide (PI) or epoxy resin encapsulant, which can be formed by molding, lamination or coating.
[0051] Furthermore, the encapsulation layer 24 has opposing first surfaces 24a and second surfaces 24b, with the carrier structure 20 bonded to the first surface 24a. The non-functional surface 21b of the electronic component 21 is flush with the second surface 24b of the encapsulation layer 24, so that the non-functional surface 21b of the electronic component 21 is exposed to the second surface 24b of the encapsulation layer 24. Alternatively, the encapsulation layer may also cover the non-functional surface 21b of the electronic component 21, making the second surface of the encapsulation layer higher than the non-functional surface 21b of the electronic component 21. It should be understood that a leveling process, such as grinding, cutting, or etching, can be used to obtain the desired result. Figure 2B The state of the encapsulation layer 24 is shown.
[0052] Furthermore, the supporting structure 20 has a plurality of conductive elements 200 formed on its lower side, and a plurality of solder bumps 250 provided thereon for use as contacts. Specifically, the conductive elements 200 may be metal pillars such as copper pillars or other conductive structures.
[0053] like Figure 2B As shown, the carrier structure 20 is attached to a substrate 25, and at least one thermally uniform interposer 8 is provided above the chip package to cover the package layer 24. The thermally uniform interposer 8 has at least one cutout portion 80 corresponding to the electronic component 21, so that at least a portion of the non-functional surface 21b of the electronic component 21 is exposed to the cutout portion 80.
[0054] In this embodiment, the thermally uniform interposer 8 is a semiconductor material, such as a silicon wafer, and is spaced apart from the encapsulation layer 24.
[0055] Please refer to the following at the same time. Figure 3A and Figure 3B , it is Figure 2A and Figure 2B The partial top view shows that the areas of the cutouts 80 may be the same or different, and the area of the cutouts 80 may correspond to (e.g., equal to or less than) the area of the exposed surface (e.g., non-functional surface 21b) of the electronic component 21. For example, the projected area of the thermally uniform interposer 8 in the vertical direction is equal to the projected area of the outline of the encapsulation layer 24 in the vertical direction.
[0056] Furthermore, the substrate 25 may be, for example, a packaging substrate with a core layer and a circuit structure, or a packaging substrate with a coreless circuit structure, which includes at least one insulating layer and at least one circuit layer bonded to the insulating layer, such as at least one fan-out redistribution layer (RDL).
[0057] like Figure 2CAs shown, laser-assisted bonding (LAB) is used to irradiate the electronic component 21 and the carrier structure 20 through the cutout portion 80, so that heat energy is transferred to the solder bump 250 through the electronic component 21, the carrier structure 20 and the thermally uniform interlayer 8, so that the electronic component 21 is bonded to the substrate 25 through the carrier structure 20.
[0058] In application, the spacing between the thermally uniform interlayer 8 and the encapsulation layer 24, as well as the size of the cutout portion 80, can be adjusted according to the thermal energy of the laser beam L and the arrangement density of the conductive bumps 23.
[0059] like Figure 4 As shown, in another embodiment of the electronic package 2 of this application, the spacing S between the thermally uniform interlayer 8' and the package layer 24 and the size of the cutout portion 80' can be varied in accordance with the thermal energy of the laser beam L and the density of the conductive bumps 23' arranged on the support structure 20 for the electronic components 21'.
[0060] Therefore, the electronic package of this application, through the configuration of the thermally uniform interposer 8, blocks the laser beam L relative to the package layer 24, allowing the laser beam L to pass through the cutout 80 to irradiate the electronic component 21 without directly irradiating the package layer 24. This allows the heat energy of the laser beam L to be transferred to the area below the package layer 24 via the support structure 20. At the same time, the thermally uniform interposer 8 absorbs the energy of the laser beam L and converts it into radiant heat, which is conducted to the package layer 24 below through air conduction, thus uniformly heating the solder bumps 250. Therefore, compared with the prior art, the electronic package of this application not only avoids the problem of the package layer 24 easily burning due to overheating, but also avoids the problem of solder non-wetting on the solder bumps 250.
[0061] This application also provides an electronic package 2, which includes: a carrier structure 20, at least one electronic component 21 disposed on the carrier structure 20, an encapsulation layer 24 disposed on the carrier structure 20 and covering the electronic component 21, a thermally uniform interlayer 8 covering the encapsulation layer 24 and at least partially exposing the electronic component 21, and a substrate 25 connected to the carrier structure 20 by a plurality of solder bumps 250.
[0062] In one embodiment, the thermally uniform interlayer 8 is a semiconductor material.
[0063] In one embodiment, the thermally uniform interlayer 8 has at least one cutout portion 80 corresponding to the electronic component 21, so that the electronic component 21 is exposed through the cutout portion 80. For example, the area of the cutout portion 80 corresponds to the area of the exposed surface of the electronic component 21.
[0064] In one embodiment, the projected area of the thermally uniform interposer 8 in the vertical direction is equal to the projected area of the contour of the encapsulation layer 24 in the vertical direction.
[0065] In summary, the electronic package of this application, through the configuration of the thermally uniform interlayer, blocks the laser beam, ensuring that the laser beam only irradiates the electronic component and not the package layer. This allows the heat energy of the laser beam to be transferred to the area below the package layer via the supporting structure. Simultaneously, the thermally uniform interlayer absorbs the laser beam energy and converts it into radiant heat, which is conducted to the package layer below through the air, thus uniformly heating the solder bumps and avoiding the problem of unwetted solder.
[0066] The above embodiments are used to illustrate the principles and effects of this application, and are not intended to limit this application. Those skilled in the art can modify the above embodiments without departing from the spirit and scope of this application. Therefore, the scope of protection of this application should be as set forth in the claims.
Claims
1. An electronic package, characterized in that, include: Load-bearing structure; Electronic components are formed on this supporting structure; An encapsulation layer is disposed on the supporting structure and covers the electronic component; A thermally uniform interlayer covers the encapsulation layer and at least partially exposes the electronic component; as well as The substrate is connected to the support structure via multiple solder bumps.
2. The electronic package as described in claim 1, characterized in that, The thermally uniform interlayer is made of semiconductor material.
3. The electronic package as described in claim 1, characterized in that, The thermally uniform interlayer has cutouts corresponding to the electronic components, so that the electronic components are exposed in the cutouts.
4. The electronic package as described in claim 3, characterized in that, The area of the cutout corresponds to the area of the exposed surface of the electronic component.
5. The electronic package as described in claim 3, characterized in that, The spacing between the thermally uniform interlayer and the encapsulation layer, as well as the size of the cutout, are determined according to the thermal energy of the laser beam irradiating the electronic package and the density of the conductive bumps arranged on the support structure for the electronic component.
6. The electronic package as claimed in claim 1, characterized in that, The thermally uniform interlayer is spaced above the electronic component and the supporting structure.