High-voltage isolation capacitor

Abstract

The utility model provides a high-voltage isolation capacitor, a high-voltage device area comprises a lower-level plate, an upper-level plate and at least one intermediate dielectric layer between an upper pole plate and a lower pole plate, an isolation ring area comprises a metal conducting layer, a first voltage-withstanding dielectric layer and a second voltage-withstanding dielectric layer, the first voltage-withstanding dielectric layer is deposited on the intermediate dielectric layer at the top layer, and the second voltage-withstanding dielectric layer is deposited on the intermediate dielectric layer at the bottom layer. The upper-stage plate and the metal conductive layer are deposited on the first voltage-withstanding dielectric layer on the top layer, and the second voltage-withstanding dielectric layer is deposited on the upper-stage plate, the metal conductive layer and the first voltage-withstanding dielectric layer; and the partition groove is arranged between the upper-stage plate and the metal conductive layer, and the partition groove and the upper-stage plate are arranged at an interval, so that the interface state formed by the voltage-withstanding dielectric layer is disconnected at the partition groove. According to the high-voltage isolation capacitor provided by the utility model, the electric field at the corner of the upper-stage plate is reduced by additionally arranging the voltage-withstanding dielectric layer with the high dielectric constant, and the interface state of the voltage-withstanding dielectric layer formed between the metal conductive layer and the upper-stage plate is blocked by arranging the partition groove, so that the voltage-withstanding performance of the high-voltage isolation capacitor is improved.

Description

Technical Field

[0001] This utility model belongs to the field of semiconductor process technology, and specifically relates to a high-voltage isolation capacitor. Background Technology

[0002] High-voltage isolation capacitors have a wide range of applications due to their numerous advantages, including low power consumption, high reliability, and ease of integration into CMOS processes. For example... Figure 1 As shown, the high-voltage isolation capacitor includes a high-voltage device region and an isolation ring region. In the high-voltage device region, a thick insulating dielectric layer (IMD) is filled between the upper and lower stage boards. In the isolation ring region, metal conductive layers are deposited on the insulating dielectric layer of the upper stage board, and metal conductive layers are embedded within each insulating dielectric layer. These metal conductive layers are electrically connected through conductive pillars. However, as... Figure 2 As shown, in this high-voltage isolation capacitor, due to the curvature effect, the electric field will concentrate in the corner of the upper plate.

[0003] Therefore, the prior art has proposed such as Figure 3 The high-voltage isolation capacitor shown incorporates a high-dielectric-constant dielectric layer, deposited on top of this layer on an upper-level board. Since the electric field strength of the dielectric is inversely proportional to its dielectric constant, the electric field at the corners of the upper-level board is reduced. However, inevitably, compared to the intermediate dielectric layer between the upper and lower boards, the interface states formed by the dielectric layer are more easily broken down, creating charge channels, thus reducing the withstand voltage of the high-voltage isolation capacitor. Therefore, the existing improved high-voltage isolation capacitor requires further improvement to increase its withstand voltage. Utility Model Content

[0004] To address the technical problem that the interface states of the withstand dielectric layer in existing high-voltage isolation capacitor structures reduce the withstand voltage performance of high-voltage isolation capacitors, this invention proposes a high-voltage isolation capacitor, comprising a high-voltage device region and an isolation ring region. The high-voltage device region includes a lower plate, an upper plate, and at least one intermediate dielectric layer between the upper and lower plates. The isolation ring region includes a metal conductive layer and further comprises:

[0005] A first withstand voltage dielectric layer and a second withstand voltage dielectric layer, wherein the dielectric constants of the first withstand voltage dielectric layer and the second withstand voltage dielectric layer are greater than the dielectric constant of the intermediate dielectric layer.

[0006] The first withstand voltage dielectric layer is deposited on the top intermediate dielectric layer, the upper stage plate and the metal conductive layer are deposited on the first withstand voltage dielectric layer, the upper stage plate and the metal conductive layer are spaced apart, and the second withstand voltage dielectric layer is deposited on the upper stage plate, the metal conductive layer and the first withstand voltage dielectric layer.

[0007] A partition groove is disposed between the upper plate and the metal conductive layer and spaced apart from the upper plate, so that the stacked first pressure-resistant dielectric layer and the second pressure-resistant dielectric layer are disconnected at the partition groove.

[0008] Furthermore, the partition groove is disposed adjacent to or spaced apart from the metal conductive layer.

[0009] Furthermore, a passivation layer is deposited on the top layer of the high-voltage isolation capacitor, and the passivation layer fills the isolation groove. The dielectric strength of the passivation layer is negatively correlated with the groove width of the isolation groove.

[0010] Furthermore, the dielectric strength of the passivation layer is equal to the dielectric strength of the intermediate dielectric layer, and the width of the partition groove is greater than the distance between the upper plate and the lower plate.

[0011] Preferably, the materials of the first and second pressure-resistant dielectric layers include SiN or SiON.

[0012] Furthermore, the isolation ring region also includes a metal layer disposed in each of the intermediate dielectric layers, and a conductive pillar connecting the metal conductive layer and the metal layer.

[0013] Preferably, the partition groove is formed by photomask etching.

[0014] Preferably, the partition groove is formed by anisotropic etching.

[0015] Furthermore, the lower-level board is deposited on the bottom dielectric layer, and each of the intermediate dielectric layers is sequentially deposited on the upper-level board, while the bottom dielectric layer is deposited on the silicon substrate.

[0016] Furthermore, the projection of the upper plate in the vertical direction is mapped onto the lower plate.

[0017] Furthermore, the intermediate dielectric layer is made of SiO2, and the bottom dielectric layer is made of SiO2.

[0018] The high-voltage isolation capacitor proposed in this invention reduces the electric field at the corner of the upper plate by adding a high dielectric constant withstand dielectric layer, and also improves the withstand voltage performance of the high-voltage isolation capacitor by setting a blocking groove to block the interface state of the withstand dielectric layer formed between the metal conductive layer and the upper plate. Attached Figure Description

[0019] Figures 1 to 3 This refers to high-voltage isolation capacitors in existing technologies;

[0020] Figure 4 This is a cross-sectional view of the high-voltage isolation capacitor proposed in this utility model;

[0021] Figure 5 This is a top view of the high-voltage isolation capacitor proposed in this utility model (the metal conductive layer and the second voltage-resistant dielectric layer on the upper plate are etched by anisotropic etching).

[0022] Figure 6 and Figure 7 To form the isolation trench by etching with a photomask;

[0023] Figure 8 To form the partition groove through anisotropic etching. Detailed Implementation

[0024] To facilitate understanding of this utility model, a more comprehensive description will be given below with reference to the accompanying drawings. The drawings illustrate preferred embodiments of this utility model. However, this utility model can be implemented in various forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of the disclosure of this utility model.

[0025] To improve the withstand voltage of existing high-voltage isolation capacitors, this invention proposes a high-voltage isolation capacitor comprising a high-voltage device region and an isolation ring region. The high-voltage device region includes at least one intermediate dielectric layer between the lower plate, the upper plate, and the upper and lower plates. The isolation ring region includes a metallic conductive layer.

[0026] High-voltage isolation capacitors also include:

[0027] The first and second withstand voltage dielectric layers have dielectric constants greater than those of the intermediate dielectric layer.

[0028] A first withstand voltage dielectric layer is deposited on the top intermediate dielectric layer. An upper-level plate and a metal conductive layer are deposited on the first withstand voltage dielectric layer, with the upper-level plate and the metal conductive layer spaced apart. A second withstand voltage dielectric layer is deposited on the upper-level plate, the metal conductive layer, and the first withstand voltage dielectric layer.

[0029] An isolation groove is disposed between the upper plate and the metal conductive layer and spaced apart from the upper plate, so that the interface state formed by the stacked first and second pressure-resistant dielectric layers is broken at the isolation groove.

[0030] Therefore, it can be seen that the high voltage isolation capacitor proposed in this utility model reduces the electric field at the corner of the upper plate by adding a high dielectric constant withstand dielectric layer, and also improves the withstand voltage performance of the high voltage isolation capacitor by setting a blocking groove to block the interface state of the withstand dielectric layer formed between the metal conductive layer and the upper plate.

[0031] Specifically, such as Figure 4 and Figure 5 As shown, the high-voltage isolation capacitor includes:

[0032] silicon substrate

[0033] The bottom dielectric layer (ILD) deposited on a silicon substrate.

[0034] Sub-boards deposited on the underlying dielectric layer ILD

[0035] The first intermediate dielectric layer IMD1 is deposited on the lower-level board.

[0036] A second intermediate dielectric layer IMD2 is deposited on the first intermediate dielectric layer IMD1.

[0037] A third intermediate dielectric layer, IMD3, is deposited on the second intermediate dielectric layer, IMD2.

[0038] The first withstand dielectric layer deposited on the third intermediate dielectric layer IMD3

[0039] An upper-level plate and a metal conductive layer are deposited on the first withstand voltage dielectric layer, with the upper-level plate and the metal conductive layer spaced apart. The vertical projection of the upper-level plate is mapped onto the lower-level plate.

[0040] A second voltage-resistant dielectric layer is deposited on the upper plate, the metal conductive layer, and the first voltage-resistant dielectric layer. The dielectric constants of the first and second voltage-resistant dielectric layers are greater than the dielectric constant of the intermediate dielectric layer.

[0041] The partition groove is disposed between the metal conductive layer and the upper plate and spaced apart from the upper plate, so that the stacking structure of the first pressure-resistant dielectric layer and the second pressure-resistant dielectric layer is broken at the partition groove, thereby blocking the interface state of the first pressure-resistant layer and the second pressure-resistant layer between the metal conductive layer and the upper plate.

[0042] Furthermore, such as Figure 4 As shown, the isolation ring region also includes a metal layer embedded in each intermediate dielectric layer, and conductive pillars connecting the metal conductive layer and each metal layer. The isolation ring region is grounded.

[0043] Furthermore, in one embodiment, the partition groove is formed by photomask etching, such as... Figure 6 and Figure 7 As shown, after the second withstand voltage dielectric layer is deposited, a mask is placed on top of the second withstand voltage dielectric layer, and then the isolation trench is formed by etching. For example, Figure 6As shown, the partition groove is spaced apart from the upper plate, meaning there is an interface state formed by the stacking of a first and a second withstand voltage dielectric layer between the partition groove and the upper plate. Similarly, the partition groove is spaced apart from the metal conductive layer, again forming an interface state between the partition groove and the metal conductive layer. The partition groove isolates the interface state between the upper plate and the metal conductive layer. Therefore, when the high-voltage isolation capacitor is connected to a voltage, breakdown cannot occur between the upper plate and the metal conductive layer, preventing the interface state from reducing the withstand voltage of the high-voltage isolation capacitor. Alternatively, as... Figure 7 As shown, the partition groove is spaced apart from the upper plate, meaning there is an interface state formed by the stacking of a first and a second withstand voltage dielectric layer between the partition groove and the upper plate. The partition groove is adjacent to the metal conductive layer, meaning there is no interface state between them. Therefore, the interface state formed by the stacking of the first and second withstand voltage dielectric layers between the partition groove and the upper plate improves the electric field strength at the edge of the upper plate. Simultaneously, the partition groove disrupts the interface state between the metal conductive layer and the upper plate, preventing the interface state from reducing the withstand voltage of the high-voltage isolation capacitor.

[0044] Furthermore, in another embodiment, the partition groove is formed by anisotropic etching, such as... Figure 8 As shown, after the second pressure-resistant dielectric layer is deposited, anisotropic etching is used on it. Existing anisotropic etching is used to form sidewall structures, but while etching to form the sidewall structures, it also etches away the stacked structure of the first and second pressure-resistant layers to form partition trenches. Using anisotropic etching saves on photomask etching compared to photomask etching. For example, Figure 8 As shown, the partition groove is spaced apart from the upper plate, meaning there is an interface state formed by the stacking of a first and a second withstand voltage dielectric layer between the partition groove and the upper plate. Similarly, the partition groove is spaced apart from the metal conductive layer, again forming an interface state between the partition groove and the metal conductive layer. Therefore, the interface state formed by the stacking of the first and second withstand voltage dielectric layers between the partition groove and the upper plate improves the electric field strength at the edge of the upper plate. Simultaneously, the partition groove disrupts the interface state between the metal conductive layer and the upper plate, preventing the interface state from reducing the withstand voltage of the high-voltage isolation capacitor.

[0045] However, as Figure 4As shown, the passivation layer is actually deposited on the top layer and fills the isolation groove. Therefore, in actual use, it is possible that the upper plate and the metal conductive layer break down before the upper and lower plates. In this case, it is necessary to control the width of the isolation groove according to the dielectric strength of the passivation layer so that the breakdown between the upper and lower plates occurs before the upper plate and the metal conductive layer. Generally, the dielectric strength of the passivation layer and the width of the isolation groove are negatively correlated; a passivation layer with a higher dielectric strength can have a smaller groove width. However, since there is no specific functional relationship between dielectric strength and groove width, it is not easy to control the specific settings of dielectric strength and groove width to ensure priority breakdown between the upper and lower plates. Therefore, for ease of operation, it is preferable that the dielectric strength of the passivation layer and the intermediate dielectric layer are the same, and the width L of the isolation groove is controlled to be greater than the distance between the upper and lower plates. This ensures that electrical breakdown between the upper and lower plates occurs before the breakdown between the metal conductive layer and the upper plate.

[0046] Furthermore, the first and second withstand voltage layers can be SiN or SiON, and the bottom dielectric layer and the intermediate dielectric layer are SiO2. The material of the intermediate dielectric layer includes SiO2, and the material of the bottom dielectric layer includes SiO2.

[0047] It should be noted that the specific implementation and corresponding illustrations provided are merely one way of describing the implementation method of this utility model, and are not intended to limit the specific structure of the implementation scheme of this utility model. Various changes or modifications can be made to these implementation methods without departing from the principles and essence of this utility model, but all such changes and modifications fall within the protection scope of this utility model.

[0048] Although the embodiments are described and illustrated separately above, some common technologies are involved. Those skilled in the art can replace and integrate them between the embodiments. If there is any content not explicitly described in one embodiment, then another embodiment that is described can be referred to.

[0049] The embodiments described above do not constitute a limitation on the scope of protection of this technical solution. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the above embodiments should be included within the scope of protection of this technical solution.

Claims

1. A high-voltage isolation capacitor, comprising a high-voltage device region and an isolation ring region, characterized in that, The high-voltage device region includes a lower plate, an upper plate, and at least one intermediate dielectric layer between the upper and lower plates. The isolation ring region includes a metal conductive layer and further includes: A first withstand voltage dielectric layer and a second withstand voltage dielectric layer, wherein the dielectric constants of the first withstand voltage dielectric layer and the second withstand voltage dielectric layer are greater than the dielectric constant of the intermediate dielectric layer. The first withstand voltage dielectric layer is deposited on the top intermediate dielectric layer, the upper stage plate and the metal conductive layer are deposited on the first withstand voltage dielectric layer, the upper stage plate and the metal conductive layer are spaced apart, and the second withstand voltage dielectric layer is deposited on the upper stage plate, the metal conductive layer and the first withstand voltage dielectric layer. A partition groove is disposed between the upper plate and the metal conductive layer and spaced apart from the upper plate, so that the stacked first pressure-resistant dielectric layer and the second pressure-resistant dielectric layer are disconnected at the partition groove.

2. The high-voltage isolation capacitor as described in claim 1, characterized in that, The partition groove is arranged adjacent to or spaced apart from the metal conductive layer.

3. The high-voltage isolation capacitor as described in claim 1, characterized in that, The top layer of the high-voltage isolation capacitor is deposited with a passivation layer, and the passivation layer fills the isolation groove. The dielectric strength of the passivation layer is negatively correlated with the width of the isolation groove.

4. The high-voltage isolation capacitor as described in claim 3, characterized in that, The dielectric strength of the passivation layer is equal to the dielectric strength of the intermediate dielectric layer, and the width of the partition groove is greater than the distance between the upper plate and the lower plate.

5. The high-voltage isolation capacitor as described in claim 1, characterized in that, The materials of the first and second pressure-resistant dielectric layers include SiN or SiON.

6. The high-voltage isolation capacitor as described in claim 1, characterized in that, The isolation ring region also includes a metal layer disposed in each of the intermediate dielectric layers, and a conductive pillar connecting the metal conductive layer and the metal layer.

7. The high-voltage isolation capacitor as described in claim 1, characterized in that, The partition groove is formed by photomask etching.

8. The high-voltage isolation capacitor as described in claim 1, characterized in that, The partition groove is formed by anisotropic etching.

9. The high-voltage isolation capacitor as described in claim 1, characterized in that, The lower-level board is deposited on the bottom dielectric layer, and the intermediate dielectric layers are sequentially deposited on the upper-level board. The bottom dielectric layer is deposited on the silicon substrate.

10. The high-voltage isolation capacitor as described in claim 9, characterized in that, The intermediate dielectric layer is made of SiO2, and the bottom dielectric layer is made of SiO2.

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