Multi-channel ADC index real-time dynamic testing device for radar signal processing

Abstract

The utility model relates to a multichannel ADC index real-time dynamic testing device for radar signal processing, and belongs to the field of hardware testing. The testing device comprises a control board card, a dual-channel programmable signal generator, a power divider, an upper computer and a testing bottom plate used for testing a multi-channel ADC acquisition board card. Wherein the input end and the output end of the control board card are respectively connected with the input end of the dual-channel programmable signal generator and a serial port of the upper computer; two output ends of the dual-channel programmable signal generator are respectively connected with an input end of the power divider and a clock input end of the tested multi-channel ADC acquisition board through the test bottom board; the output end of the power divider is connected with the input end of the multi-channel ADC acquisition board through the test bottom board; and the upper computer is connected with the output end of the multi-channel ADC acquisition board through the test bottom board. According to the utility model, the real-time dynamic test of the multichannel ADC of the radar seeker signal processing extension set is realized.

Description

Technical Field

[0001] This utility model belongs to the field of hardware testing, and in particular relates to a real-time dynamic testing device for multi-channel ADC indicators in radar signal processing. Background Technology

[0002] The radar seeker signal processing unit has specific requirements for multi-channel ADCs in terms of phase consistency, amplitude consistency, effective bits, spurious-free dynamic range, and instantaneous bandwidth. Traditional testing methods for multi-channel ADCs in radar seeker signal processing units are limited and generate small amounts of test data. Typically, the processor captures data once or multiple times, then exports the data to a computer using the processor's software for analysis. Traditional measurement methods are limited in functionality, lack real-time measurement capabilities, and cannot perform ADC performance analysis based on the radar seeker's signal characteristics. Therefore, traditional testing methods cannot confirm whether the multi-channel ADC performance meets the radar seeker's requirements in the initial design phase of the signal processing unit; verification must be performed throughout the entire radar system. This lengthens the verification cycle, resulting in a longer development cycle between the design of the multi-channel ADC acquisition board and the development of the radar seeker system. If the multi-channel ADC performance is found to be unsatisfactory when used in the radar seeker system, it significantly extends the system development cycle, leading to low efficiency, long testing times, and high costs. Utility Model Content

[0003] Based on the above analysis, the present invention aims to provide a real-time dynamic testing device for multi-channel ADC indicators in radar signal processing, thereby enabling real-time dynamic testing of multi-channel ADC indicators.

[0004] A real-time dynamic testing device for multi-channel ADC performance in radar signal processing, specifically comprising:

[0005] The system includes a control board, a dual-channel programmable signal generator, a power divider, a host computer, and a test baseboard for testing multi-channel ADC acquisition boards; among these,

[0006] The input and output terminals of the control board are connected to the input terminal of the dual-channel programmable signal generator and the serial port of the host computer, respectively.

[0007] The two outputs of the dual-channel programmable signal generator are connected to the input of the power divider and the clock input of the multi-channel ADC acquisition board under test via the test base plate, respectively.

[0008] The output of the power divider is connected to the input of the multi-channel ADC acquisition board via the test base plate;

[0009] The host computer is connected to the output of the multi-channel ADC acquisition board via the test baseboard.

[0010] Furthermore, the control board includes a system power supply, clock, memory, FPGA, interface chip, and external communication connector; wherein,

[0011] The external communication connector and interface chip are connected through the baseboard circuit of the control board;

[0012] The interface chip, memory, and clock are connected to the FPGA via the baseboard circuitry of the control board.

[0013] The system power supply is fixed on the base plate of the control board.

[0014] Furthermore, the input end of the external communication connector is connected to the serial port of the host computer, and the output end is connected to the input end of the dual-channel programmable signal generator.

[0015] Furthermore, the input end of the external communication connector is connected to the Ethernet port of the host computer, and the output end is connected to the input end of the dual-channel programmable signal generator.

[0016] Furthermore, the system power supply of the control board is electrically connected to the power supply.

[0017] Furthermore, the second output terminal of the control board is connected to the processor of the multi-channel ADC acquisition board through the GPMC interface of the test baseboard.

[0018] Furthermore, the second output terminal of the control board is connected to the processor of the multi-channel ADC acquisition board through the SPI interface of the test baseboard.

[0019] Furthermore, the host computer connects to the output of the multi-channel ADC acquisition board via the optical port of the test baseboard.

[0020] Furthermore, the host computer is connected to the output of the multi-channel ADC acquisition board via the Ethernet port of the test baseboard.

[0021] Furthermore, the host computer is connected to the output of the multi-channel ADC acquisition board via the USB port of the test baseboard.

[0022] This utility model can achieve at least one of the following beneficial effects:

[0023] By configuring the parameters of the dual-channel programmable signal generator using a host computer, it is possible to generate simulated test signals according to the requirements of radar seeker signal processing characteristics. This meets the signal testing requirements of radar systems with multiple processing cycles and high instantaneous bandwidth, and solves the problem that traditional multi-channel ADC testing can only perform static performance testing of point frequency signals in a single signal processing cycle. It enables simultaneous accumulation calculation of ADC performance indicators for multiple repetition cycles, which is efficient, real-time, and saves R&D costs.

[0024] Through various testing modes, including standard signal source test mode, linear frequency modulated signal source test mode, and specific instantaneous bandwidth test mode, and with selectable repetition frequency superposition numbers for each mode, real-time ADC performance analysis can be performed based on the signal characteristics of the radar seeker. This confirms whether the performance of the multi-channel ADC meets the requirements of the radar seeker during the initial design phase of the signal processing unit, avoiding wasted time on redevelopment due to problems encountered during overall system verification, and shortening the development cycle of the radar seeker system.

[0025] Other features and advantages of this invention will be set forth in the following description, and some advantages may become apparent from the description or be learned by practicing the invention. The objectives and other advantages of this invention will be realized and obtained from what is particularly pointed out in the description, claims, and drawings. Attached Figure Description

[0026] The accompanying drawings are for illustrative purposes only and are not intended to limit the scope of the invention. Throughout the drawings, the same reference numerals denote the same parts.

[0027] Figure 1 This is a structural diagram of the testing device of the present invention;

[0028] Figure 2 This is a schematic diagram of the control board structure. Detailed Implementation

[0029] The preferred embodiments of the present invention will now be described in detail with reference to the accompanying drawings, which constitute a part of this application and are used together with the embodiments of the present invention to illustrate the principles of the present invention, but are not intended to limit the scope of the present invention.

[0030] A specific embodiment of this utility model discloses a real-time dynamic testing device for multi-channel ADC performance in radar signal processing, specifically including a control board, a dual-channel programmable signal generator, a power divider, a host computer, and a test base plate for testing the multi-channel ADC acquisition board; wherein...

[0031] The input and output terminals of the control board are connected to the input terminal of the dual-channel programmable signal generator and the serial port of the host computer, respectively.

[0032] The two outputs of the dual-channel programmable signal generator are connected to the input of the power divider and the clock input of the multi-channel ADC acquisition board under test via the test base plate, respectively.

[0033] The output of the power divider is connected to the input of the multi-channel ADC acquisition board via the test base plate;

[0034] The host computer is connected to the output of the multi-channel ADC acquisition board via the test baseboard.

[0035] Specifically, the host computer is usually an industrial control computer, and host computer software is written for data acquisition and processing.

[0036] Specifically, during testing, the host computer software offers three test modes: a standard signal source test mode, a linear frequency modulated (LFM) signal source test mode, and a specific instantaneous bandwidth test mode. Each mode allows selection of the number of repetition frequencies, which users can choose according to their specific needs. Furthermore, the standard signal source test mode outputs a signal at a specific standard frequency, the LFM signal source test mode outputs a signal with continuously varying frequency, and the specific instantaneous bandwidth test mode outputs a high-bandwidth LFM signal.

[0037] Furthermore, during testing, the host computer software uses data processing tools such as MATLAB to analyze the data, enabling real-time analysis of indicators such as phase consistency, amplitude consistency, effective bits of each ADC channel, signal-to-noise ratio (SNR), and spurious-free dynamic range (SNR) of the multi-channel ADC. Based on the radar system requirements, ADC performance under multiple repetition frequency cycles is measured repeatedly using the control gate signal and then superimposed to obtain the results. This is used to test whether the signal-to-noise ratio and spurious-free dynamic range under the repetition frequency cycles meet the system requirements.

[0038] Specifically, the dual-channel programmable signal generator is used to simulate the analog signals required by the radar system. It can generate linear frequency modulated signals, instantaneous bandwidth signals, and sampling clocks for multi-channel ADC acquisition boards.

[0039] Specifically, the power divider is a 1-to-multipoint power divider, used to split the generated analog signal into multiple signals. The number of channels in the power divider is selected based on the number of ADC channels; when the number of channels is large, they can be cascaded to meet the required number of channels. The output of the power divider is connected to the input of the multi-channel ADC acquisition board via an RF cable, which is used to transmit high-speed analog signals.

[0040] Specifically, the control board includes system power supply, clock, memory, FPGA, interface chip, and external communication connector; among them,

[0041] The external communication connector and interface chip are connected through the baseboard circuit of the control board;

[0042] The interface chip, memory, and clock are connected to the FPGA via the baseboard circuitry of the control board.

[0043] The system power supply is fixed on the base plate of the control board.

[0044] Specifically, the control board uses FPGA programmable logic devices to control the corresponding power supply chip, clock chip, interface chip, memory, and external communication connector. The control board is used to directly collect and send instructions to the host computer, dual-channel programmable signal generator, and multi-channel ADC acquisition board.

[0045] Furthermore, the input end of the external communication connector is connected to the serial port or Ethernet port of the host computer, and the output end is connected to the input end of the dual-channel programmable signal generator.

[0046] Furthermore, the system power supply of the control board is electrically connected to the power supply.

[0047] Furthermore, the second output terminal of the control board is connected to the processor of the multi-channel ADC acquisition board via the GPMC interface or SPI interface of the test baseboard. During testing, when the host computer software sends a control command to the control board, the control board detects the trigger signal and controls its output signal waveform to the dual-channel programmable signal source. The second output terminal of the control board sends a gate signal to the multi-channel ADC acquisition board, and the signal data received by the ADC is acquired through the gate signal.

[0048] Furthermore, the host computer connects to the output of the multi-channel ADC acquisition board via the optical port, Ethernet port, or USB port of the test baseboard.

[0049] This embodiment discloses a real-time dynamic testing device for multi-channel ADC performance in radar signal processing. By configuring the parameters of a dual-channel programmable signal generator using a host computer, it can generate simulated test signals according to the requirements of radar seeker signal processing characteristics. This satisfies the signal testing requirements of radar systems with multiple processing cycles and high instantaneous bandwidth, and solves the problem that traditional multi-channel ADC testing can only perform static performance testing of point frequency signals in a single signal processing cycle. It enables simultaneous accumulation calculation of ADC performance indicators for multiple repetition cycles, which is efficient, real-time, and saves R&D costs.

[0050] Through various testing modes, including standard signal source test mode, linear frequency modulated signal source test mode, and specific instantaneous bandwidth test mode, and with selectable repetition frequency superposition numbers for each mode, real-time ADC performance analysis can be performed based on the signal characteristics of the radar seeker. This confirms whether the performance of the multi-channel ADC meets the requirements of the radar seeker during the initial design phase of the signal processing unit, avoiding wasted time on redevelopment due to problems encountered during overall system verification, and shortening the development cycle of the radar seeker system.

[0051] The above description is only a preferred embodiment of the present utility model, but the protection scope of the present utility model is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present utility model should be included within the protection scope of the present utility model.

Claims

1. A real-time dynamic testing device for multi-channel ADC performance in radar signal processing, characterized in that, This includes a control board, a dual-channel programmable signal generator, a power divider, a host computer, and a test baseboard for testing multi-channel ADC acquisition boards; among which, The input and output terminals of the control board are connected to the input terminal of the dual-channel programmable signal generator and the serial port of the host computer, respectively. The two outputs of the dual-channel programmable signal generator are connected to the input of the power divider and the clock input of the multi-channel ADC acquisition board under test via the test base plate, respectively. The output of the power divider is connected to the input of the multi-channel ADC acquisition board via the test base plate; The host computer is connected to the output of the multi-channel ADC acquisition board via the test baseboard.

2. The testing apparatus according to claim 1, characterized in that, The control board includes a system power supply, clock, memory, FPGA, interface chip, and external communication connector; among which, The external communication connector and interface chip are connected through the baseboard circuit of the control board; The interface chip, memory, and clock are connected to the FPGA via the baseboard circuitry of the control board. The system power supply is fixed on the base plate of the control board.

3. The testing apparatus according to claim 2, characterized in that, The input end of the external communication connector is connected to the serial port of the host computer, and the output end is connected to the input end of the dual-channel programmable signal generator.

4. The testing apparatus according to claim 2, characterized in that, The input end of the external communication connector is connected to the Ethernet port of the host computer, and the output end is connected to the input end of the dual-channel programmable signal generator.

5. The testing apparatus according to claim 3 or 4, characterized in that, The system power supply of the control board is electrically connected to the power supply.

6. The testing apparatus according to claim 3 or 4, characterized in that, The second output terminal of the control board is connected to the processor of the multi-channel ADC acquisition board through the GPMC interface of the test baseboard.

7. The testing apparatus according to claim 3 or 4, characterized in that, The second output terminal of the control board is connected to the processor of the multi-channel ADC acquisition board through the SPI interface of the test baseboard.

8. The testing apparatus according to claim 3 or 4, characterized in that, The host computer is connected to the output of the multi-channel ADC acquisition board through the optical port of the test base plate.

9. The testing apparatus according to claim 3 or 4, characterized in that, The host computer is connected to the output of the multi-channel ADC acquisition board via the Ethernet port of the test baseboard.

10. The testing apparatus according to claim 3 or 4, characterized in that, The host computer is connected to the output of the multi-channel ADC acquisition board via the USB port of the test baseboard.

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