Multi-interface cache encryption device based on storage and calculation integrated architecture

Abstract

The utility model provides a multi-interface cache encryption device based on a storage and calculation integrated architecture, which comprises a chip, a cache unit, an encryption unit and a multi-interface module are integrated on the chip, the cache unit is used for temporarily storing accessed data, the encryption unit is interconnected with the cache unit through a bus to carry out encryption or decryption processing in real time, and the multi-interface module is used for storing the accessed data. And the encryption unit is connected with an external computer and storage equipment through the multi-interface module. According to the invention, the PRAM technology is adopted, and the characteristics of high performance and low power consumption are combined, so that efficient cooperative work between storage and encryption calculation can be realized.

Description

Technical Field

[0001] This utility model relates to the field of memory, and in particular to a multi-interface cache encryption device based on a memory-computing integrated architecture. Background Technology

[0002] With the rapid development of information technology and the dramatic increase in data volume, the demand for data storage and processing is growing daily. This is especially true in fields such as big data, cloud computing, and artificial intelligence, where the requirements for high-performance memory and processors are increasingly stringent. However, the traditional von Neumann architecture faces a "storage bottleneck" problem when processing large-scale data. Frequent data transfers between storage and processing units lead to high latency and low efficiency, which is particularly pronounced in applications requiring real-time responses.

[0003] Furthermore, data security is a significant issue in the current storage and computing field. With the increase in cyberattacks and data breaches, protecting the confidentiality and integrity of data during storage and transmission has become a pressing challenge. Traditional storage architectures exhibit a clear separation between data encryption and storage, leading to security vulnerabilities during data transmission.

[0004] In recent years, significant progress has been made in the research and development of in-memory computing chips. Resistive random access memory (RRAM), also known as memristor technology, is a key area of ​​our research. RRAM utilizes the resistance changes of materials to store information, featuring high density, low power consumption, and non-volatility. Data storage and computation are achieved by adjusting the current to change the resistance state of the memory cells. PRAM, with its excellent non-volatility and high speed, can effectively support in-memory computing architectures. This application proposes a multi-interface cache encryption device based on an in-memory computing architecture, using RRAM. Utility Model Content

[0005] The purpose of this invention is to provide a multi-interface caching encryption device based on a storage-computing integrated architecture, which improves the data encryption and caching capabilities of computer systems and enables flexible expansion of various interfaces.

[0006] The technical solution to achieve the purpose of this utility model is as follows:

[0007] A multi-interface cache encryption device based on a storage-computing integrated architecture includes a chip. The chip integrates a cache unit, an encryption unit, and a multi-interface module. The cache unit is used to temporarily store accessed data. The encryption unit is interconnected with the cache unit via a bus to perform encryption or decryption processing in real time. The encryption unit is connected to an external computer or storage device via the multi-interface module.

[0008] Preferably, the cache unit and the encryption unit are integrated on the same chip using PRAM technology.

[0009] Preferably, the encryption unit and the multi-interface module are interconnected using an AXI or Wishbone bus.

[0010] Preferably, the multi-interface module, AXI, or Wishbone bus interconnect is fabricated using CMOS technology.

[0011] Preferably, the multi-interface module is interconnected with external computers and storage devices using PCIe, mSATA, USB, or M.2 interfaces.

[0012] Preferably, the cache unit adopts a multi-level cache architecture.

[0013] Preferably, the encryption unit is connected to an external computer and a storage device via a multi-interface module.

[0014] Preferably, the encryption unit is connected to an external computer via a multi-interface module, and the computer is connected to a storage device.

[0015] Preferably, the storage device is an electronic disk.

[0016] Compared with the prior art, the beneficial effects of this utility model are as follows:

[0017] This utility model, a multi-interface cache encryption device based on a storage-computing integrated architecture, effectively improves the data processing capability of a computer system, reduces power consumption, and ensures data security and reliability by integrating storage and computing encryption functions. The device offers multiple operating modes, especially bypass mode and multiple serial modes, enabling the chip to have flexible scalability in different application scenarios and meet modern computing needs. Attached Figure Description

[0018] Figure 1 This is a connection diagram for the serial operation mode of this device.

[0019] Figure 2 This is a connection diagram for the bypass operation mode of this device. Detailed Implementation

[0020] This invention provides a multi-interface cache encryption device based on an in-memory computing architecture. It integrates a cache unit designed with PRAM and an encryption unit (such as SM2, SM3, SM4, AES, RSA, SHA encryption cores) on the same chip. The related logic circuits of the encryption unit are also designed based on PRAM. The encryption unit is interconnected with the cache unit through a bus and is connected to an external computer and storage device through a multi-interface module, thereby achieving a tight integration of data storage and processing and reducing data transmission latency.

[0021] The cache unit is primarily responsible for temporarily storing frequently accessed data, thereby improving data access speed. Employing PRAM technology, combined with its fast read / write capabilities and non-volatility, it significantly reduces data access latency. This unit uses a multi-level cache architecture, including L1, L2, and L3 caches, each used to store data at different levels. The L1 cache stores the most frequently used data, while the L2 and L3 caches store less frequently accessed data.

[0022] The cache unit embeds existing dynamic cache management strategies (such as LRU, LFU, etc.), monitors data access patterns in real time, and automatically adjusts cached content to optimize performance and ensure a high hit rate.

[0023] The caching unit and the encryption unit are connected via a high-speed interconnect bus to ensure that encryption processing can be performed in real time when caching data, thereby improving data security.

[0024] The encryption unit provides hardware-accelerated data encryption and decryption capabilities and is designed using PRAM technology to ensure data confidentiality during storage and transmission. This unit supports multiple encryption algorithms, including AES, RSA, SHA, SM2, SM3, and SM4, allowing for flexible selection based on specific needs.

[0025] While data is being written to the cache unit, the encryption unit encrypts the data in real time to ensure data security during storage. Decryption also occurs during data retrieval, guaranteeing data integrity.

[0026] Performance optimization:

[0027] The encryption unit uses parallel technology to improve the speed of encryption and decryption, ensuring that it will not become a performance bottleneck under high data transmission rates. At the same time, it has low power consumption due to the use of PRAM design.

[0028] The interface module provides multiple external interfaces to support connections to computer systems and external storage devices, including PCIe, mSATA, M.2, and USB interfaces. The interface design considers various application scenarios, and the module can be flexibly configured as needed to ensure compatibility with different types of external devices.

[0029] The encryption unit and multi-interface modules are interconnected using AXI or Wishbone buses. The multi-interface modules and the on-chip AXI or Wishbone interconnect bus can be implemented using CMOS technology. The multi-interface modules are interconnected with external electronic disks and external computers using PCIe, mSATA, USB, or M.2 interfaces, ensuring efficient data transmission and control signal delivery. Data flow between modules is managed by a bus controller, employing priority-based scheduling algorithms (such as LRU and LFU) to ensure that critical tasks can obtain bus resources in a timely manner. The design and implementation of these modules complement each other, collectively forming a high-efficiency, secure, and flexible multi-interface intelligent cache encryption chip and device. By integrating storage, computing, and security functions, this chip can provide excellent performance and reliability for modern computing needs.

[0030] Combination Figure 1 and Figure 2 The device includes two operating modes: bypass and serial.

[0031] Bypass Operation Mode: The encryption unit connects to external computers and storage devices via multiple interface modules. The PRAM base chip can function as a PCIe or USB coprocessor module, enhancing the computer system's data encryption and caching capabilities. When data is transmitted via the PCIe or USB interface, the chip encrypts and caches the data in real time, thereby improving data security and access speed.

[0032] Serial operating mode: The encryption unit connects to an external computer via a multi-interface module, and the computer connects to the storage device. The PRAM base chip can serve as a bridging solution, supporting PCIe to mSATA, PCIe to M.2, mSATA bridging, M.2 bridging, or USB to mSATA, USB to M.2, providing efficient data caching, encryption, and interface conversion functions. Different serial modes allow users to select the optimal data transmission scheme according to specific needs, ensuring fast and reliable data interaction between the computer and external storage devices.

[0033] The design fully considers testability (DFT) and integrates a test access port (TAP) and boundary scan unit on the PRAM substrate to facilitate later testing and verification and improve mass production yield.

[0034] This invention's in-memory computing chip utilizes PRAM technology, combining its high performance and low power consumption with ease of integration with CMOS processes to achieve efficient collaboration between storage and computing. The invention aims to provide an efficient and secure data processing solution by integrating storage, computing, and encryption functions to meet the challenges of modern computing needs. By optimizing the combination of storage and encrypted computing, it improves data processing speed and security, providing flexible support for various application scenarios.

[0035] It should be noted that the innovation of this utility model lies in the integration of hardware units. The caching, encryption methods, etc. involved are all existing methods or functions that the hardware itself has, and do not involve any program improvements. For example, the encryption algorithm in the encryption unit is integrated into the hardware unit itself or burned into the hardware, and no modifications are required.

[0036] The above are merely preferred embodiments of this application and do not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A multi-interface cache encryption device based on a storage-computing integrated architecture, characterized in that, The chip includes a cache unit, an encryption unit, and a multi-interface module. The cache unit is used to temporarily store accessed data. The encryption unit is interconnected with the cache unit via a bus to perform encryption or decryption processing in real time. The encryption unit is connected to an external computer or storage device via the multi-interface module. The cache unit and the encryption unit are integrated on the same chip using PRAM technology.

2. The multi-interface cache encryption device based on a storage-computing integrated architecture according to claim 1, characterized in that, The encryption unit and the multi-interface module are interconnected using an AXI or Wishbone bus.

3. The multi-interface cache encryption device based on a storage-computing integrated architecture according to claim 2, characterized in that, The multi-interface module, AXI, or Wishbone bus interconnect uses CMOS technology.

4. The multi-interface cache encryption device based on a storage-computing integrated architecture according to claim 2, characterized in that, The multi-interface module is interconnected with external computers and storage devices using PCIe, mSATA, USB, or M.2 interfaces.

5. The multi-interface cache encryption device based on a storage-computing integrated architecture according to claim 1, characterized in that, The cache unit adopts a multi-level cache architecture.

6. The multi-interface cache encryption device based on a storage-computing integrated architecture according to claim 1, characterized in that, The encryption unit is connected to an external computer and storage device through multiple interface modules.

7. The multi-interface cache encryption device based on a storage-computing integrated architecture according to claim 1, characterized in that, The encryption unit is connected to an external computer via a multi-interface module, and the computer is connected to a storage device.

8. A multi-interface cache encryption device based on a storage-computing integrated architecture according to any one of claims 1-7, characterized in that, The storage device is an electronic disk.

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