Three-state input port circuit and chip, display panel and display device comprising same
By designing a three-state input port circuit, including a receiver, a branch, and a bias voltage source, the problems of complex structure, high power consumption, and poor anti-interference capability in the existing technology are solved. Stable operation and low power consumption are achieved within the range of power supply voltage variation, and the anti-interference capability is enhanced.
Patent Information
- Application Number
- CN202422638494.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-30
- Publication Date
- 2025-11-14
- Estimated Expiration
- 2034-10-30
AI Technical Summary
Existing tri-state input port circuits are complex in structure and consume a lot of power, making it difficult to adapt to a wide range of power supply voltage changes. They are also prone to detection errors under high noise and unstable power supply voltage conditions, and have poor anti-interference capabilities.
A three-state input port circuit is designed, including a receiver, first and second branches, and a bias voltage source. Different output combinations can be output by controlling the current flowing through each branch. Optionally, a filter unit and a cascode amplifier can be added to filter and adapt to power supply voltage changes.
It achieves stable operation in application scenarios with large power supply voltage variations, reduces port power consumption, improves anti-interference capability, and reduces noise interference through filtering.
Smart Images
Figure CN223553317U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of integrated circuit technology, and in particular to a tri-state input port circuit and a chip, display panel and display device including the circuit. Background Technology
[0002] Input signals in electronic circuits include three basic logic states: high level, low level, and high impedance. Signals exhibiting these three logic states are collectively referred to as tri-state signals. When designing circuits, a detection circuit is typically used to identify the input state, and then the system is configured accordingly based on the different input states.
[0003] In existing technologies, the structure of existing tri-state input port circuits is relatively complex, consumes a lot of power, and is difficult to adapt to a wide range of power supply voltage variations. Traditional tri-state input port circuits are also prone to detection errors under high noise and unstable power supply voltage conditions, and have poor anti-interference capabilities.
[0004] Therefore, it is desirable to have a new tri-state input port circuit that can overcome the above problems. Utility Model Content
[0005] In view of the above problems, the purpose of this utility model is to provide a tri-state input port circuit and a chip, display panel and display device including the circuit, especially a tri-state input port circuit architecture, so as to adapt to application scenarios with large power supply voltage changes.
[0006] According to one aspect of this utility model, a tri-state input port circuit is provided, comprising:
[0007] The receiving end receives the input signal;
[0008] The first branch has a first end connected to the receiving end and a second end connected to the first output end.
[0009] The second branch, the first end of which is connected to the receiving end, and the second end of which is connected to the second output end; and
[0010] A bias voltage source is connected to the first branch to control the current flowing through the first branch; the bias voltage source is also connected to the second branch to control the current flowing through the second branch.
[0011] When the input signals received by the receiving end are different, the first output end and the second output end output different combinations of outputs.
[0012] Optionally, the tri-state input port circuit further includes:
[0013] A filtering unit is connected to the receiving end to filter the input end and / or power supply noise.
[0014] Optionally, the tri-state input port circuit further includes a first transistor, a second transistor, a third transistor, and a fourth transistor;
[0015] The first terminal of the first transistor is connected to the receiving terminal, the second terminal of the first transistor is connected to the first terminal of the third transistor, and the third terminal of the first transistor is connected to the bias voltage source.
[0016] The first terminal of the second transistor is connected to the second terminal of the fourth transistor, the second terminal of the second transistor is connected to the receiving terminal, and the third terminal of the second transistor is connected to the bias voltage source.
[0017] The third terminal of the third transistor is connected to the first terminal of the third transistor;
[0018] The first terminal of the fourth transistor is grounded, and the third terminal of the fourth transistor is connected to the second terminal of the fourth transistor.
[0019] Wherein, the first transistor is a PMOS transistor, the first terminal of the first transistor is the drain, the second terminal of the first transistor is the source, and the third terminal of the first transistor is the gate.
[0020] The second transistor is an NMOS transistor, with its first terminal being the source, its second terminal being the drain, and its third terminal being the gate.
[0021] The third transistor is a PMOS transistor, with its first terminal being the drain, its second terminal being the source, and its third terminal being the gate.
[0022] The fourth transistor is an NMOS transistor, with its first terminal being the source, its second terminal being the drain, and its third terminal being the gate.
[0023] Optionally, the tri-state input port circuit further includes a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor;
[0024] The first terminal of the fifth transistor is connected to the first output terminal, and the third terminal of the fifth transistor is connected to the second terminal of the first transistor.
[0025] The first terminal of the sixth transistor is grounded, and the second terminal of the sixth transistor is connected to the first output terminal;
[0026] The first terminal of the seventh transistor is connected to the second output terminal;
[0027] The first terminal of the eighth transistor is grounded, the second terminal of the eighth transistor is connected to the second output terminal, and the third terminal of the eighth transistor is connected to the first terminal of the second transistor.
[0028] The fifth transistor is a PMOS transistor, with its first terminal being the drain, its second terminal being the source, and its third terminal being the gate.
[0029] The sixth transistor is an NMOS transistor, with its first terminal being the source, its second terminal being the drain, and its third terminal being the gate.
[0030] The seventh transistor is a PMOS transistor, with its first terminal being the drain, its second terminal being the source, and its third terminal being the gate.
[0031] The eighth transistor is an NMOS transistor, with its first terminal being the source, its second terminal being the drain, and its third terminal being the gate.
[0032] Optionally, the tri-state input port circuit further includes a first resistor and a first capacitor;
[0033] The first end of the first resistor is connected to the receiving end; the second end of the first resistor is connected to the first end of the first capacitor, the third end of the sixth transistor, and the third end of the seventh transistor, respectively.
[0034] The second terminal of the first capacitor is grounded.
[0035] Optionally, the tri-state input port circuit further includes:
[0036] The second resistor has its first end connected to the receiving end, and its second end connected to the first end of the first resistor, the first end of the first transistor, and the second end of the second transistor.
[0037] Optionally, the bias voltage source includes a common-source cascode amplifier.
[0038] Optionally, the common-source cascode amplifier includes a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, and a thirteenth transistor;
[0039] The first terminal of the ninth transistor is connected to the second terminal of the tenth transistor, the second terminal of the ninth transistor is connected to the first bias node, and the third terminal of the ninth transistor is connected to the first bias node.
[0040] The first terminal of the tenth transistor is grounded, the second terminal of the tenth transistor is connected to the third terminal of the tenth transistor, and the third terminal of the tenth transistor is connected to the third terminal of the thirteenth transistor.
[0041] The first terminal of the eleventh transistor is connected to the second terminal of the twelfth transistor, and the third terminal of the eleventh transistor is connected to the first terminal of the eleventh transistor.
[0042] The first terminal of the twelfth transistor is connected to the second bias node, and the third terminal of the twelfth transistor is connected to the second bias node;
[0043] The first terminal of the thirteenth transistor is grounded, and the second terminal of the thirteenth transistor is connected to the second bias node.
[0044] Wherein, the ninth transistor is an NMOS transistor, the first terminal of the ninth transistor is the source, the second terminal of the ninth transistor is the drain, and the third terminal of the ninth transistor is the gate;
[0045] The tenth transistor is an NMOS transistor, with its first terminal being the source, its second terminal being the drain, and its third terminal being the gate.
[0046] The eleventh transistor is a PMOS transistor, with its first terminal being the drain, its second terminal being the source, and its third terminal being the gate.
[0047] The twelfth transistor is a PMOS transistor, with its first terminal being the drain, its second terminal being the source, and its third terminal being the gate.
[0048] The thirteenth transistor is an NMOS transistor, with its first terminal being the source, its second terminal being the drain, and its third terminal being the gate.
[0049] Optionally, the tri-state input port circuit further includes a first transistor and a second transistor;
[0050] The first terminal of the first transistor is connected to the receiving terminal, and the third terminal of the first transistor is connected to the second bias node;
[0051] The second terminal of the second transistor is connected to the receiving terminal, and the third terminal of the second transistor is connected to the first bias node.
[0052] According to another aspect of the present invention, a chip is provided. The chip includes any of the tri-state input port circuits described above.
[0053] According to another aspect of the present invention, a display panel is provided. The display panel includes any of the tri-state input port circuits described above.
[0054] According to another aspect of the present invention, a display device is provided. The display device includes a display panel; and any of the tri-state input port circuits described above.
[0055] The present invention provides a tri-state input port circuit and a chip, display panel and display device thereof. The first branch and the second branch are respectively connected to the receiving end. The bias voltage source is respectively connected to the first branch and the second branch to control the current flowing through each branch. When the input signal received by the receiving end is different, the corresponding output terminals of the first branch and the second branch output different output combinations, realizing the input of tri-state signals. In addition, the setting of the bias voltage source can adapt to application scenarios with large power supply voltage changes.
[0056] Furthermore, the bias voltage source effectively reduces the port's operating current, lowers power consumption, and improves anti-interference capability.
[0057] Furthermore, the filtering unit is connected to the receiving end to perform filtering, which can filter out noise interference.
[0058] Furthermore, the circuit of this application includes a common-source common-gate amplifier, with a MOSFET connected in series between the power supply and ground, and the current increases exponentially with changes in the power supply.
[0059] Furthermore, the circuit structure of this application is simple and has low power consumption. Attached Figure Description
[0060] The above and other objects, features and advantages of the present invention will become clearer from the following description of embodiments of the present invention with reference to the accompanying drawings, in which:
[0061] Figure 1 A schematic diagram of the structure of a three-state input port circuit according to an embodiment of the present invention is shown;
[0062] Figure 2 A schematic diagram of the bias voltage source according to an embodiment of the present invention is shown;
[0063] Figure 3A current-voltage diagram of a three-state input port circuit according to an embodiment of the present invention is shown during operation. Detailed Implementation
[0064] Various embodiments of the present invention will now be described in more detail with reference to the accompanying drawings. In the various drawings, the same elements are indicated by the same or similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale. Furthermore, some well-known parts may not be shown in the drawings.
[0065] The specific embodiments of this utility model will be further described in detail below with reference to the accompanying drawings and examples. Many specific details of this utility model, such as the structure, materials, dimensions, processing techniques, and methods of the components, are described below to provide a clearer understanding of the utility model. However, as those skilled in the art will understand, this utility model may be implemented without adhering to these specific details.
[0066] It should be understood that when describing the structure of a component, when referring to a layer or region as being "above" or "on top of" another layer or region, it can mean that it is directly above the other layer or region, or that it contains other layers or regions between it and the other layer or region. Furthermore, if the component is flipped over, that layer or region will be located "below" or "under" the other layer or region.
[0067] According to one aspect of the present invention, a tri-state input port circuit is provided. The tri-state input port circuit includes a receiver, a first branch, a second branch, and a bias voltage source.
[0068] Specifically, the receiving end receives the input signal. The input signal includes at least one of the following: high level, low level, and high impedance state (NC, floating state).
[0069] The first end of the first branch is connected to the receiving end, and the second end of the first branch is connected to the first output end.
[0070] The first end of the second branch is connected to the receiving end, and the second end of the second branch is connected to the second output end.
[0071] A bias voltage source is connected to the first branch to control the current flowing through the first branch. A bias voltage source is connected to the second branch to control the current flowing through the second branch.
[0072] When the input signals received by the receiving end are different, the first output terminal and the second output terminal will output different combinations of outputs.
[0073] In an optional embodiment of this invention, a first transistor is provided on the first branch, and a bias voltage source is connected to the control terminal of the first transistor to control the current flowing through the first transistor (first branch). A second transistor is provided on the second branch, and a bias voltage source is connected to the control terminal of the second transistor to control the current flowing through the second transistor (second branch). The first transistor and the second transistor are, for example, MOSFETs, and their control terminal is the gate.
[0074] In an optional embodiment of this invention, the tri-state input port circuit further includes a filtering unit. The filtering unit is connected to the receiving end to filter input and / or power supply noise, such as filtering the input signal. Optionally, the filtering unit includes a resistor (R) and a capacitor (C), and performs RC filtering to remove noise interference.
[0075] Figure 1 A schematic diagram of a three-state input port circuit according to an embodiment of the present invention is shown. Figure 1 As shown, in a specific embodiment of this utility model, the tri-state input port circuit includes first to thirteenth transistors, a first resistor, a second resistor, a first capacitor, and a bias voltage source. The first to thirteenth transistors are MOS (Metal-Oxide-Semiconductor Field-Effect Transistors). For ease of description, ... Figure 1 For each transistor in the transistor, the port located at the top is called the second terminal, the port located at the bottom is called the first terminal, and the port located to the side of the first and second terminals is called the third terminal.
[0076] Specifically, the first terminal of the first transistor (MOS1) is connected to the receiver 10. The second terminal of the first transistor (MOS1) is connected to the first terminal of the third transistor (MOS3). The third terminal of the first transistor (MOS1) is connected to a bias voltage source (the structure of the bias voltage source is not shown in the figure; VBPB represents the bias voltage connected to the first transistor). Optionally, the first transistor (MOS1) is a PMOS transistor (P-type MOS transistor), with the first terminal of the first transistor (MOS1) being the drain, the second terminal of the first transistor (MOS1) being the source, and the third terminal of the first transistor (MOS1) being the gate.
[0077] The first terminal of the second transistor (MOS2) is connected to the second terminal of the fourth transistor (MOS4). The second terminal of the second transistor (MOS2) is connected to the receiver 10. The third terminal of the second transistor (MOS2) is connected to a bias voltage source (the structure of the bias voltage source is not shown in the figure; VBNB represents the bias voltage connected to the second transistor). Optionally, the second transistor (MOS2) is an NMOS transistor (N-type MOS transistor), with the first terminal of the second transistor (MOS2) being the source, the second terminal of the second transistor (MOS2) being the drain, and the third terminal of the second transistor (MOS2) being the gate.
[0078] The third terminal of the third transistor (MOS3) is connected to the first terminal of the third transistor (MOS3). Optionally, the second terminal of the third transistor (MOS3) is connected to ground or to other devices. Optionally, the third transistor (MOS3) is a PMOS transistor (P-type MOS transistor). The first terminal of the third transistor (MOS3) is the drain, the second terminal of the third transistor (MOS3) is the source, and the third terminal of the third transistor (MOS3) is the gate.
[0079] The first terminal of the fourth transistor (MOS4) is grounded. The third terminal of the fourth transistor (MOS4) is connected to the second terminal of the fourth transistor (MOS4). Optionally, the fourth transistor (MOS4) is an NMOS transistor (N-type MOS transistor). The first terminal of the fourth transistor (MOS4) is the source, the second terminal of the fourth transistor (MOS4) is the drain, and the third terminal of the fourth transistor (MOS4) is the gate.
[0080] The first terminal of the fifth transistor (MOS5) is connected to the first output terminal 21. The third terminal of the fifth transistor (MOS5) is connected to the second terminal of the first transistor (MOS1). Optionally, the second terminal of the fifth transistor (MOS5) is connected to ground or to other devices. Optionally, the fifth transistor (MOS5) is a PMOS transistor (P-type MOS transistor). The first terminal of the fifth transistor (MOS5) is the drain, the second terminal of the fifth transistor (MOS5) is the source, and the third terminal of the fifth transistor (MOS5) is the gate.
[0081] The first terminal of the sixth transistor (MOS6) is grounded, and the second terminal of the sixth transistor (MOS6) is connected to the first output terminal 21. Optionally, the sixth transistor is an NMOS transistor (N-type MOS transistor), with the first terminal of the sixth transistor (MOS6) being the source, the second terminal of the sixth transistor (MOS6) being the drain, and the third terminal of the sixth transistor (MOS6) being the gate.
[0082] The first terminal of the seventh transistor (MOS7) is connected to the second output terminal 22. Optionally, the second terminal of the seventh transistor (MOS7) is connected to the ground or to other devices. Optionally, the seventh transistor (MOS7) is a PMOS transistor (P-type MOS transistor). The first terminal of the seventh transistor (MOS7) is the drain, the second terminal of the seventh transistor (MOS7) is the source, and the third terminal of the seventh transistor (MOS7) is the gate.
[0083] The first terminal of the eighth transistor (MOS8) is grounded, the second terminal of the eighth transistor (MOS8) is connected to the second output terminal 22, and the third terminal of the eighth transistor (MOS8) is connected to the first terminal of the second transistor (MOS2). Optionally, the eighth transistor (MOS8) is an NMOS transistor (N-type MOS transistor). The first terminal of the eighth transistor (MOS8) is the source, the second terminal of the eighth transistor (MOS8) is the drain, and the third terminal of the eighth transistor (MOS8) is the gate.
[0084] In an optional embodiment of this invention, the tri-state input port circuit further includes a first resistor R1 and a first capacitor C1. The first end of the first resistor R1 is connected to the receiver 10. The second end of the first resistor R1 is connected to the first end of the first capacitor C1, the third end of the sixth transistor (MOS6), and the third end of the seventh transistor (MOS7), respectively. The second end of the first capacitor C1 is grounded. Optionally, the tri-state input port circuit further includes a second resistor R2. The first end of the second resistor R2 is connected to the receiver 10, and the second end of the second resistor R2 is connected to the first end of the first resistor R1, the first end of the first transistor (MOS1), and the second end of the second transistor (MOS2), respectively.
[0085] In an optional embodiment of this invention, the first end of the first branch is connected to the receiving end 10, and the second end of the first branch is connected to the first output end 21. At least one of a first transistor (MOS1), a third transistor (MOS3), a fifth transistor (MOS5), and a sixth transistor (MOS6) is disposed on the first branch. The first end of the second branch is connected to the receiving end 10, and the second end of the second branch is connected to the second output end 22. At least one of a second transistor (MOS2), a fourth transistor (MOS4), a seventh transistor (MOS7), and an eighth transistor (MOS8) is disposed on the second branch. The receiving end 10 receives input signals, including a high level (receiving end 10 connected to a power supply), a low level (receiving end 10 grounded), and a high impedance state (receiving end 10 floating). The three different input signals correspond to three different control codewords, i.e., the first output end 21 and the second output end 22 output different combinations.
[0086] Figure 2A schematic diagram of a bias current source according to an embodiment of the present invention is shown. Figure 2 As shown, the bias current source according to an embodiment of the present invention includes a cascode amplifier. The cascode amplifier, for example, includes cascaded transistors, one transistor serving as the input stage and the other as the output stage. The transistor in the input stage is responsible for providing high input impedance and low noise, while the transistor in the output stage is responsible for providing high output impedance and gain. Further, the cascode amplifier includes a ninth transistor (MOS9), a tenth transistor (MOS10), an eleventh transistor (MOS11), a twelfth transistor (MOS12), and a thirteenth transistor (MOS13).
[0087] Specifically, the first terminal of the ninth transistor (MOS9) is connected to the second terminal of the tenth transistor (MOS10), the second terminal of the ninth transistor (MOS9) is connected to the first bias node, and the third terminal of the ninth transistor (MOS9) is also connected to the first bias node. The first bias node, VBNB, is shown in the diagram. The first bias node VBNB in the bias current source is connected to... Figure 1 The third terminal of the second transistor (MOS2) is shown. Optionally, the second terminal / first bias node VBNB of the ninth transistor (MOS9) is connected to the ground or to other devices. Optionally, the ninth transistor (MOS9) is an NMOS transistor (N-type MOS transistor). The first terminal of the ninth transistor (MOS9) is the source, the second terminal of the ninth transistor (MOS9) is the drain, and the third terminal of the ninth transistor (MOS9) is the gate.
[0088] The first terminal of the tenth transistor (MOS10) is grounded, the second terminal of the tenth transistor (MOS10) is connected to the third terminal of the tenth transistor (MOS10), and the third terminal of the tenth transistor (MOS10) is connected to the third terminal of the thirteenth transistor (MOS13). Optionally, the tenth transistor (MOS10) is an NMOS transistor (N-type MOS). The first terminal of the tenth transistor (MOS10) is the source, the second terminal of the tenth transistor (MOS10) is the drain, and the third terminal of the tenth transistor (MOS10) is the gate.
[0089] The first terminal of the eleventh transistor (MOS11) is connected to the second terminal of the twelfth transistor (MOS12), and the third terminal of the eleventh transistor (MOS11) is connected to the first terminal of the eleventh transistor (MOS11). Optionally, the second terminal of the eleventh transistor (MOS11) is connected to ground or to other devices. Optionally, the eleventh transistor (MOS11) is a PMOS transistor (P-type MOS transistor). The first terminal of the eleventh transistor (MOS11) is the drain, the second terminal of the eleventh transistor (MOS11) is the source, and the third terminal of the eleventh transistor (MOS11) is the gate.
[0090] The first terminal of the twelfth transistor (MOS12) is connected to the second bias node, and the third terminal of the twelfth transistor (MOS12) is also connected to the second bias node. The second bias node VBPB in the bias current source is connected to... Figure 1 The third terminal of the first transistor (MOS1) shown is shown. Optionally, the twelfth transistor (MOS12) is a PMOS transistor (P-type MOS transistor). The first terminal of the twelfth transistor (MOS12) is the drain, the second terminal of the twelfth transistor (MOS12) is the source, and the third terminal of the twelfth transistor (MOS12) is the gate.
[0091] The first terminal of the thirteenth transistor (MOS13) is grounded, and the second terminal of the thirteenth transistor (MOS13) is connected to the second bias node. Optionally, the thirteenth transistor (MOS13) is an NMOS transistor (N-type MOS transistor). The first terminal of the thirteenth transistor (MOS13) is the source, the second terminal of the thirteenth transistor (MOS13) is the drain, and the third terminal of the thirteenth transistor (MOS13) is the gate.
[0092] Optionally, the tri-state input port circuit further includes a first transistor (MOS1) and a second transistor (MOS2). The first terminal of the first transistor (MOS1) is connected to the receiver 10, and the third terminal of the first transistor (MOS1) is connected to the second bias node. The second terminal of the second transistor (MOS2) is connected to the receiver 10, and the third terminal of the second transistor (MOS2) is connected to the first bias node.
[0093] The tri-state input port circuit according to the embodiment of this utility model adopts a common-source common-gate amplifier, and two diode-connected MOS transistors are connected in series between the power supply and ground, with the current increasing exponentially with the power supply.
[0094] Figure 3 A current-voltage diagram of the three-state input port circuit according to an embodiment of the present invention is shown during operation. (In conjunction with...) Figures 1 to 3 As shown, during the change of power supply voltage from 2.5V to 3.3V, the current (I1) flowing through the first transistor (MOS1) and the second transistor (MOS2) changes from 0.8μA to 5μA; when the power supply voltage is above 3.3V, the current (I1) flowing through the first transistor (MOS1) and the second transistor (MOS2) changes little, remaining around 5μA. For most tri-state input port circuits in the prior art, during the change of power supply voltage from 2.5V to 6V, the current (I0) flowing through the portions corresponding to the first and second transistors of this application changes from 0.5μA to over 10μA. In contrast, the solution of this application can effectively reduce the operating current of the port.
[0095] According to another aspect of the present invention, a chip is provided. The chip includes the tri-state input port circuit described above. Optionally, the receiving end of the tri-state input port circuit is connected to a pin of the chip. The chip according to the embodiment of the present invention can realize the detection and use of tri-state inputs, etc.
[0096] According to another aspect of the present invention, a display panel is provided. The display panel includes the tri-state input port circuit described above. The display panel can be a liquid crystal display panel, an organic light-emitting diode (OLED) panel, an electronic ink panel, etc.
[0097] According to another aspect of the present invention, a display device is provided. The display device includes a display panel and a tri-state input port circuit as described above. The display device can be used in televisions, computers, smartphones, etc. Optionally, the display device is at least one selected from sub-millimeter diode light-emitting display devices, micron diode light-emitting display devices, and quantum dot diode light-emitting display devices. The display device is, for example, a complete display including a display panel, a housing, a bracket, a circuit board, etc. The display device may include one or more display panels, as well as other necessary components (such as a power adapter, interface ports, control buttons, etc.).
[0098] The tri-state input port circuit and the chip, display panel, and display device included therein, implemented according to this utility model, can adapt to application scenarios with a large range of power supply voltage variations, and effectively reduces port operating current, optimizing power consumption and anti-interference capabilities. The tri-state input port circuit according to the embodiments of this utility model also features simple structure and low power consumption.
[0099] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.
[0100] As described above, these embodiments of the present invention do not exhaustively cover all details, nor do they limit the invention to the specific embodiments described. Clearly, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the present invention, thereby enabling those skilled in the art to effectively utilize the present invention and its modifications. The present invention is limited only by the claims and their full scope and equivalents.
Claims
1. A tri-state input port circuit, characterized in that, include: The receiving end receives the input signal; The first branch has a first end connected to the receiving end and a second end connected to the first output end. The second branch has a first end connected to the receiving end and a second end connected to the second output end. as well as A bias voltage source is connected to the first branch to control the current flowing through the first branch; The bias voltage source is connected to the second branch to control the current flowing through the second branch. When the input signals received by the receiving end are different, the first output end and the second output end output different combinations of outputs.
2. The tri-state input port circuit according to claim 1, wherein, The tri-state input port circuit also includes: A filtering unit is connected to the receiving end to filter the input end and / or power supply noise.
3. The tri-state input port circuit according to claim 1, wherein, The tri-state input port circuit also includes a first transistor, a second transistor, a third transistor, and a fourth transistor; The first terminal of the first transistor is connected to the receiving terminal, the second terminal of the first transistor is connected to the first terminal of the third transistor, and the third terminal of the first transistor is connected to the bias voltage source. The first terminal of the second transistor is connected to the second terminal of the fourth transistor, the second terminal of the second transistor is connected to the receiving terminal, and the third terminal of the second transistor is connected to the bias voltage source. The third terminal of the third transistor is connected to the first terminal of the third transistor; The first terminal of the fourth transistor is grounded, and the third terminal of the fourth transistor is connected to the second terminal of the fourth transistor. Wherein, the first transistor is a PMOS transistor, the first terminal of the first transistor is the drain, the second terminal of the first transistor is the source, and the third terminal of the first transistor is the gate. The second transistor is an NMOS transistor, with its first terminal being the source, its second terminal being the drain, and its third terminal being the gate. The third transistor is a PMOS transistor, with its first terminal being the drain, its second terminal being the source, and its third terminal being the gate. The fourth transistor is an NMOS transistor, with its first terminal being the source, its second terminal being the drain, and its third terminal being the gate.
4. The tri-state input port circuit according to claim 3, wherein, The tri-state input port circuit also includes a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor; The first terminal of the fifth transistor is connected to the first output terminal, and the third terminal of the fifth transistor is connected to the second terminal of the first transistor. The first terminal of the sixth transistor is grounded, and the second terminal of the sixth transistor is connected to the first output terminal; The first terminal of the seventh transistor is connected to the second output terminal; The first terminal of the eighth transistor is grounded, the second terminal of the eighth transistor is connected to the second output terminal, and the third terminal of the eighth transistor is connected to the first terminal of the second transistor. The fifth transistor is a PMOS transistor, with its first terminal being the drain, its second terminal being the source, and its third terminal being the gate. The sixth transistor is an NMOS transistor, with its first terminal being the source, its second terminal being the drain, and its third terminal being the gate. The seventh transistor is a PMOS transistor, with its first terminal being the drain, its second terminal being the source, and its third terminal being the gate. The eighth transistor is an NMOS transistor, with its first terminal being the source, its second terminal being the drain, and its third terminal being the gate.
5. The tri-state input port circuit according to claim 4, wherein, The tri-state input port circuit also includes a first resistor and a first capacitor; The first end of the first resistor is connected to the receiving end; the second end of the first resistor is connected to the first end of the first capacitor, the third end of the sixth transistor, and the third end of the seventh transistor, respectively. The second terminal of the first capacitor is grounded.
6. The tri-state input port circuit according to claim 5, wherein, The tri-state input port circuit also includes: The second resistor has its first end connected to the receiving end, and its second end connected to the first end of the first resistor, the first end of the first transistor, and the second end of the second transistor.
7. The tri-state input port circuit according to claim 1, wherein, The bias voltage source includes a common-source cascode amplifier.
8. The tri-state input port circuit according to claim 7, wherein, The common-source common-gate amplifier includes a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, and a thirteenth transistor; The first terminal of the ninth transistor is connected to the second terminal of the tenth transistor, the second terminal of the ninth transistor is connected to the first bias node, and the third terminal of the ninth transistor is connected to the first bias node. The first terminal of the tenth transistor is grounded, the second terminal of the tenth transistor is connected to the third terminal of the tenth transistor, and the third terminal of the tenth transistor is connected to the third terminal of the thirteenth transistor. The first terminal of the eleventh transistor is connected to the second terminal of the twelfth transistor, and the third terminal of the eleventh transistor is connected to the first terminal of the eleventh transistor. The first terminal of the twelfth transistor is connected to the second bias node, and the third terminal of the twelfth transistor is connected to the second bias node; The first terminal of the thirteenth transistor is grounded, and the second terminal of the thirteenth transistor is connected to the second bias node. Wherein, the ninth transistor is an NMOS transistor, the first terminal of the ninth transistor is the source, the second terminal of the ninth transistor is the drain, and the third terminal of the ninth transistor is the gate; The tenth transistor is an NMOS transistor, with its first terminal being the source, its second terminal being the drain, and its third terminal being the gate. The eleventh transistor is a PMOS transistor, with its first terminal being the drain, its second terminal being the source, and its third terminal being the gate. The twelfth transistor is a PMOS transistor, with its first terminal being the drain, its second terminal being the source, and its third terminal being the gate. The thirteenth transistor is an NMOS transistor, with its first terminal being the source, its second terminal being the drain, and its third terminal being the gate.
9. The tri-state input port circuit according to claim 8, wherein, The tri-state input port circuit also includes a first transistor and a second transistor; The first terminal of the first transistor is connected to the receiving terminal, and the third terminal of the first transistor is connected to the second bias node; The second terminal of the second transistor is connected to the receiving terminal, and the third terminal of the second transistor is connected to the first bias node.
10. A chip, characterized in that, include: The tri-state input port circuit as described in any one of claims 1-9.
11. A display panel, characterized in that, include: The tri-state input port circuit as described in any one of claims 1-9.
12. A display device, characterized in that, include: Display panel; as well as The tri-state input port circuit as described in any one of claims 1-9.