Composite operational circuit in integrated circuit
By designing a composite arithmetic circuit and utilizing the time-division multiplexing of register groups and arithmetic modules, the problem of high hardware resource consumption in integrated circuits was solved, enabling efficient filtering and binary convolution operations and reducing hardware resource overhead.
Patent Information
- Application Number
- CN202423107503.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-16
- Publication Date
- 2025-11-18
- Estimated Expiration
- 2034-12-16
AI Technical Summary
In existing integrated circuits, FIR filters and binary convolution operation units consume a lot of hardware resources, so it is necessary to reduce hardware resource overhead.
Design a composite arithmetic circuit in an integrated circuit to implement filtering and binary convolution operations by using a register group, a multiplication/binary operation module, and an addition module in a time-sharing manner, thereby reducing the duplication of hardware resources.
It enables simultaneous filtering and binary convolution operations on the same hardware platform, reducing hardware resource consumption and improving resource utilization efficiency.
Smart Images
Figure CN223566131U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The utility model relates to the field of hardware operation especially relates to a composite operation circuit in integrated circuit. BACKGROUND
[0002] In the existing integrated circuit, FIR (Finite Impulse Response) filter and binary convolution operation unit are usually designed respectively, and hardware resource occupation is high.
[0003] Therefore, a new technical scheme is needed to solve the above problems. UTILIT Y MODEL CONTENTS
[0004] One of the purposes of the utility model is to provide a composite operation circuit in integrated circuit, which can not only realize filter operation, but also realize binary convolution operation, and reduce hardware resource consumption.
[0005] According to one aspect of the utility model, the utility model provides a composite operation circuit in integrated circuit, it includes: first register group is used to cache multiple filter coefficients when carrying out filter operation, and is used to cache multiple convolution coefficients when carrying out binary convolution operation;Second register group is used to receive and shift the multiple filter data that caches in turn input when carrying out filter operation;Third register is used to receive and cache the binary data of binary convolution that input when carrying out binary convolution operation;Multiplication / binary operation module and addition module, wherein the multiplication / binary operation module and the addition module when carrying out filter operation, based on the filter data and the filter coefficient carry out multiplication and addition operation, when carrying out binary convolution operation, based on the convolution coefficient and the binary data of binary convolution that input carry out binary operation and addition operation.
[0006] In one embodiment, the first register group caches multiple convolution coefficients each time when performing the binary convolution operation, and the third register caches the binarized data to be subjected to the binary convolution each time when performing the binary convolution operation, wherein the multiple convolution coefficients in the first register group are updated multiple times when performing the binary convolution operation, and the binarized data to be subjected to the binary convolution in the third register is updated multiple times when performing the binary convolution operation; the multiplication / binary operation module performs multiplication operation on each data to be filtered in the second register group and the corresponding filter coefficient in the first register group to obtain multiple filter product data when performing the filtering operation, and performs binary operation on the binarized data to be subjected to the binary convolution in the third register and each convolution coefficient in the first register group to obtain multiple binary operation data when performing the binary convolution operation; the addition module adds the multiple filter product data obtained by the multiplication / binary operation module to obtain filter result data when performing the filtering operation, and adds the multiple binary convolution temporary result data obtained previously and the multiple binary operation data currently obtained by the multiplication / binary operation module respectively to obtain the multiple binary convolution temporary result data currently when performing the binary convolution operation, wherein the convolution coefficient in the first register group and the binarized data to be subjected to the binary convolution in the third register are updated once each time, and the multiple binary convolution temporary result data currently is obtained based on the updated convolution coefficient and the updated binarized data to be subjected to the binary convolution when performing the binary convolution operation, and the multiple binary convolution temporary result data obtained last time is output as the multiple binary convolution final result data after the convolution coefficient and the binarized data to be subjected to the binary convolution are updated to a predetermined threshold number of times.
[0007] Compared with the prior art, the utility model discloses through time-sharing first register group, multiplex multiplication / binary operation module and / or the addition module performs filtering operation and binary convolution operation, reduces the resource consumption of hardware.
DRAWINGS
[0008] In order to more clearly illustrate the technical scheme of the embodiment of the utility model, the drawings needed in the embodiment description will be briefly introduced as follows, and obviously, the drawings in the following description are only some embodiments of the utility model, and for those skilled in the art, other drawings can also be obtained based on these drawings without the creative labor, wherein:
[0009] Figure 1 It is another partial structure block diagram of the composite operation circuit in the integrated circuit in the utility model.
[0010] Figure 2 It is another partial structure block diagram of the composite operation circuit in the integrated circuit in the utility model.
CONCRETE EMBODIMENT
[0011] In order to make the above object, characteristics and advantages of the present application more apparent, comprehensible and easier to understand, the present application will be further described in detail below with reference to the drawings and specific embodiments.
[0012] The term "one embodiment" or "an embodiment" as used herein means that a particular feature, structure, or characteristic described can be included in at least one embodiment of the present application. The appearances of the phrase "in one embodiment" or "in an embodiment" in various places in the specification are not necessarily all referring to the same embodiment, nor are they necessarily all referring to a single, special or unique embodiment. In the present application, unless otherwise clearly specified and limited, the terms "connected", "connected", "coupled" and the like, which are used to express electrical connection, should be interpreted in a broad sense; for example, it can be direct electrical connection, or indirect electrical connection through an intermediate medium, and the intermediate medium can be electronic components, functional circuits, etc. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.
[0013] In the description of the present application, it should be understood that the terms "upper", "lower", "front", "back", "front", "back", "left", "right", "vertical", "vertical", "horizontal", "top", "bottom", "inner", "outer" and the like indicate the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present application.
[0014] The present application provides a composite operation circuit in an integrated circuit, which can not only realize filtering operation, but also realize binary convolution operation, and reduce the resource consumption of hardware.
[0015] Figure 1 Part of the structure block diagram of the composite operation circuit in the integrated circuit in the present application. Figure 2 Another part of the structure block diagram of the composite operation circuit in the integrated circuit in the present application.
[0016] As Figure 1 And 2As shown, the composite operation circuit in the integrated circuit comprises a first register group 110, a second register group 120, a third register 130, a multiplication / binary operation module 150 and an addition module 170. The first register group 110 is used to buffer a plurality of filter coefficients when performing a filter operation, and is used to buffer a plurality of convolution coefficients when performing a binary convolution operation. The second register group 120 is used to receive and shift a plurality of to-be-filtered data input in sequence when performing a filter operation. The third register 130 is used to receive and buffer the input binary data to be binary-convolved when performing a binary convolution operation. The multiplication / binary operation module 150 and the addition module 170 perform multiplication and addition operations based on the to-be-filtered data and the filter coefficients when performing a filter operation, and perform binary operation and addition operation based on the convolution coefficients and the binary data to be binary-convolved when performing a binary convolution operation. In this way, by time-division multiplexing the first register group, the multiplication / binary operation module and / or the addition module to perform filter operation and binary convolution operation, the resource overhead of hardware is reduced. That is, in a single integrated circuit (or chip), the composite operation circuit can work as a filter and can also work as a binary convolution operation unit. By using efficient instructions, the composite operation circuit works as a filter or as a binary convolution operation unit in time-division manner, without interfering with each other.
[0017] In one embodiment, the first register group 110 buffers multiple convolution coefficients at a time when performing the binary convolution operation, and the third register 130 buffers the binarized data to be convolved at a time when performing the binary convolution operation. When performing the binary convolution operation, the multiple convolution coefficients in the first register group 110 are updated multiple times, and the binarized data to be convolved in the third register 130 is updated multiple times. When performing the filtering operation, the multiplication / binary operation module 150 performs multiplication operation on each data to be filtered in the second register group 120 and the corresponding filter coefficient in the first register group 110 to obtain multiple filtering product data, and when performing the binary convolution operation, the multiplication / binary operation module 150 performs binary operation on the binarized data to be convolved in the third register 130 and each convolution coefficient in the first register group 110 to obtain multiple binary operation data. When performing the filtering operation, the addition module 170 adds the multiple filtering product data obtained by the multiplication / binary operation module 150 to obtain filtering result data, and when performing the binary convolution operation, the addition module 170 adds the previous multiple binary convolution temporary result data and the multiple binary operation data currently obtained by the multiplication / binary operation module 150 respectively to obtain the current multiple binary convolution temporary result data. When performing the binary convolution operation, the convolution coefficient in the first register group 110 and the binarized data to be convolved in the third register are updated once, and the current multiple binary convolution temporary result data is obtained based on the updated convolution coefficient and the updated binarized data to be convolved. After the convolution coefficient is updated to a predetermined number of threshold values, the multiple binary convolution temporary result data obtained last time is output as the multiple binary convolution final result data.
[0018] In one embodiment, the composite operation circuit further comprises a fourth register group 160, a fifth register group 180, and a sixth register 190. The fourth register group 160 is used to buffer the multiple filtering product data obtained by the multiplication / binary operation module 150 when performing the filtering operation, and to buffer the multiple binary operation data obtained by the multiplication / binary operation module 150 when performing the binary convolution operation. When performing the binary convolution operation, the addition module 170 adds the previous multiple binary convolution temporary result data buffered by the fifth register group 180 and the multiple binary operation data currently obtained by the multiplication / binary operation module 150 respectively to obtain the current multiple binary convolution temporary result data, and buffers the obtained current multiple binary convolution temporary result data into the fifth register group 180. The sixth register 190 is used to buffer the filtering result data obtained by the addition module 170 when performing the filtering operation.
[0019] As can be seen, the filtering operation and the binary convolution operation are time-division multiplexed using the first register group 110, the multiplication / binary operation module 150, the addition module 170, and the fourth register group 160, thus saving hardware overhead.
[0020] In one embodiment, the composite operation circuit further includes a random access memory 140. The random access memory 140 is used to cache the plurality of filtering coefficients into a first register group 110 during filtering operations and to update the plurality of convolution coefficients to the first register group 110 during binary convolution operations.
[0021] The first register group 110 includes multiple first registers 111. Each first register is used to cache one of the multiple filtering coefficients during filtering operations and one of the multiple convolution coefficients during binary convolution operations. The second register group 120 includes multiple second registers 121, each corresponding to one of the multiple first registers. The multiple second registers are arranged sequentially to form a shift register. The first second register in the shift register sequentially receives the input data to be filtered. Each time a new data to be filtered is received, each second register in the shift register shifts the data to be filtered cached in it to the next second register. The first second register in the shift register caches the new data to be filtered, and the last second register in the shift register outputs or deletes the data to be filtered cached in it. The fourth register group 160 includes multiple fourth registers 161. Each fourth register is used to cache one filtered product data obtained by the multiplication / binary operation module during filtering operations and one binary operation data obtained by the multiplication / binary operation module during binary convolution operations. The fifth register group 180 includes a plurality of fifth registers 181, each of which is used to cache a temporary binary convolution result data obtained by the addition module during binary convolution operations.
[0022] like Figure 1 The example shown illustrates eight first registers 111, eight second registers 121, eight fourth registers 161, and eight fifth registers 181. In other embodiments, there can be m first registers, m second registers, m fourth registers, and m fifth registers, with m filtering coefficients and m convolution coefficients, where m is a natural number greater than or equal to 2. The filtering operation is an FIR filtering operation, and the first, second, and third registers are all N-bit registers, where N is a natural number greater than or equal to 2. Preferably, both the first and second register groups are vector registers, which can improve data loading speed and operation speed.
[0023] likeFigure 1 As shown, the multiplication / binary operation module 150 includes multiple multiplication / binary operation units 151, such as m multiplication / binary operation units ( Figure 1 (where m = 8). Each multiplication / binary operation unit corresponds to a first register 111 and a second register 121. When performing filtering operations, each multiplication / binary operation unit multiplies the filtering coefficients cached in the corresponding first register 111 with the data to be filtered cached in the corresponding second register 121 to obtain a filtered product. Each fourth register 161 caches a filtered product obtained by a corresponding multiplication / binary operation unit 151. When performing binary convolution operations, each multiplication / binary operation unit 151 performs a binary operation on the convolution coefficients cached in the corresponding first register 111 and the binary data to be binary convolved cached in the third register 130 to obtain a binary operation data. Each fourth register 161 caches a binary operation data obtained by a corresponding multiplication / binary operation unit. In one embodiment, each multiplication / binary operation unit includes a multiplication unit and a binary operation unit. During filtering operations, the multiplication unit of the multiplication / binary operation unit is active, i.e., performs multiplication operations, while the binary operation unit of the multiplication / binary operation unit is inactive. During binarized convolution operations, the binary operation unit of the multiplication / binary operation unit is active, i.e., performs binary operations, while the multiplication unit of the multiplication / binary operation unit is inactive.
[0024] like Figure 1 As shown, the addition module 170 includes multiple addition units 171, such as m addition units ( Figure 1 (m=8). Each addition unit 171 corresponds to a multiplication / binary operation unit 151. Each addition unit is used to add a previous temporary binary convolution result data and a current binary operation data obtained by the multiplication / binary operation unit respectively to obtain a current temporary binary convolution result data when performing binary convolution operation. Each fifth register 181 caches a temporary binary convolution result data obtained by the corresponding addition unit 171.
[0025] like Figure 1 As shown, part or all of the addition unit 171 is used to add multiple filtered product data obtained from each multiplication / binary operation unit to obtain filtered result data during filtering operations, and the sixth register 190 caches the filtered result data obtained by the addition module. Figure 1In the example shown, m = 8, and there are 8 addition units, in which the addition unit addO adds the 0th and 4th filter product data obtained by the multiplication / binary operation units (Binconv / MulO, Binconv / Mul4), the addition unit addl adds the 1st and 5th filter product data obtained by the multiplication / binary operation units (Binconv / Mul1, Binconv / Mul5), the addition unit add2 adds the 2nd and 6th filter product data obtained by the multiplication / binary operation units (Binconv / Mul2, Binconv / Mul6), the addition unit add3 adds the 3rd and 7th filter product data obtained by the multiplication / binary operation units (Binconv / Mul3, Binconv / Mul7), the addition unit add4 adds the result of the addition unit addO and the result of the addition unit addl, the addition unit add5 adds the result of the addition unit add2 and the result of the addition unit add3. The addition unit add6 adds the result of the addition unit add4 and the result of the addition unit add5 to obtain the final filter result data, which is finally output to the sixth register 190. The addition unit add7 is not used in the filter operation.
[0026] When the composite operation circuit performs the FIR filter operation, i.e., is used as a FIR filter, the following FIR filter operation is performed:
[0027] where x t-i is the to-be-filtered data cached at a past time; w i is a fixed filter coefficient, y t is the filter result data (i.e., the data after FIR filtering) output at the current t time, which is stored in the sixth register 190, and i is the position or serial number of the corresponding unit, parameter, or data, i.e., 0-7 in the example shown in FIG. 1. Figure 1 That is, in the FIR filter operation, the m filter coefficients w i are respectively cached in the m first registers 111 (for example, i is respectively 0-7), the m to-be-filtered data x t-i are respectively cached in the m second registers 121 (for example, i is respectively 0-7), the multiplication / binary operation module 150 performs the multiplication operation, and the addition module 170 performs the addition operation.
[0028] When the composite operation circuit performs the binary convolution operation, i.e., is used as a binary convolution operation unit, the following binary convolution operation is performed:
[0029]
[0030]
[0031] wherein, x k is the binarized data of the k+1th input to be binarily convolved (e.g. binary data of N bits, such as N=16), which is buffered in the third register 130, the Binconv function is a binary operation function, the HammingWeight function is used to calculate the number of "1"s in the current binary data, such as HammingWeight(0101) is 2, and N is the data bit width of is the k+1th updated convolution coefficient (e.g. binary data of N bits, such as N=16), which is stored in the corresponding first register [i], and is an exclusive or operator, which is updated with the change of k, K+1 is a predetermined number threshold of the number of times of updating the convolution coefficient; y i is the i-th binarily convolved temporary result data, which is stored in the fifth register [i], wherein [i] is the position or serial number of the corresponding unit, parameter or data.
[0032] In the description of the present specification, the description of the terms "one embodiment", "some embodiments", "an example", "a specific example" or "some examples" means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In the present specification, the illustrative description of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art can combine and combine different embodiments or examples described in the present specification.
[0033] Although the embodiments of the present application have been shown and described above, it should be understood that the above embodiments are exemplary and should not be construed as limiting the present application. Those skilled in the art can make changes, modifications and variations to the above embodiments within the scope of the present application.
Claims
1. A composite operational circuit in an integrated circuit, characterized in that, It includes: The first register group is used to cache multiple filtering coefficients when performing filtering operations and multiple convolution coefficients when performing binary convolution operations. The second register group is used to receive and shift multiple data to be filtered input sequentially during filtering operations; The third register is used to receive and buffer the input binarized data to be binarized during binary convolution operations; Multiplication / Binary Operation Module; and Addition module, The multiplication / binary operation module and the addition module perform multiplication and addition operations based on the data to be filtered and the filtering coefficients when performing filtering operations, and perform binary operations and addition operations based on the convolution coefficients and the binary data to be binary convolved when performing binary convolution operations.
2. The composite operational circuit according to claim 1, characterized in that, The first register group caches multiple convolution coefficients each time it performs a binary convolution operation, and the third register caches one set of binarized data to be binarized each time it performs a binary convolution operation. During the binary convolution operation, the multiple convolution coefficients in the first register group are updated multiple times, and the binarized data to be binarized in the third register is updated multiple times. When performing filtering operations, the multiplication / binary operation module multiplies each data to be filtered in the second register group with the corresponding filtering coefficient in the first register group to obtain multiple filtered product data. When performing binary convolution operations, it performs binary operation on the binarized data to be binary convolved in the third register and each convolution coefficient in the first register group to obtain multiple binary operation data. When performing filtering operations, the addition module adds the multiple filtered product data obtained by the multiplication / binary operation module to obtain the filtered result data. When performing binary convolution operations, it adds the previous multiple temporary binary convolution result data to the multiple binary operation data currently obtained by the multiplication / binary operation module to obtain the current multiple temporary binary convolution result data. During binary convolution operations, each time the convolution coefficients in the first register group and the binarized data to be binarized in the third register are updated, the current multiple temporary binary convolution result data is obtained based on the updated convolution coefficients and the updated binarized data to be binarized. After the convolution coefficients and the binarized data to be binarized are updated to a predetermined number of times, the last obtained multiple temporary binary convolution result data is output as the final result data of multiple binary convolutions.
3. The composite operational circuit according to claim 2, characterized in that, It also includes: The fourth register group is used to cache multiple filtered product data obtained by the multiplication / binary operation module during filtering operations, and to cache multiple binary operation data obtained by the multiplication / binary operation module during binary convolution operations. In the fifth register group, when performing binary convolution operations, the addition module adds the previous multiple temporary binary convolution results cached in the fifth register group to the multiple binary operation data currently obtained by the multiplication / binary operation module to obtain the current multiple temporary binary convolution results, and caches the current multiple temporary binary convolution results into the fifth register group. The sixth register is used to cache the filtered result data obtained by the addition module during the filtering operation.
4. The composite operational circuit according to claim 3, characterized in that, The filtering operation and the binary convolution operation are time-division multiplexed using the first register group, the multiplication / binary operation module, the addition module, and the fourth register group.
5. The composite operational circuit according to claim 3, characterized in that, It also includes: A random access memory is used to cache the plurality of filtering coefficients into a first register group during filtering operations and to update the plurality of convolution coefficients into the first register group during binary convolution operations.
6. The composite operational circuit according to claim 3, characterized in that, The first register group includes a plurality of first registers, each of which is used to cache one of the plurality of filtering coefficients when performing filtering operations and to cache one of the plurality of convolution coefficients when performing binary convolution operations; The second register group includes multiple second registers, each corresponding to a plurality of first registers. These second registers are arranged sequentially to form a shift register. The first second register in the shift register sequentially receives input data to be filtered. Upon receiving new data to be filtered, each second register in the shift register shifts its buffered data to the next second register. The first second register in the shift register buffers the new data to be filtered, and the last second register in the shift register outputs or deletes its buffered data to be filtered. The fourth register group includes multiple fourth registers. Each fourth register is used to cache a filtered product data obtained by the multiplication / binary operation module during filtering operations and to cache a binary operation data obtained by the multiplication / binary operation module during binary convolution operations. The fifth register group includes multiple fifth registers, each of which is used to cache a temporary binary convolution result data obtained by the addition module during binary convolution operations.
7. The composite operational circuit according to claim 6, characterized in that, The multiplication / binary operation module includes multiple multiplication / binary operation units. Each multiplication / binary operation unit corresponds to a first register and a second register. When performing filtering operations, each multiplication / binary operation unit multiplies the filtering coefficients cached in the corresponding first register with the data to be filtered cached in the corresponding second register to obtain a filtered product. Each fourth register caches the filtered product obtained by one of the corresponding multiplication / binary operation units. When performing binary convolution operations, each multiplication / binary operation unit performs binary operations on the convolution coefficients cached in the corresponding first register and the binary data to be binary convolved cached in the third register to obtain a binary operation data. Each fourth register caches the binary operation data obtained by one of the corresponding multiplication / binary operation units.
8. The composite operational circuit according to claim 7, characterized in that, The addition module includes multiple addition units, each corresponding to a multiplication / binary operation unit. Each addition unit, during binary convolution operations, adds a previous temporary binary convolution result to the current temporary binary convolution result obtained by the multiplication / binary operation unit. Each fifth register caches the temporary binary convolution result obtained by one addition unit. Some or all of the addition units are used to add the multiple filtered product data obtained from each multiplication / binary operation unit to obtain the filtered result data during filtering operations, and the sixth register caches the filtered result data obtained by the addition module.
9. The composite operational circuit according to claim 3, characterized in that, The filtering operation is an FIR filtering operation. The first register, the second register, and the third register are all N-bit registers, where N is a natural number greater than or equal to 2. Both the first register group and the second register group are vector registers.
10. The composite operational circuit according to claim 7, characterized in that, Each multiplication / binary operation unit includes a multiplication unit and a binary operation unit. During filtering operations, the multiplication unit of the multiplication / binary operation unit is active, while the binary operation unit is inactive. During binarized convolution operations, the binary operation unit of the multiplication / binary operation unit is active, while the multiplication unit is inactive.
11. The composite operational circuit according to claim 10, characterized in that, Each binary operation unit performs the following binary operations: Where, x k Let N be the binarized data to be binarized in the (k+1)th input. The `Binconv` function is a binary operation function, and the `HammingWeight` function is used to calculate the number of "1"s in the current binary data. Data bit width, The convolution coefficients are updated in the (k+1)th iteration, and ⊙ represents the XOR operator. During the operation, The update is performed as k changes, where K+1 is a predetermined threshold for the number of times the convolution coefficients are updated, and i is the position or index of the corresponding unit, parameter, or data.