Airborne image module

Abstract

An airborne image module comprises a processing unit, an interface unit and a power supply system. The processing unit is connected with other functional modules through the interface unit; the processing unit comprises a domestic FPGA. The PL end of the FPGA is connected to the interface unit through a multipath RS422 bus interface, a QSPI input interface, a QSPI output, an LVDS interface and an SPI interface. The PS end of the FPGA provides at least one path of gigabit network interface which is connected to the interface unit through an Ethernet PHY chip; and the PS end of the FPGA is also connected with the storage chip. According to the utility model, on one hand, the cost is low, abundant peripheral interfaces and functional modules are provided, integration with different interface protocols can be facilitated, flexible expansion is supported, and the flexibility, expansibility and maintainability of the system are greatly improved; and on the other hand, the high-efficiency cooperative work of the PL end and the PS end is greatly improved.

Description

TECHNICAL FIELD

[0001] The utility model relates to airborne image processing and storage technical field, especially a kind of airborne image module. BACKGROUND

[0002] Airborne image module refers to the image acquisition and processing system installed on aircraft, for obtaining, transmitting and processing image data, usually equipped with high-resolution camera, sensor, data processing unit and related hardware, can real-time shoot and transmit aerial shooting video data, as video processing and storage module.

[0003] For example, the direct function of existing video encryption storage module is to convert original video signal into digital data by using compression technology, and simultaneously carry out encryption processing, and then store the encrypted digital data. The existing airborne image module has poor flexibility and expandability, and low data transmission processing and storage efficiency.

[0004] Therefore, the present application aims to provide an airborne image module based on domestic high-performance processor. UTILITY MODEL CONTENT

[0005] The utility model aims at overcoming the above-mentioned shortcomings of prior art and providing an airborne image module mainly based on domestic chips, which has low cost, high flexibility and expandability, and high data processing and storage efficiency.

[0006] The technical scheme of the utility model is as follows: an airborne image module, comprising a processing unit, an interface unit and a power system; the processing unit is connected to other functional modules through the interface unit; the processing unit comprises a domestic FPGA, the PL end of the FPGA is connected to the interface unit through a multi-channel RS422 bus interface, a QSPI input interface, a QSPI output, an LVDS interface and an SPI interface; the PS end of the FPGA provides at least one gigabit network interface, which is connected to the interface unit through an Ethernet PHY chip; the PS end of the FPGA is also connected to a storage chip.

[0007] Further, the interface unit comprises connectors XS1-XS6, each connector is connected to different functional modules.

[0008] Further, the processing unit, the interface unit and the power supply system are integrated on the on-board interface board; the connector XS1 is connected between the power supply system and the baseband board, for accessing power supply to power the baseband board; the connector XS2 is connected between the on-board interface board and the baseband board, for control and feedback of the on-board interface board; the connector XS3 is connected between the on-board interface board and the cryptographic machine, for cryptographic machine interface; the connector XS4 is connected between the on-board interface board and the external device, for external interface; the connector XS5 is connected between the on-board interface board and the multi-channel signal processing module, for debugging port; the connector XS6 is connected between the on-board interface board and the image decoding board, for image decoding board interface.

[0009] Further, the power supply system is used for powering the processing unit, and also connected with the connector XS1, for powering the corresponding external functional module.

[0010] Further, the PS end and the PL end of the FPGA are each loaded with a storage chip, including an EMMC memory connected with the PS end, a BGA-SSD memory connected with the GTX interface of the PL end, and an SSD memory connected with the PCIE interface of the PL end.

[0011] Further, the PS end of the FPGA provides at least one UART connected to the connector XS5, for PS end debugging; the PL end of the FPGA provides at least one UART connected to the connector XS2, for control of the baseband board to send state feedback information to the on-board interface board, and control of the on-board interface board to send link control information to the baseband board; the PS end and the PL end of the FPGA each further provide one JTAG debugging interface connected to the connector XS5, for providing debugging access through the standard JTAG debugging interface.

[0012] Further, the PS end of the FPGA is externally connected with an Ethernet PHY chip through an RGMII interface, and the Ethernet PHY chip is further connected to the connector XS5 through a gigabit network.

[0013] Further, the PL end of the FPGA is connected with an LVDS input interface chip through an LVDS output interface, and the LVDS input interface chip is further connected to the SPI input end of the connector XS2; the SPI output end of the connector XS2 is connected with an LVDS output interface chip, and the LVDS output interface chip is further connected to the LVDS input interface of the FPGA PL end; the PL end of the FPGA is connected with another LVDS output interface chip through an SPI output interface, and the LVDS output interface chip is further connected to the LVDS input end of the connector XS3; the LVDS output end of the connector XS3 is connected with another LVDS input interface chip, and the LVDS input interface chip is further connected to the SPI input interface of the FPGA PL end.

[0014] Further, the PL end of the FPGA provides a plurality of UART interfaces respectively connected to corresponding RS422 interface chips, and then performs bidirectional communication with the connector XS4 through the RS422 interface chips; the PL end of the FPGA also provides a plurality of UART interfaces respectively connected to corresponding RS422 interface chips, and then performs bidirectional communication with the connector XS6 through the RS422 interface chips; and the PL end of the FPGA also provides one UART interface connected to an RS422 interface chip, and then performs bidirectional communication with the connector XS3 through the RS422 interface chip.

[0015] Further, the PL end of the FPGA is connected to the connector XS2 through at least one QSPI output interface, and the PL end of the FPGA is also connected to the connector XS2 through at least two QSPI input interfaces.

[0016] The utility model discloses beneficial effects:

[0017] On the one hand, domestic FPGA is adopted, which can provide lower cost and higher controllability compared with imported FPGA; and by setting interfaces for the FPGA, rich peripheral interfaces and function modules are provided, which can be conveniently integrated with different interface protocols (such as SPI, QSPI, RS422, LVDS, etc.), and support flexible expansion, and facilitate customized design according to application requirements.

[0018] On the other hand, data processing and storage are performed by using the PL end and the PS end, since the PL end is a hardware-implemented data processing unit, the system can perform data processing and transmission with extremely low delay, especially for applications requiring high real-time performance such as video data, the PL end can perform real-time data caching and transmission, and is not disturbed by factors such as operating system scheduling, ensuring that data can be quickly circulated to the PS end for storage or further processing, so that the data processing of the PL end can quickly generate results, and the PS end is responsible for storage, further analysis or data export through the network, greatly improving the efficient cooperation of the PL end and the PS end.

[0019] Furthermore, by setting a plurality of connectors, different circuit boards can be connected respectively, not only improving the flexibility, expandability and maintainability of the system, but also enabling different functional board cards to be combined as required, ensuring that the entire system can operate efficiently, and facilitating future upgrading and maintenance. BRIEF DESCRIPTION OF DRAWINGS

[0020] Figure 1 is a structural schematic diagram of an embodiment of the utility model. DETAILED DESCRIPTION

[0021] The utility model will be further described in detail below in combination with the drawings and specific embodiments.

[0022] As Figure 1 shown: an on-board image module, comprising a processing unit, an interface unit and a power supply system, and the processing unit, the interface unit and the power supply system are integrated on an on-board interface board, and the on-board interface board is electrically connected with other circuit boards or electrical devices through the interface unit.

[0023] In this embodiment, the interface unit includes connectors XS1-XS6, wherein the connector XS1 is connected between the +28V power supply and the baseband board, used for accessing the +28V power supply; the connector XS2 is connected between the on-board interface board and the baseband board, used for on-board interface board control and feedback; the connector XS3 is connected between the on-board interface board and the cipher machine, used as a cipher machine interface; the connector XS4 is connected between the on-board interface board and external devices (such as communication interface devices, etc.), used as an external interface; the connector XS5 is connected between the on-board interface board and the multi-channel signal processing module, used as a debugging port; and the connector XS6 is connected between the on-board interface board and the image decoding board, used as an image decoding board interface.

[0024] In this embodiment, the power supply system adopts +28V DC input, and generates voltages required by each device through each DC-DC or LDO chip. Preferably, after the +28V DC input, the voltage is stepped down to 12V by a first DC-DC chip, which can supply power to electrical devices requiring 12V voltage, in addition, the 12V voltage can be further stepped down to the voltage required by the processing unit by a second DC-DC chip to supply power, and the +28V DC input is also connected to the connector XS1, used for supplying power to the baseband board.

[0025] In this embodiment, the processing unit is implemented by using FPGA. Specifically, in this embodiment, according to the FPGA and peripheral connection relationship and resource management cost scheme, the chip of Fudan Micro FMQL45T900-N is preferably used, which has two characteristics of PL end (programmable logic end) and PS end (processor system end). The FPGA of this embodiment mainly realizes network communication, EMMC, DDR3, RS422, LVDS, QSPI and other data interface communication. Among them, the PL part of the FPGA realizes QSPI, LVDS, RS422, UART and other interface communication through IO and external interface chips; the PS part of the FPGA is connected with external gigabit network port, debugging serial port and EMMC storage interface, and the gigabit network port is used for communication and debugging.

[0026] The specific circuit connection relationship of the FPGA is as follows:

[0027] (1) The PS end and the PL end of the FPGA are connected with storage chips, specifically, the PS end of the FPGA is connected with a 32GB EMMC storage, which is used to store a file system, an operating system and an upgradable program, and preferably uses a SMFC32GBMP device of Guowei. The GTX interface of the PL end of the FPGA is connected with a 60GB BGA-SSD, i.e. a solid state disk adopting a BGA packaging technology, which is used for external data storage and export; the PL end of the FPGA is connected with an SSD (solid state disk) through a PCIE interface, which is used for data storage and reading. In addition, the PS end and the PL end of the FPGA each uses a 512GB DDR3L to form a 32-bit bandwidth cache unit, and the DDR3L chip selects an XZF41J256M16 of Zhongtianxingkong. The PL end of the FPGA is configured with a Nor Flash storage, which adopts two EFM25F128A to form a 32MB capacity, and is used to store a configuration file of the FPGA.

[0028] (2) The PS end of the FPGA provides one-way UART connection to the connector XS5, which is used for PS end debugging. The PL end of the FPGA provides one-way UART connection to the connector XS2, which is used for sending state feedback information from the baseband board to the airborne interface board, and sending link control information from the airborne interface board to the baseband board.

[0029] (3) The PS end and the PL end of the FPGA each provide one-way JTAG debugging interface connection to the connector XS5, which provides debugging access through a standard JTAG debugging interface, i.e. there is a DAP controller in the chip internal PS end, which provides debugging support for the PS system through the JTAG debugging interface; and there is a TAP controller in the PL part, which provides debugging support for the PL part.

[0030] (4) The PS end of the FPGA is externally connected with an Ethernet PHY chip through an RGMII interface, and the Ethernet PHY chip is connected to the connector XS5 through a gigabit network. The FPGA chip FMQL45T900-N has two Ethernet controllers, which can provide two-way gigabit Ethernet and support 1000 / 100 / 10Mbps self-adaptation. The JXYI8211 gigabit Ethernet PHY chip of Chengdu Xinyi in China is preferably adopted in the embodiment. Through the RGMII interface of the PS end of the complex FPGA chip, two-way 1000 / 100 / 10Mbps self-adaptive Ethernet interface can be realized. The airborne image module of the embodiment only needs one-way gigabit Ethernet, i.e. only needs to use one-way RGMII interface to externally connect with one Ethernet PHY chip.

[0031] (5) The PL end of the FPGA is connected to the LVDS input interface chip through the LVDS output interface, and then connected to the SPI input end of the connector XS2 through the LVDS input interface chip; the SPI output end of the connector XS2 is connected to the LVDS output interface chip, and then connected to the LVDS input interface of the PL end of the FPGA through the LVDS output interface chip, thereby forming the bidirectional data transmission between the airborne interface board and the baseband board. The LVDS input interface chip has two differential input interfaces, which are used to send data to the baseband board, i.e. the LVDS differential signal output by the PL end of the FPGA is converted into a single-ended signal by the LVDS input interface chip and output to the connector XS2; the LVDS output interface chip has two differential output interfaces, which are used to receive external data, i.e. the single-ended signal of the external baseband board is converted into an LVDS differential signal by the LVDS output interface chip and input into the FPGA.

[0032] In addition, the PL end of the FPGA is connected to another LVDS output interface chip through the SPI output interface, and then connected to the LVDS input end of the connector XS3 through the LVDS output interface chip; the LVDS output end of the connector XS3 is connected to another LVDS input interface chip, and then connected to the SPI input interface of the PL end of the FPGA through the LVDS input interface chip, thereby forming the bidirectional data transmission between the airborne interface board and the cryptographic machine. The LVDS input interface chip is used to receive external image data, i.e. the external LVDS differential signal is converted into a single-ended signal and input into the FPGA after being input into the LVDS input interface chip; the LVDS output interface chip is used to send data to the cryptographic machine, i.e. the single-ended signal output by the PL end of the FPGA is converted into a differential signal by the LVDS output interface chip and output to the connector XS3.

[0033] The above-mentioned LVDS output interface chip adopts HWD90LV047A of Chengdu Huaweixing, and the LVDS input interface chip adopts HWD90LV048A of Chengdu Huaweixing.

[0034] (6) RS-422 communication interface:

[0035] ① In the PL end of the FPGA, four UART interfaces are provided to connect four RS422 interface chips respectively, and then bidirectional communication is carried out with the connector XS4 through the four RS422 interface chips. The RS422 interface chip selects the CP3490S chip of Chuantuxing. The specific connection relationship is shown in Table 1:

[0036] Table 1: Connector XS4-RS422 external interface definition

[0037]

[0038] Among them, in the bidirectional communication between the four RS422 interface chips and the connector XS4, TX1 and RX1 are used as the first transceiving signal, TX2 and RX2 are used as the second transceiving signal, TX3 and RX3 are used as the third transceiving signal, and the corresponding RS422 interface chip is used as a reserved interface; TX4 and RX4 are used as the fourth transceiving signal, and only RX4 signal works here.

[0039] 2) In the PL end of the FPGA, 3-way UART interfaces are further provided to connect another 3 pieces of RS422 interface chips, and then the bidirectional communication is performed between the 3 pieces of RS422 interface chips and the connector XS6. The specific connection relationship is shown in Table 2:

[0040] Table 2: RS422 external interface definition of connector XS6

[0041]

[0042] 3) In the PL end of the FPGA, 1-way UART interface is further provided to connect 1 piece of RS422 interface chip, and then the bidirectional communication is performed between the RS422 interface chip and the connector XS3, that is, the bidirectional serial port communication between the PL end of the FPGA and the cryptographic machine is realized, which is used for sending control instructions between the on-board interface board and the cryptographic machine, sending state information from the cryptographic machine to the on-board interface board, etc.

[0043] (7) The PL end of the FPGA is connected to the connector XS2 through one-way QSPI output interface, and the PL end of the FPGA is further connected to the connector XS2 through two-way QSPI input interface.

[0044] The on-board image module of the embodiment is mainly installed in the internal of the user's case, and the form is a non-standard form card. The communication is performed with the external device through the network port, QSPI, LVDS, RS422 and other interfaces.

[0045] Based on the above, in the embodiment, the main performance requirements of the PL end of the FPGA are as follows:

[0046] 1) Interact with external devices through 8-way RS422 bus interface, 2-way QSPI input, 1-way QSPI output, 2-way LVDS, and 2-way SPI;

[0047] 2) Use 1-way PCIE external SSD and 1-way GTX external BGA-SSD for data storage and reading.

[0048] The main performance requirements of the PS end are as follows:

[0049] 1) 1-way gigabit network interface;

[0050] 2) 1-way UART for PS end debugging;

[0051] 3) 1 lane EMMC for system file storage.

[0052] The working principle of the embodiment is that the FPGA PL end transceives data of each lane of RS422 / QSPI / SPI and the like, buffers the data, and transmits the buffered data from the PL end to the PS end through an AXI bus to realize data storage at the PS end. The terminal mainly realizes receiving of video data through QSPI and LVDS interfaces, and exporting of stored video data through a gigabit network. For example, when an onboard image module is externally connected with a baseband board, a cipher machine, a multi-channel signal processing module, an image decoding board and external equipment, 28VDC is supplied to the baseband board through the connector XS1. The onboard interface board performs bidirectional data transmission with the baseband board through the QSPI and LVDS interfaces through the connector XS2, for example, to realize receiving of video data, and conversion of raw video signals into digital data. The onboard interface board performs bidirectional data transmission with the cipher machine through the SPI / LVDS mode through the connector XS3, for example, to receive processed video data sent by the baseband board, and to perform encryption processing on the video data; the processed data can be stored in a SSD solid state disk. The onboard interface board performs bidirectional communication with the external equipment through the RS422 interface through the connector XS4, to send corresponding instructions, such as parameter binding.

[0053] It can be understood that the connectors XS1 to XS6 of the embodiment are not limited to connection with the baseband board, the cipher machine, the multi-channel signal processing module, the image decoding board and the like, but can also be connected with other circuit boards according to requirements, and the above is only a preferred embodiment of the application.

[0054] In summary, the utility model discloses one aspect adopts the domestic FPGA, compared with imported FPGA can provide lower cost and higher controllability, and through the interface setting to FPGA, provided abundant peripheral interface and function module, can conveniently integrate with different interface agreement (such as SPI, QSPI, RS422, LVDS etc.), and support flexible extension, facilitate according to application demand to carry out the customized design. On the other hand, utilize its PL end and PS end to carry out data processing and storage, because the PL end is the data processing unit of hardware implementation, system can carry out data processing and transmission with very low delay, especially for the application of video data etc. need high real-time, the PL end can carry out data cache and transmission in real time, will not be interfered by operating system scheduling etc. factor, ensure that data can flow to the PS end and store or further process quickly, so that the data processing of PL end can generate result quickly, and the PS end is responsible for storage, further analysis or through network carries out data guide, greatly improve the efficient cooperation of PL end and PS end. Furthermore, through setting up multiple connectors, can connect different circuit boards respectively, not only improve the flexibility, expandability and maintainability of system, but also can carry out the combination of different function board according to the need, ensure that the whole system can operate efficiently, facilitate the upgrading and maintenance of later.

Claims

1. An on-board image module comprising a processing unit, an interface unit and a power supply system; characterized in that, The processing unit is connected with other functional modules through an interface unit; the processing unit comprises a domestic FPGA, a PL end of the FPGA is connected with the interface unit through a multi-path RS422 bus interface, a QSPI input interface, a QSPI output, an LVDS interface and an SPI interface; a PS end of the FPGA provides at least one path of a gigabit network interface, and is connected with the interface unit through an Ethernet PHY chip; the PS end of the FPGA is also connected with a storage chip.

2. The on-board image module of claim 1, wherein, The interface unit comprises connectors XS1 to XS6, each of which is connected with different functional modules.

3. The on-board image module of claim 2, wherein, The processing unit, the interface unit and a power supply system are integrated on a machine-mounted interface board; the connector XS1 is connected between the power supply system and a baseband board, and is used for accessing power supply to supply power for the baseband board; the connector XS2 is connected between the machine-mounted interface board and the baseband board, and is used for control and feedback of the machine-mounted interface board; the connector XS3 is connected between the machine-mounted interface board and a cipher machine, and is used as a cipher machine interface; the connector XS4 is connected between the machine-mounted interface board and external equipment, and is used as an external interface; the connector XS5 is connected between the machine-mounted interface board and a multi-channel signal processing module, and is used as a debugging port; and the connector XS6 is connected between the machine-mounted interface board and an image decoding board, and is used as an image decoding board interface. The power supply system is used for supplying power for the processing unit, and is also connected with the connector XS1, which is used for supplying power for corresponding external functional modules.

4. An airborne image module according to claim 2 or 3, characterized in that, The PS end and the PL end of the FPGA are both provided with storage chips, including an EMMC memory connected with the PS end, a BGA-SSD memory connected with a GTX interface of the PL end and an SSD memory connected with a PCIE interface of the PL end.

5. The on-board image module of claim 1, wherein, The PS end of the FPGA provides at least one path of a UART connected with the connector XS5, which is used for debugging of the PS end; the PL end of the FPGA provides at least one path of a UART connected with the connector XS2, which is used for sending state feedback information from the baseband board to the machine-mounted interface board and sending link control information from the machine-mounted interface board to the baseband board; the PS end and the PL end of the FPGA are also respectively provided with one path of a JTAG debugging interface connected with the connector XS5, which provides debugging access through a standard JTAG debugging interface.

6. The on-board image module of claim 3, wherein, The PS end of the FPGA is externally connected with an Ethernet PHY chip through an RGMII interface, and the Ethernet PHY chip is connected with the connector XS5 through a gigabit network.

7. The on-board image module according to claim 2 or 3, characterized in that, ​ 8. The on-board image module according to claim 2 or 3, characterized in that, The PL end of the FPGA is connected to the LVDS input interface chip through the LVDS output interface, and then connected to the SPI input end of the connector XS2 through the LVDS input interface chip; the SPI output end of the connector XS2 is connected to the LVDS output interface chip, and then connected to the LVDS input interface of the FPGA PL end through the LVDS output interface chip; the PL end of the FPGA is connected to another LVDS output interface chip through the SPI output interface, and then connected to the LVDS input end of the connector XS3 through the LVDS output interface chip; the LVDS output end of the connector XS3 is connected to another LVDS input interface chip, and then connected to the SPI input interface of the FPGA PL end through the LVDS input interface chip.

9. The on-board image module according to claim 2 or 3, characterized in that, The PL end of the FPGA provides a plurality of UART interfaces connected to the corresponding RS422 interface chips, and then performs bidirectional communication with the connector XS4 through the RS422 interface chips; the PL end of the FPGA also provides a plurality of UART interfaces connected to the corresponding RS422 interface chips, and then performs bidirectional communication with the connector XS6 through the RS422 interface chips; and the PL end of the FPGA also provides a UART interface connected to the RS422 interface chip, and then performs bidirectional communication with the connector XS3 through the RS422 interface chip.

10. The on-board image module according to claim 2 or 3, characterized in that, The PL end of the FPGA is connected to the connector XS2 through at least one QSPI output interface, and the PL end of the FPGA is also connected to the connector XS2 through at least two QSPI input interfaces.

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