Groove type silicon carbide MOSFET device

Abstract

The utility model discloses a groove type silicon carbide MOSFET device, which belongs to the technical field of power semiconductor devices and comprises a second conductive type substrate, a second conductive type drift region, polycrystalline silicon, a gate dielectric layer, a CSL layer and a first conductive type masking layer. The first conductive type shielding layer is also provided with a first conductive type grounding region which is arranged at the bottom of the gate dielectric layer, and the top of the first conductive type grounding region is connected with the bottom of the gate dielectric layer; the first conductive type base regions are arranged on the two sides of the first conductive type grounding region, and the tops of the first conductive type base regions are connected with the gate dielectric layer; and the second conductive type grounding base region is arranged at the bottoms of the first conductive type grounding region and the first conductive type base region. By introducing the first conductive type grounding region, the first conductive type base region and the second conductive type grounding base region into the first conductive type masking layer, the JFET resistance is reduced, the conduction loss is reduced, and the short-circuit tolerance time is prolonged.

Description

TECHNICAL FIELD

[0001] The utility model relates to power semiconductor device technical field, especially a kind of trench type silicon carbide MOSFET device. BACKGROUND

[0002] Silicon carbide is a wide bandgap compound semiconductor, and is one of the representatives of the third generation semiconductor materials. Compared with traditional Si materials, it has 3 times larger bandgap and 10 times larger critical breakdown field, and also has higher electron saturation drift speed, thermal conductivity and other advantages. This makes the devices based on silicon carbide material have broad application prospects in the fields of high power, high temperature, high voltage, radiation resistance, etc.

[0003] SiC MOSFET is the most widely used silicon carbide device on the market. Compared with traditional Si MOSFET, SiC MOSFET of the same voltage level and current capacity has smaller on-resistance, which can effectively reduce the on-state loss of power devices during operation. In addition, it has small parasitic capacitance, fast switching speed, high thermal conductivity and high temperature resistance, etc. Therefore, SiC MOSFET is favored by new energy vehicles, photovoltaic power generation and other fields. Silicon carbide MOSFET as a power device is usually a vertical device, which has two typical structures: planar and trench. Due to the poor interface state of the current silicon carbide material and the gate oxide, the channel mobility is too low, which makes the on-state characteristics of planar MOSFET have a large distance compared with the theoretical limit. In addition, the cell size of planar MOSFET has its theoretical limit. The trench device developed by etching process can realize smaller cell size, and the channel has higher mobility, so it effectively improves the chip integration, greatly reduces the on-resistance, and has great development potential.

[0004] As the core device of the system, the performance of SiC MOSFET device has a great influence on the system. Compared with Si trench MOSFET, when SiC trench MOSFET is in blocking state, the gate oxide layer will deteriorate and fail under the action of relatively large electric field. In order to protect the gate oxide layer, various SiC trench MOSFETs with grounded P-type mask layer have been studied in academia and industry. However, the grounded P-type mask layer re-introduces JFET resistance, which increases the on-state loss of the device. Although the floating P-type mask layer can protect the gate oxide layer while improving the static characteristics of the device, the SiC trench MOSFET with floating P-type mask layer has slow switching speed and dynamic switching characteristics degradation. In addition, compared with Si IGBT, due to higher power density and drain current unsaturation caused by short channel effect, SiC MOSFET has smaller short circuit resistance time, which brings severe challenges to the performance and reliability of the whole system.

[0005] It should be noted that the information disclosed in the background section of the utility model is only intended to deepen the understanding of the general background of the utility model, and should not be regarded as acknowledging or implying in any form that the information constitutes prior art known to those skilled in the art. Content of the utility model

[0006] The utility model discloses a trench type silicon carbide MOSFET device to solve the problem that the grounding P type mask layer reintroduces JFET resistance and increases the on-state loss of the device.

[0007] To solve the above technical problems, the utility model provides a trench type silicon carbide MOSFET device, which comprises a second conductive type substrate, a second conductive type drift region, polysilicon, a gate dielectric layer, a CSL layer and a first conductive type mask layer, and the first conductive type mask layer is further provided with:

[0008] A first conductive type ground region is arranged at the bottom of the gate dielectric layer, and the top of the first conductive type ground region is connected with the bottom of the gate dielectric layer;

[0009] A second conductive type ground base region is arranged on both sides of the first conductive type ground region, and the top of the second conductive type ground base region is connected with the gate dielectric layer;

[0010] A second conductive type base region is arranged at the bottom of the first conductive type ground region and the second conductive type ground base region.

[0011] Preferably, the top of the CSL layer is further provided with a first conductive type well region.

[0012] Preferably, the top of the first conductive type well region is further provided with a first conductive type source region.

[0013] Preferably, the utility model further comprises a second conductive type source region, one side of the second conductive type source region is connected with the gate dielectric layer, and the other side is connected with the first conductive type source region.

[0014] Preferably, the utility model further comprises a source metal, the source metal is arranged at the top of the first conductive type source region and the second conductive type source region, and the source metal forms ohmic contact with the first conductive type source region and the second conductive type source region.

[0015] Preferably, the top of the polysilicon is arranged with a gate metal, and the source metal and the gate metal have a spacing.

[0016] Preferably, the second conductive type base region and the first conductive type ground region are electrically connected with the source metal.

[0017] Preferably, the back surface of the second conductive type substrate is further provided with a drain metal, and the drain metal forms an ohmic contact with the second conductive type substrate.

[0018] Preferably, the first conductive type is P type, and the second conductive type is N type.

[0019] Preferably, the first conductive type is N type, and the second conductive type is P type.

[0020] In the trench type silicon carbide MOSFET device provided by the utility model, the first conductive type grounding base area, the first conductive type base area and the second conductive type grounding base area are introduced in the first conductive type masking layer, here, only the first conductive type is P type, and the second conductive type is N type are taken as examples to describe the effect, the first conductive type base area hole barrier height is adjusted by gate bias, so that the first conductive type masking layer is floating under certain gate bias, the JFET resistance caused by the first conductive type masking layer of the device is reduced, and the on-resistance of the device and the on-loss in the dynamic switching process are optimized. In addition, when the device is short-circuited, the temperature in the device rises, the intrinsic carrier concentration rises, the first conductive type base area hole barrier height decreases, the first conductive type masking layer is out of the floating state, and is electrically connected with the first conductive type grounding base area again, so that the JFET resistance value increases to the JFET resistance value before the first conductive type masking layer is not floating, and the saturation current of the device decreases. Compared with the traditional device with the same on-resistance, the short-circuit resistance time of the device is also reduced. BRIEF DESCRIPTION OF DRAWINGS

[0021] Those skilled in the art will understand that the drawings provided are for a better understanding of the utility model, and do not constitute any limitation on the scope of the utility model. Among them:

[0022] Figure 1 It is a structure diagram of a silicon carbide trench type MOSFET device provided with a first conductive type masking layer under a gate slot;

[0023] Figure 2 It is a structure schematic diagram of the trench type silicon carbide MOSFET device of the utility model embodiment one;

[0024] Figure 3 It is a forward characteristic simulation diagram of the trench type silicon carbide MOSFET device of the utility model embodiment one;

[0025] Figure 4 It is a short-circuit characteristic simulation diagram of the trench type silicon carbide MOSFET device of the utility model embodiment one

[0026] Figure 5 It is a structure schematic diagram of the first conductive type masking layer of the utility model embodiment two;

[0027] Figure 6 Structure diagram of forming CSL layer and first conductive type well region of the second embodiment of the utility model;

[0028] Figure 7 Structure diagram of ion implantation forming first conductive type source region of the second embodiment of the utility model;

[0029] Figure 8 Structure diagram of ion implantation forming second conductive type source region of the second embodiment of the utility model;

[0030] Figure 9 Structure diagram of etching out gate slot of the second embodiment of the utility model;

[0031] Figure 10 Structure diagram of ion implantation forming second conductive type ground base region of the second embodiment of the utility model;

[0032] Figure 11 Structure diagram of ion implantation forming first conductive type base region of the second embodiment of the utility model;

[0033] Figure 12 Structure diagram of ion implantation forming first conductive type ground region of the second embodiment of the utility model;

[0034] Figure 13 Structure diagram of forming gate dielectric layer and polysilicon of the second embodiment of the utility model;

[0035] Figure 14 Structure diagram of depositing metal of the second embodiment of the utility model.

[0036] In the drawings:

[0037] 1, source metal; 2, gate metal; 3, first conductive type source region; 4, second conductive type source region; 5, first conductive type well region; 6, CSL layer; 7, first conductive type mask layer; 8, polysilicon; 9, gate dielectric layer; 10, second conductive type drift region; 11, second conductive type substrate; 12, drain metal; 13, first conductive type base region; 14, second conductive type ground base region; 15, first conductive type ground region. DETAILED DESCRIPTION

[0038] In order to make the purpose, advantages and characteristics of the present application more clear, the present application will be further described in detail below in combination with the drawings and specific embodiments. It should be noted that the drawings are all very simplified and not drawn in proportion, and are only used to facilitate and clearly assist the purpose of describing the embodiments of the present application. In addition, the structures shown in the drawings are often a part of the actual structures. In particular, the emphasis of each drawing needs to be different, and sometimes different proportions are used.

[0039] As used in the present application, the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise. The term "or" is generally employed in its sense including "and / or" unless the context clearly dictates otherwise. The term "plurality" is generally employed in its sense including "at least one" unless the context clearly dictates otherwise. The term "at least two" is generally employed in its sense including "two or more" unless the context clearly dictates otherwise. In addition, the terms "first," "second," "third," etc. are used only for descriptive purposes and should not be construed as indicating or implying relative importance or an indicated number of technical features. Thus, features defined with "first," "second," "third" can explicitly or implicitly include one or at least two of the features. The term "proximal" generally refers to the end closer to the operator, and the term "distal" generally refers to the end closer to the patient. "One" and "the other" and "proximal" and "distal" generally refer to two parts corresponding to each other, which not only includes the end point. The terms "mounting," "connecting," and "connecting" should be understood broadly. For example, it can be fixedly connected, or it can be detachably connected, or it can be integrated; it can be mechanically connected, or it can be electrically connected; it can be directly connected, or it can be indirectly connected through an intermediate medium; it can be the internal communication or interaction of two elements. In addition, as used in the present application, a component disposed in another component generally only indicates that there is a connection, coupling, cooperation or transmission relationship between the two components, and the two components can be directly connected, coupled, cooperated or transmitted, or indirectly connected, coupled, cooperated or transmitted through an intermediate component. Unless the context clearly indicates otherwise, it cannot be understood as indicating or implying the spatial position relationship between the two components, i.e. one component can be in any orientation inside, outside, above, below or one side of another component. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0040] Research has found that for SiC trench MOSFETs with a grounded P-type mask layer, i.e. a first conductivity type mask layer 7, as shown in Figure 1 Although the introduction of the first conductivity type mask layer 7 can play a role in protecting the gate oxide layer, i.e. the gate dielectric layer 9, it re-introduces the JFET resistance, increasing the on-state loss of the device. Even if a floating first conductivity type mask layer 7 is used, there are still switching characteristic problems.

[0041] The core idea of the utility model lies in that a first conductive type grounding region, a first conductive type base region and a second conductive type grounding base region are introduced in the first conductive type mask layer, only the first conductive type is P type and the second conductive type is N type are used for effect description, the height of the hole barrier of the first conductive type base region is adjusted by the gate bias, the first conductive type mask layer is floating under certain gate bias, the JFET resistance caused by the first conductive type mask layer connected with the ground is reduced, the on-resistance of the device and the on-loss in the dynamic switching process are optimized.

[0042] Example one

[0043] Specifically, refer to Figures 2-4 , which is the schematic diagram of the utility model example one. As shown in Figure 2 , a trench type silicon carbide MOSFET device, comprising a second conductive type substrate 11, a second conductive type drift region 10, a polysilicon 8, a gate dielectric layer 9, a CSL layer 6 and a first conductive type mask layer 7, the first conductive type mask layer 7 is further provided with:

[0044] A first conductive type grounding region 15 is arranged at the bottom of the gate dielectric layer 9, and the top of the first conductive type grounding region 15 is connected with the bottom of the gate dielectric layer 9.

[0045] A first conductive type base region 13 is arranged on both sides of the first conductive type grounding region 15, and the top of the first conductive type base region 13 is connected with the gate dielectric layer 9.

[0046] A second conductive type grounding base region 14 is arranged at the bottom of the first conductive type grounding region 15 and the first conductive type base region 13.

[0047] The first conductive type substrate 11 is provided with the second conductive type drift region 10, the second conductive type drift region 10 is provided with the first conductive type mask layer 7, the first conductive type mask layer 7 is provided with the second conductive type grounding base region 14, the second conductive type grounding base region 14 is provided with the first conductive type grounding region 15, the first conductive type grounding region 15 is provided with the first conductive type base region 13, and the first conductive type grounding region 15 is provided with the gate dielectric layer 9 and the polysilicon 8.

[0048] Exemplarily, the materials of the second conductive type source region 4, the first conductive type source region 3, the first conductive type well region 5, the CSL layer 6, the first conductive type mask layer 7, the first conductive type base region 13, the second conductive type ground base region 14, the first conductive type contact region 15, the second conductive type drift region 10 and the second conductive type substrate 11 are all silicon carbide, and the material of the gate dielectric layer 9 is silicon oxide.

[0049] In one embodiment, the first conductive type is P type and the second conductive type is N type. Therefore, the first conductive type base region 13 can be doped with P type dopants, such as boron. However, in other embodiments of the present application, the carriers can be holes, in which case the first conductive type is N type, and the second conductive type is P type, which will not be described herein.

[0050] More preferably, the first conductive type mask layer 7 is not grounded, but needs to have a certain contact area with the gate dielectric layer 9, so that the potential of the floating first conductive type mask layer 7 can be adjusted by the gate bias.

[0051] Exemplarily, when the first conductive type is P type and the second conductive type is N type, the polysilicon 8 is N type polysilicon.

[0052] Herein, only the first conductive type is P-type and the second conductive type is N-type as an example. When the gate bias of the device is greater than zero, the first conductive type base region 13 is gradually depleted under the action of the gate bias and the PN junction formed by the second conductive type grounded base region 14 and the first conductive type base region 13. When the gate bias reaches a certain value, the first conductive type base region 13 is completely depleted. At this time, a hole barrier is formed between the first conductive type mask layer 7 and the first conductive type grounded base region, preventing the movement of holes between the two regions. The first conductive type mask layer 7, which is originally grounded through the first conductive type base region 13, is in a floating state. Under the action of the gradually increasing gate bias and drain-source voltage, the potential of the floating first conductive type mask layer 7 rises, thereby reducing the JFET resistance value caused by the introduction of the first conductive type mask layer 7, and reducing the on-resistance and on-loss of the device. When the gate bias of the device is less than a certain gate bias (which can be adjusted by changing the doping concentration of the first conductive type base region 13 and the second conductive type grounded base region 14, and the thickness of the gate dielectric layer 9), the first conductive type base region 13 is not completely depleted, and the first conductive type mask layer 7 is still in a grounded state, thereby avoiding the degradation of the dynamic switching characteristics caused by continuous floating. In addition, when the device is short-circuited, the continuously rising temperature increases the intrinsic carrier concentration of the device, so that the first conductive type base region 13, which is originally in a depleted state under the control of the gate bias, is no longer depleted, reducing the height of the hole barrier formed in the first conductive type base region 13, so that the first conductive type mask layer 7 is re-grounded, and the potential of the first conductive type mask layer 7 becomes the ground potential. Thus, the JFET resistance value increases to the original JFET resistance value before the first conductive type mask layer 7 is not floating, and the saturation current of the device decreases. Compared with the conventional device with the same on-resistance, the short-circuit tolerance time of the device is increased, as shown in the forward characteristic and on-state characteristic simulation diagram of the improved structure and the conventional structure. Figure 3 and Figure 4 The forward characteristic and on-state characteristic simulation diagram of the improved structure and the conventional structure.

[0053] It should be noted that the doping concentration of the first conductive type base region 13 and the second conductive type grounded base region 14 needs to be accurately controlled, so that both of them cannot be completely depleted without gate bias.

[0054] In addition, during preparation, the first conductive type grounded region 15, the second conductive type grounded base region 14 and the first conductive type base region 13 can be ion implanted after the gate trench etching, or ion implanted before the epitaxial formation of the CSL layer 6, which is not specifically limited herein.

[0055] In an embodiment, the first conductive type grounded region 15 and the first conductive type source region 3 can be formed synchronously or in steps.

[0056] Specifically, the top of the CSL layer 6 is further provided with a first-conductivity-type well region 5. The CSL layer 6 is located below the left and right sides of the gate dielectric layer 9, the top of the polysilicon 8 has a gate metal 2, the top of the first-conductivity-type source region 3 and the second-conductivity-type source region 4 has a source metal 1, and the source metal 1 simultaneously forms an ohmic contact with the first-conductivity-type source region 3 and the second-conductivity-type source region 4. The bottom of the second-conductivity-type substrate 11 is provided with a drain metal 12, and the drain metal 12 forms an ohmic contact with the second-conductivity-type substrate 11. The top of the first-conductivity-type well region 5 is further provided with the first-conductivity-type source region 3 and the second-conductivity-type source region 4, one side of the second-conductivity-type source region 4 is connected with the gate dielectric layer 9, and the other side is connected with the first-conductivity-type source region 3. The first-conductivity-type source region 3 and the second-conductivity-type source region 4 are laterally arranged on the top of the first-conductivity-type well region 5.

[0057] The source metal 1 is further included, and the source metal 1 is arranged on the top of the first-conductivity-type source region 3 and the second-conductivity-type source region 4, and simultaneously forms an ohmic contact with the first-conductivity-type source region 3 and the second-conductivity-type source region 4. The top of the polysilicon 8 is arranged with the gate metal 2, and the source metal 1 and the gate metal 2 have a spacing therebetween.

[0058] Specifically, the second-conductivity-type ground base region 14 and the first-conductivity-type ground region 15 are electrically connected with the source metal 1 (not shown in the figure). The second-conductivity-type ground base region 14 and the first-conductivity-type ground region 15 are connected with the source metal 1 through layout design.

[0059] Specifically, the back of the second-conductivity-type substrate 11 is further provided with the drain metal 12, and the drain metal 12 forms an ohmic contact with the second-conductivity-type substrate 11.

[0060]

Embodiment Two

[0061] Based on the same technical concept, the disclosure further provides a manufacturing method of a trench-type silicon carbide MOSFET device. Specifically, refer to Figures 5-14 which is a schematic diagram of the embodiment two of the utility model. The manufacturing method of the trench-type silicon carbide MOSFET device comprises the following steps:

[0062] S1, a second-conductivity-type substrate 11 is provided, the front surface of the second-conductivity-type substrate 11 has a second-conductivity-type drift region 10, and a first-conductivity-type mask layer 7 is formed in the second-conductivity-type drift region 10 through first-conductivity-type ion implantation. As shown in Figure 5As shown, the top of the second conductivity type substrate 11 has a second conductivity type drift region 10. The second conductivity type substrate 11 is first cleaned, and the area to be ion implanted is defined by photoresist (not labeled). First conductivity type ion implantation is performed on the second conductivity type drift region 10 to form a first conductivity type masking layer 7.

[0063] In one embodiment, the first conductivity type is P-type, the second conductivity type is N-type, the first conductivity type ion is P-type, and the second conductivity type ion is N-type. In this embodiment, only the first conductivity type being P-type and the second conductivity type being N-type will be described. Therefore, the base region 13 of the first conductivity type can be doped with a P-type dopant, such as boron. However, in other embodiments of this invention, the charge carrier can be a hole, in which case the first conductivity type is N-type, and the corresponding second conductivity type is P-type, which will not be elaborated further here.

[0064] For example, after forming the first conductivity type masking layer 7, several desired conductive regions are formed on top of the first conductivity type masking layer 7, such as... Figures 6-8 As shown, a gate trench is formed by etching the front side of the second conductivity type substrate 11, such as... Figure 9 As shown, after the grid trench is formed, a first conductive type grounding area 15, a first conductive type base area 13, and a second conductive type grounding base area 14 are formed in the first conductive type masking layer 7. The tops of the first conductive type grounding area 15, the first conductive type base area 13, and the second conductive type grounding base area 14 are all connected to the bottom of the grid trench.

[0065] Specifically, forming several desired conductive regions in the first conductive type masking layer 7 includes:

[0066] like Figure 6 As shown, a CSL layer 6 of the second conductivity type is epitaxially formed on the drift region 10 of the second conductivity type, and a well region 5 of the first conductivity type is formed by second conductivity type ion implantation on the CSL layer 6.

[0067] like Figure 7 As shown, first conductivity type ion implantation is performed in the first conductivity type well region 5 to form two first conductivity type source regions 3 with a gap.

[0068] like Figure 8 As shown, second conductivity type ion implantation is performed between the first conductivity type source regions 3 to form a second conductivity type source region 4, which is disposed on top of the first conductivity type well region 5.

[0069] In one embodiment, the first-conductivity-type mask layer 7 is formed by direct vertical ion implantation before the formation of the CSL layer 6 by epitaxy. The concave first-conductivity-type base region 13 is initially in a near-rectangular shape, and becomes concave after the etching of the inverse-tapered gate trench, and the gate dielectric layer 9 is formed after the etching of the inverse-tapered gate trench.

[0070] S2, as shown in the first-conductivity-type mask layer 7, a second-conductivity-type ion implantation is performed to form a second-conductivity-type ground base region 14. Figure 10

[0071] S3, as shown in the second-conductivity-type ground base region 14, a first-conductivity-type ion implantation is performed at the top of the second-conductivity-type ground base region 14 to form a first-conductivity-type base region 13. The first-conductivity-type base region 13 is located on top of the second-conductivity-type ground base region 14. Figure 11

[0072] S4, as shown in the first-conductivity-type base region 13, a first-conductivity-type ion implantation is performed to form a first-conductivity-type gate region 15, and annealing is performed for activation, wherein the bottom of the first-conductivity-type gate region 15 is connected to the top of the second-conductivity-type ground base region 14, and the two sides are connected to the first-conductivity-type base region 13. Figure 12

[0073] In one embodiment, the first-conductivity-type gate region 15 and the first-conductivity-type source region 3 can be formed synchronously or in steps.

[0074] It should be noted that the doping concentration of the first-conductivity-type base region 13 and the second-conductivity-type ground base region 14 needs to be precisely controlled to ensure that both cannot be completely depleted without gate bias.

[0075] Specifically, the second-conductivity-type ground base region 14 and the first-conductivity-type gate region 15 are electrically connected to the source metal 1 (not shown). The second-conductivity-type ground base region 14 and the first-conductivity-type gate region 15 are connected to the source metal 1 through layout design.

[0076] S5, after the formation of the first-conductivity-type gate region 15:

[0077] As shown in the gate trench, a gate dielectric layer 9 is formed by dry oxygen oxidation on the inner wall of the gate trench, and a polysilicon 8 is deposited in the gate trench, wherein the gate dielectric layer 9 is silicon oxide, and the polysilicon 8 is doped with second-conductivity-type ions. Figure 13

[0078] As shown in the gate trench, a gate dielectric layer 9 is formed by dry oxygen oxidation on the inner wall of the gate trench, and a polysilicon 8 is deposited in the gate trench, wherein the gate dielectric layer 9 is silicon oxide, and the polysilicon 8 is doped with second-conductivity-type ions. Figure 14 ​​​​As shown, metal is deposited on the front side of the second conductivity type substrate 11 to form source metal 1 in ohmic contact with the top of the first conductivity type source region 3 and the second conductivity type source region 4, and gate metal 2 in ohmic contact with the top of the polysilicon 8, and metal is deposited on the back side of the second conductivity type substrate 11 to form drain metal 12, wherein the second conductivity type ground base region 14 and the first conductivity type ground region 15 are electrically connected to the source metal 1.

[0079] In one embodiment, the source contact hole is etched, metal is deposited and alloyed, the gate contact hole is etched, metal is deposited and alloyed, and metal is also deposited on the back side of the second conductivity type substrate 11 and alloyed. In this case, the polysilicon end of the device is the gate, the second conductivity type substrate end is the drain, and the first conductivity type source region 3 and the second conductivity type source region 4 are the source.

[0080] In addition, the first conductivity type ground region 15, the second conductivity type ground base region 14 and the first conductivity type base region 13 can be formed by ion implantation after the gate trench is etched, or can be formed by ion implantation before the CSL layer 6 is epitaxially formed, and the present application is not limited in this regard.

[0081] For example, the second conductivity type source region 4, the first conductivity type source region 3, the first conductivity type well region 5, the CSL layer 6, the first conductivity type mask layer 7, the first conductivity type base region 13, the second conductivity type ground base region 14, the first conductivity type ground region 15, the second conductivity type drift region 10 and the second conductivity type substrate 11 are all made of silicon carbide, and the material of the gate dielectric layer 9 is silicon oxide.

[0082] Here, only the first conductive type is P type and the second conductive type is N type as an example, when the gate bias of the device is greater than zero, with the increase of the gate bias, the first conductive type base region 13 is gradually depleted under the action of the gate bias and the PN junction formed by the second conductive type grounded base region 14 and the first conductive type base region 13. When the gate bias reaches a certain value, the first conductive type base region 13 is completely depleted. At this time, a hole barrier is formed between the first conductive type mask layer 7 and the first conductive type grounded base region, preventing the movement of holes between the two regions. The first conductive type mask layer 7 originally grounded through the first conductive type base region 13 is in a floating state. Under the action of the gradually increasing gate bias and drain-source voltage, the floating first conductive type mask layer 7 potential rises, thereby reducing the JFET resistance value due to the introduction of the first conductive type mask layer 7, and the on-resistance and on-loss of the device are also reduced. When the gate bias of the device is less than a certain gate bias (which can be adjusted by changing the doping concentration of the first conductive type base region 13 and the second conductive type grounded base region 14, and the thickness of the gate dielectric layer 9), the first conductive type base region 13 is not completely depleted, and the first conductive type mask layer 7 is still in a grounded state, thereby avoiding the degradation of the dynamic switching characteristics due to continuous floating. In addition, when the device is short-circuited, the continuously rising temperature increases the intrinsic carrier concentration of the device, so that the first conductive type base region 13, which was originally in a depleted state under the control of the gate bias, is no longer depleted, reducing the height of the hole barrier formed in the first conductive type base region 13, so that the first conductive type mask layer 7 is re-grounded, and the potential of the first conductive type mask layer 7 becomes the ground potential. Thus, the JFET resistance value increases to the original JFET resistance value before the first conductive type mask layer 7 is not floating, and the saturation current of the device decreases. Compared with the conventional device with the same on-resistance, the short-circuit tolerance time of the device is increased, as shown in the forward characteristic and on-state characteristic simulation diagram of the improved structure of the present case and the conventional structure. Figure 3 and Figure 4 the forward characteristic and on-state characteristic simulation diagram of the improved structure of the present case and the conventional structure.

[0083] The above description is only a description of the preferred embodiment of the present application, and is not any limitation on the scope of the present application. Any changes or modifications made by a person skilled in the art based on the above disclosure are within the protection scope of the technical scheme of the present application.

Claims

1. A trench silicon carbide MOSFET device comprising a second conductivity type substrate, a second conductivity type drift region, polysilicon, a gate dielectric layer, a CSL layer, and a first conductivity type mask layer, characterized in that, The first conductive type mask layer is further provided with: A first conductive type ground region is arranged at the bottom of the gate dielectric layer, and the top of the first conductive type ground region is connected with the bottom of the gate dielectric layer; A second conductive type ground base region is arranged at both sides of the first conductive type ground region, and the top of the second conductive type ground base region is connected with the gate dielectric layer; A second conductive type base region is arranged at the bottom of the first conductive type ground region and the second conductive type ground base region.

2. The trench silicon carbide MOSFET device of Claim 1, wherein, The top of the CSL layer is further provided with a first conductive type well region.

3. The trench silicon carbide MOSFET device of Claim 2, wherein, The top of the first conductive type well region is further provided with a first conductive type source region.

4. The trench silicon carbide MOSFET device of Claim 3, wherein, Further comprising a second conductive type source region, one side of the second conductive type source region is connected with the gate dielectric layer, and the other side is connected with the first conductive type source region.

5. The trench silicon carbide MOSFET device of Claim 4, wherein, Further comprising a source metal, the source metal is arranged at the top of the first conductive type source region and the second conductive type source region, and the source metal forms ohmic contact with the first conductive type source region and the second conductive type source region.

6. The trench silicon carbide MOSFET device of Claim 5, wherein, The top of the polysilicon is arranged with a gate metal, and the source metal and the gate metal have a spacing therebetween.

7. The trench silicon carbide MOSFET device of Claim 5, wherein, The second conductive type base region and the first conductive type ground region are electrically connected with the source metal.

8. The trench silicon carbide MOSFET device of Claim 1, wherein, The back of the second conductive type substrate is further provided with a drain metal, and the drain metal forms ohmic contact with the second conductive type substrate.

9. The trench silicon carbide MOSFET device of any one of claims 1-8, wherein, The first conductive type is P type, and the second conductive type is N type.

10. The trench silicon carbide MOSFET device of any of Claims 1-8, wherein, The first conductive type is N type, and the second conductive type is P type.

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