SIC MOSFET device with high freewheeling capability

Abstract

The utility model discloses an SIC MOSFET device with high follow current capability, and relates to the technical field of semiconductors. An SBD structure is arranged in the SiC MOSFET chip and connected with a body diode of the SBD structure in parallel, the embedded SBD diode forms a U-shaped N + region through a groove, the contact area of the N + region and Schottky metal in the vertical direction is increased, the conduction voltage drop of the embedded SBD diode is reduced, the follow current capacity of the SiC MOSFET device is greatly improved, and power loss is reduced. In the blocking state, the deeply injected PP region is beneficial to shielding the embedded SBD region and a high electric field at the bottom of the gate trench, and the reliability of the device can be improved.

Description

TECHNICAL FIELD

[0001] The utility model relates to the technical field of semiconductor, especially to SIC MOSFET device with high freewheeling capability. BACKGROUND

[0002] SiC MOSFET can significantly improve the energy efficiency of the motor by virtue of its performance advantages for more and more industries, such as energy storage, charging piles, photovoltaic inverters, motor drives, industrial control power supplies; in motor control units, SiC MOSFET can improve the energy efficiency of the motor by about 5% compared with traditional silicon-based IGBT modules, which means that electric vehicles can reduce energy consumption by about 5%, thereby improving the range and performance.

[0003] In motor drivers and synchronous rectifiers and other applications, SiC MOSFET usually needs to be anti-parallel with a freewheeling diode for rectification, which not only occupies additional packaging area, but also introduces parasitic inductance, thereby limiting the switching frequency and reducing the power density of the power converter / inverter. Although the body diode of SiC MOSFET can realize rectification function, it may have the risk of bipolar degradation and increase the on-state power consumption. Therefore, how to design a SiC MOSFET device that greatly reduces the chip footprint area, while improving the freewheeling capability of the device and reducing power loss is a technical problem that needs to be solved at present. SUMMARY

[0004] To solve the above problems, the utility model provides a kind of SIC MOSFET device with high freewheeling capability, which reduces diode on-state voltage drop, improves the freewheeling capability of SiC MOSFET device and reduces power loss.

[0005] The technical scheme of the utility model is:

[0006] The preparation method of the SIC MOSFET device with high freewheeling capability comprises the following steps:

[0007] S100, in the heavily doped N + The N-type buffer layer and the N - Drift layer are grown on the substrate layer (1) in sequence.

[0008] S200, the P-well region is formed on the N - Drift layer by ion implantation, and the heavily doped NP region and the heavily doped PP region are formed on the P-well region by ion implantation.

[0009] S300, the first trench region is formed on the NP region by dry etching; the second trench region is formed on the P-well region by dry etching.

[0010] S400, N formed by ion implantation in the P-well region + The area is activated by high-temperature ions after injection.

[0011] S500, in the first trench region, a gate oxide layer is formed by thermal oxidation, and a Poly layer is formed by deposition;

[0012] S600 forms a dielectric layer on the gate oxide layer and the poly layer to isolate the gate electrode and the source electrode metal;

[0013] S700 forms a source ohmic contact alloy layer on the NP and PP regions by metal sputtering.

[0014] S800, in N + Schottky metal is formed on the region, dielectric layer, and source ohmic contact alloy layer by metal sputtering; a source metal layer is sputtered on the Schottky metal to lead out the source electrode;

[0015] S900, in N + Reduce N on the back side of the substrate + The substrate thickness is determined by forming a drain metal layer through metal evaporation, which leads out the drain electrode.

[0016] Specifically, in step S100, N + The substrate is doped with N ions at a concentration of 1e. 19 cm -2 ±10%; The N-type buffer layer is doped with N ions, with a doping concentration of 1e⁻¹. 18 cm -2 ±10%; N - The drift layer is doped with N ions at a concentration of 8e⁻. 15 -2e 16 cm -2 The thickness is 5-20um.

[0017] Specifically, in step S200, the P-well region is doped with Al ions at a concentration of 1e⁻¹. 17 -1e 18 cm -2 The NP region is doped with N ions, and the doping concentration is 1e. 18 -5e 18 cm -2 The PP region is doped with Al ions, and the doping concentration is 5e. 18 -1e 19 cm -2 .

[0018] Specifically, in step S400, N + The region is doped with N ions, with a doping concentration of 5e. 18 -1e 19 cm-2 .

[0019] The SIC MOSFET device with high freewheeling capability comprises, from bottom to top, a drain metal layer, an N + substrate layer, an N - drift layer, a P-well region, an NP region, a source ohmic contact alloy layer, a Schottky metal and a source metal layer.

[0020] The N - drift layer is internally provided with:

[0021] The outer end of the NP region is provided with a PP region extending downward, and the PP region extends downward from the top surface of the P-well region.

[0022] The top surface of the NP region is provided with a first trench region extending downward; the first trench region has a U-shaped structure and is filled in sequence through a gate oxide layer and a Poly layer.

[0023] The outer end of the PP region is provided with an N + region extending downward; the N + region extends downward from the top surface of the P-well region and has a depth greater than that of the second trench region and less than that of the PP region.

[0024] The top surface of the N + region is provided with a second trench region extending downward; the second trench region has a rectangular structure and is filled in sequence through the Schottky metal and the source metal layer.

[0025] The top surface of the NP region is provided with a dielectric layer covering the gate oxide layer and the Poly layer.

[0026] The utility model has the advantages of:

[0027] The utility model improves the freewheeling capability of the SiC MOSFET device, and parallelly connects the SBD structure (formed of the Schottky metal and the N + region) with the body diode, so that the SBD diode in the SiC MOSFET chip utilizes the trench to form the U-shaped N + region, increases the area of the N + region in the vertical direction in contact with the Schottky metal, reduces the on-voltage drop of the embedded SBD diode, greatly improves the freewheeling capability of the SiC MOSFET device, reduces the power loss, and improves the reliability of the device in the blocking state. BRIEF DESCRIPTION OF DRAWINGS

[0028] Figure 1 is the structural schematic diagram of the step S100 of the utility model.

[0029] Figure 2 is the structure schematic diagram of step S200 of the utility model;

[0030] Figure 3 is the structure schematic diagram of step S300 of the utility model;

[0031] Figure 4 is the structure schematic diagram of step S400 of the utility model;

[0032] Figure 5 is the structure schematic diagram of step S500 of the utility model;

[0033] Figure 6 is the structure schematic diagram of step S600 of the utility model;

[0034] Figure 7 is the structure schematic diagram of step S700 of the utility model;

[0035] Figure 8 is the structure schematic diagram of step S800 of the utility model;

[0036] Figure 9 is the structure schematic diagram of step S900 of the utility model;

[0037] Figure 10 is the structure schematic diagram of step S1000 of the utility model;

[0038] Figure 11 is the structure schematic diagram of step S1100 of the utility model;

[0039] Figure 12 is the structure schematic diagram of step S1200 of the utility model;

[0040] Figure 13 is the structure schematic diagram of step S1300 of the utility model;

[0041] Figure 14 is the structure schematic diagram of step S1400 of the utility model;

[0042] Fig. 1 is N + substrate layer, 2 is N-type buffer layer, 3 is N - drift layer, 4 is P-well region, 5 is NP region, 6 is PP region, 7 is first trench region, 8 is second trench region, 9 is N + region, 10 is gate oxide layer, 11 is Poly layer, 12 is dielectric layer, 13 is source ohmic contact alloy layer, 14 is Schottky metal, 15 is source metal layer, 16 is drain metal layer. DETAILED DESCRIPTION

[0043] The utility model will be explained in detail below with specific examples. The examples of the embodiments are shown in the drawings, and the illustrative embodiments of the utility model and their explanations are only for explaining the utility model and not as a limitation of the utility model.

[0044] The preparation method of the SIC MOSFET device with high freewheeling capability comprises the following steps:

[0045] S100, refer to Figure 1 Fig. 1, a heavily doped N + substrate layer 1 is grown with an N-type buffer layer 2.

[0046] The N + substrate layer 1 of step S100 is doped with N ions, with a thickness of 360-400um and a doping concentration of 1e 19 cm -2 ±10%, and the N-type buffer layer 2 is also doped with N ions, with a thickness of 0.8-1.2um and a doping concentration of 1e 18 cm -2 ±10%.

[0047] S200, refer to Figure 2 Fig. 2, a layer of primary N - drift layer 3 is epitaxially grown on the N-type buffer layer 2.

[0048] The primary N - drift layer 3 of step S200 is doped with N ions, with a doping concentration of 8e 15 -2e 16 cm -2 and a thickness of 5-20um.

[0049] S300, refer to Figure 3 Fig. 3, a P-well region 4 is formed on the N - drift layer 3 through ion implantation.

[0050] The P-well region 4 in step S300 is doped with Al ions, with a doping concentration of 1e 17 -1e 18 cm -2 .

[0051] S400, refer to Figure 4 Fig. 4, a heavily doped NP region 5 is formed on the P-well region 4 through ion implantation.

[0052] The NP region 5 in step S400 is doped with N ions, with a thickness of 0.2-0.5um and a doping concentration of 1e 18 -5e 18 cm -2 .

[0053] S500, refer to Figure 5 As shown in the figure, in the P-well region 4, the side of the NP region 5 is formed into a heavily doped PP region 6 by ion implantation;

[0054] In step S500, the PP region 6 is doped with Al ions, and the doping concentration is 5e 18 -1e 19 cm -2 , and the implantation depth is 1.2-1.5um.

[0055] S600, refer to Figure 6 As shown in the figure, a first trench region 7 extending to the P-well region 4 below is formed on the surface of the NP region 5 by dry etching;

[0056] S700, refer to Figure 7 As shown in the figure, a second trench region 8 extending below is formed on the surface of the P-well region 4 by dry etching;

[0057] In step S700, the etching depth of the second trench region 8 is greater than the depth of the P-well region 4, and can be inconsistent with the depth of the first trench region 7.

[0058] S800, refer to Figure 8 As shown in the figure, an N + region 9 is formed in the second trench region 8 by ion implantation, and after the implantation is completed, high-temperature ion activation is performed;

[0059] In step S800, the N + region 9 is doped with N ions, and the doping concentration is 5e 18 -1e 19 cm -2 , and the doping depth is less than the depth of the PP region 6.

[0060] S900, refer to Figure 9 As shown in the figure, a gate oxide layer 10 is formed in the first trench region 7 by dry oxygen thermal oxidation process, and a channel is formed at the interface with the P-Well region 4;

[0061] In step S900, the growth temperature of the gate oxide layer 10 is 1250-1350℃, the growth thickness is 40-60nm, and annealing treatment needs to be performed in a NO atmosphere, the annealing temperature is 1250℃, and the time is 1H, so as to improve the density of the gate oxide layer 10 and reduce defects.

[0062] S1000, refer to Figure 10 As shown in the figure, a Poly layer 11 is deposited on the gate oxide layer 10 to form a gate electrode;

[0063] S1100, refer to Figure 11The oxide is deposited on the top of the Poly layer 11 to form the dielectric layer 12, which separates the gate electrode and the source electrode metal;

[0064] S1200, referring to Figure 12 The source ohmic contact alloy layer 13 is formed by sputtering Ni metal on the top of the NP region 5 and the PP region 6.

[0065] The annealing temperature of the source ohmic contact alloy layer 13 in step S1200 is 1000℃, and the annealing time is 5min, so as to form the alloy and achieve the ohmic contact effect.

[0066] S1300, referring to Figure 13 The source ohmic contact alloy layer 13, the dielectric layer 12, the N + The Schottky metal 14 and the source metal layer 15 are formed by sputtering Ti / AlCu metal on the top of the N

[0067] S1400, referring to Figure 14 The Schottky metal 14 and the source metal layer 15 are formed by sputtering Ti / AlCu metal on the top of the N + The thickness of the N + The drain metal layer 16 is formed by sputtering Ni metal and then evaporating Ti / Ni / Ag metal on the back of the substrate layer 1 through a thinning process.

[0068] The drain metal layer 16 in step S1400 needs to be laser annealed after sputtering Ni metal, and the laser energy is 2-4mJ / cm 2 Then, the Ti / Ni / Ag multi-layer metal or other metal is evaporated, and the total thickness is 1.4-2um.

[0069] The SIC MOSFET device with high current continuation capability comprises, from bottom to top, a drain metal layer 16, a substrate layer 1, an N + type buffer layer 2, an N - type drift layer 3, a source ohmic contact alloy layer 13, a Schottky metal 14, and a source metal layer 15.

[0070] The N - type drift layer 3 is provided with:

[0071] A P-well region 4 extends downward from the top surface of the N - type drift layer 3;

[0072] NP regions 5 are provided, each extending downward from the top surface of the P-well region 4 and having a spacing from the bottom surface of the P-well region 4;

[0073] PP region 6, provided with several, respectively from the top surface of the P-well region 4 downwardly extending and located at the side of the NP region 5, the PP region 6 downwardly extending to the lower of the P-well region 4;

[0074] N + Region 9, the cross section is U-shaped structure, from the top surface of the NP region (5) downwardly extending and located between the middle pair of the PP region 6, the bottom surface of the region 9 is located between the bottom surface of the P-well region 4 and the bottom surface of the PP region 6; + Region 9, the cross section is U-shaped structure, from the top surface of the NP region (5) downwardly extending and located between the middle pair of the PP region 6, the bottom surface of the region 9 is located between the bottom surface of the P-well region 4 and the bottom surface of the PP region 6;

[0075] Gate oxide layer 10, provided with several, the cross section is U-shaped structure, respectively from the top surface of the NP region 5 downwardly extending to the lower of the P-well region 4, the bottom surface of the gate oxide layer 10 is located between the bottom surface of the P-well region 4 and the bottom surface of the PP region 6;

[0076] Poly layer 11, disposed in the gate oxide layer 10;

[0077] The top surface of the NP region 5 is provided with several medium layers 12 connected with the gate oxide layer 10 and the Poly layer 11 respectively.

[0078] The source ohmic contact alloy layer 13 is provided with several, respectively located at the side of the medium layer 12, the bottom surface of the source ohmic contact alloy layer 13 is connected with the NP region 5 and the PP region 6 respectively.

[0079] The bottom surface of the Schottky metal 14 is connected with the source ohmic contact alloy layer 13, the medium layer 12 and the N + Region 9 respectively.

[0080] The bottom surface of the source metal layer 15 covers the Schottky metal 14 and fills the middle recess in the N + Region 9.

[0081] The utility model improves the freewheeling capability of SiC MOSFET device, sets up SBD structure (comprises Schottky metal 14 and N + Region 9) and parallelly connected with the body diode in the SiC MOSFET chip, the embedded SBD diode utilizes the groove to form U-shaped N + Region increases the area of N + Region and Schottky metal contact in the vertical direction, reduces the on-voltage drop of embedded SBD diode, greatly improves the freewheeling capability of SiC MOSFET device, reduces power loss.Under the blocking state, the deep injection PP region 6 is favorable for shielding the high electric field of embedded SBD area and gate groove bottom, can improve the reliability of device.

Claims

1. A SiC MOSFET device with high freewheeling capability, characterized in that, Including a drain metal layer (16) arranged sequentially from bottom to top, N + Substrate (1), N-type buffer layer (2), N - Drift layer (3), source ohmic contact alloy layer (13), Schottky metal (14) and source metal layer (15); The N - The drift layer (3) is provided with: P-well region (4), from the N - The top surface of the drift layer (3) extends downwards; The NP region (5) is provided with several of them, which extend downward from the top surface of the P-well region (4); PP region (6) is provided in several parts, which extend downward from the top surface of P-well region (4) and are located on the side of NP region (5); N + The region (9) has a U-shaped cross-section, extends downward from the top surface of the NP region (5), and is located between the two PP regions (6) in the middle. The gate oxide layer (10) is provided in several forms, each with a U-shaped cross-section, extending downward from the top surface of the NP region (5) to the bottom of the P-well region (4); A poly layer (11) is disposed within the gate oxide layer (10); The top surface of the NP region (5) is provided with several dielectric layers (12) that are respectively connected to the gate oxide layer (10) and the Poly layer (11).

2. The SiC MOSFET device with high freewheeling capability according to claim 1, characterized in that, The thickness of the N+ substrate layer (1) is 360-400um.

3. The SiC MOSFET device with high freewheeling capability according to claim 1, characterized in that, The thickness of the NP region (5) is 0.2-0.5 μm.

4. The SiC MOSFET device with high freewheeling capability according to claim 1, characterized in that, The injection depth of the PP region (6) is 1.2-1.5 μm.

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