Multistage junction termination structure of vertical GaN diode

Abstract

The utility model belongs to the field of semiconductors, and discloses a multistage junction termination structure of a vertical GaN diode. The multistage junction termination structure comprises a sapphire substrate on which a GaN nodule layer grows; a silicon-doped n +-GaN layer is grown on the GaN nodule layer, a silicon-doped n-GaN layer is grown on the n +-GaN layer, a magnesium-doped p-GaN layer is grown on the n-GaN layer, and a magnesium-doped p +-GaN layer is grown on the p-GaN layer; etching from the p < + >-GaN layer to the n < + >-GaN layer, and preparing a negative electrode on the surface of the n < + >-GaN layer; etching from the p +-GaN layer to the p-GaN layer to form a continuous multi-stage step, and preparing a positive electrode on the surface of the p +-GaN layer; according to the utility model, after the multi-stage step junction termination structure is introduced, the electric field aggregation phenomenon is obviously relieved, which indicates that the junction termination structure effectively reduces the internal electric field peak value.

Description

TECHNICAL FIELD

[0001] The utility model relates to the field of semiconductor, in particular to a multistage junction terminal structure of vertical GaN diode. BACKGROUND

[0002] At present, the main problem of GaN-based diode's withstand voltage is the electric field concentration effect at the junction edge, which limits the improvement of GaN-based diode's breakdown voltage. Designing an efficient junction terminal is the main method to deal with the electric field concentration effect.

[0003] For traditional silicon-based diodes, the method to realize the junction terminal is usually to implant ions at the main junction edge through ion implantation technology, thereby forming a junction terminal region. However, in the process of high-energy ion implantation, it is easy to cause crystal damage, and the dose and the length and depth of diffusion are difficult to accurately control. Therefore, it is difficult to accurately control the dose, and too high or too low dose may result in unsatisfactory doping effect. GaN material has a small diffusion coefficient, making it difficult for the implanted dopant to diffuse in the crystal. These make it very difficult to implant ions in the thin layer of P-type GaN. On the other hand, the junction terminal realized by ion implantation technology usually uses a relatively thick p-GaN thickness (generally in the range of 300-500 nm), which limits the on-resistance of the vertical GaN diode to some extent.

[0004] For GaN material, the way to form p-type GaN needs to dope Mg in GaN, which is a reaction that occurs in vapor deposition, not through ion implantation. Moreover, the acceptor level of Mg in GaN is deep, and its activation rate is low. Therefore, the method of realizing the junction terminal through ion implantation is not practical for GaN-based devices.

[0005] Therefore, it is of great significance to develop a new process that can avoid ion implantation and realize an efficient junction terminal structure on a thin layer of P-type GaN with a relatively economical and simple process step. SUMMARY

[0006] In view of the above-mentioned defects of the prior art, the purpose of the utility model is to develop a relatively economical and simple process step to realize an efficient junction terminal structure on a thin layer of P-type GaN and its preparation method, in order to improve the breakdown voltage of the vertical GaN diode.

[0007] The utility model provides a kind of multistage junction terminal structure of vertical GaN diode, comprising: sapphire substrate, GaN nucleus layer is grown on the sapphire substrate;Silicon-doped n+-GaN layer is grown on the GaN nucleus layer, silicon-doped n-GaN layer is grown on the n+-GaN layer, magnesium-doped p-GaN layer is grown on n-GaN layer, magnesium-doped p+-GaN layer is grown on p-GaN layer;From p+-GaN layer etching to n+-GaN layer, and anode is prepared on the n+-GaN layer surface;From p+-GaN layer etching to p-GaN layer, form continuous multistage step, and cathode is prepared on the p+-GaN layer surface.

[0008] Further, the size of the multistage step is obtained by fitting an elliptical boundary, and the area of the rectangular region formed by the multistage step is equal to the integral area of the corresponding elliptical boundary.

[0009] Further, the setting mode of the width of the multistage step includes setting a higher step height near the edge of the step and setting a lower step height near the center of the step.

[0010] Further, the setting mode of the width of the multistage step includes setting a wider step width near the edge of the step and setting a narrower step width near the center of the step.

[0011] Further, the height of the multistage step and the width of the multistage step satisfy the following formula:

[0012]

[0013] wherein L represents the total length of the junction terminal, x represents the step width, y represents the step height, T n represents the total height of the junction terminal.

[0014] The beneficial effects of the utility model include:

[0015] Compared with traditional silicon-based semiconductor power devices, the vertical GaN power diode of the utility model can achieve higher breakdown voltage under the same drift layer thickness due to the high critical breakdown field and high electron mobility of its material itself, and it can achieve lower switching loss and on-resistance under the same current and voltage conditions. These characteristics provide great potential and opportunities for further development in the field of power semiconductors. The utility model proposes a new multistage junction terminal and its preparation method, which can further improve the breakdown voltage of the device. After introducing the multistage step junction terminal structure, the electric field concentration phenomenon is obviously relieved, which indicates that the junction terminal structure effectively reduces the internal electric field peak. BRIEF DESCRIPTION OF DRAWINGS

[0016] Figure 1 is a multi-stage junction termination structure schematic diagram of a vertical GaN diode in the embodiment of the utility model;

[0017] Figure 2 is a multi-stage junction termination structure schematic diagram of a vertical GaN diode in the preferred embodiment of the utility model;

[0018] Figure 3 is a potential line distribution schematic diagram of a junction termination extension area in the embodiment of the utility model;

[0019] Figure 4 is a schematic diagram of a multi-stage junction termination structure in the embodiment of the utility model;

[0020] Figure 5 is a highest and average breakdown voltage simulation diagram of the embodiment of the utility model compared with prior art;

[0021] Figure 6 is an electric field simulation diagram under reverse bias of the embodiment of the utility model compared with prior art. DETAILED DESCRIPTION

[0022] The utility model will be further described below in combination with the drawings and embodiments, and it should be noted that in the description of the utility model, the terms "upper", "lower", "left", "right", "inner", "outer" and the like indicate the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the utility model and simplifying the description, and cannot be understood as indicating or implying that the devices or elements must have a particular orientation, be constructed and operated in a particular way, and therefore cannot be understood as limiting the utility model. The terms "first", "second", "third" and the like are only for the purpose of description, and cannot be understood as indicating or implying relative importance.

[0023] In some embodiments of the utility model, as shown in Figure 1 A multi-stage junction termination structure of a vertical GaN diode includes: a sapphire substrate, a GaN nuclear layer is grown on the sapphire substrate; a silicon-doped n+-GaN layer is grown on the GaN nuclear layer, a silicon-doped n-GaN layer is grown on the n+-GaN layer, a magnesium-doped p-GaN layer is grown on the n-GaN layer, and a magnesium-doped p+-GaN layer is grown on the p-GaN layer.

[0024] The GaN nuclear layer (nuclear layer) is also called a nucleation layer or an initial growth layer, which is a very thin GaN layer grown on a substrate (such as sapphire, SiC, etc.) first in the GaN epitaxial growth process. This thin film is crucial for the growth of subsequent high-quality GaN epitaxial layers.

[0025] For example, the epitaxial layer is grown by metal-organic chemical vapor deposition (MOCVD) and includes a 20 nm thick p-layer. + -GaN (magnesium doping concentration of 10) 20 cm -3 A 100nm thick layer of p-GaN (with a magnesium doping concentration of 10) 19 cm -3 A layer of n-GaN with a thickness of 5 μm (silicon doping concentration of 1-3 × 10⁻⁶) 16 cm -3 ) and a layer of n with a thickness of 1.5μm + -GaN (silicon doping concentration of 10) 18 cm -3 They are all grown on sapphire substrates.

[0026] In the preferred embodiment of this utility model, such as Figure 2 As shown, a multi-level junction termination structure for a vertical GaN diode includes: a sapphire substrate, on which a GaN junction core layer is grown; a silicon-doped n+-GaN layer is grown on the GaN junction core layer, a silicon-doped n-GaN layer is grown on the n+-GaN layer, a magnesium-doped p-GaN layer is grown on the n-GaN layer, and a magnesium-doped p+-GaN layer is grown on the p-GaN layer; an electrode is formed by etching from the p+-GaN layer to the n+-GaN layer; and a cathode is formed on the surface of the n+-GaN layer. An electrode is also formed by etching from the p+-GaN layer to the p-GaN layer, forming a continuous multi-level step structure, and a cathode is formed on the surface of the p+-GaN layer. This embodiment of the invention uses a GaN diode with a multi-level step termination structure designed with elliptical boundary fitting. The following description uses this structure as an example to detail various implementation methods.

[0027] In this embodiment of the utility model, the design principle of the multi-level terminal is as follows: Figure 3 The calculations are shown below. For junction termination design, two principles are often followed: first, the amount of charge introduced along the junction termination direction gradually decreases; second, the depletion region of the device under reverse bias is expanded as much as possible, making the internal electric field of the device relatively uniform. Therefore, the size of the multi-level steps is obtained by fitting an elliptical boundary, resulting in a rectangular region area including the multi-level steps whose integral area is equal to the corresponding elliptical boundary area. The width of the multi-level steps is set by setting a higher step height near the step edge and a lower step height near the step center. The width of the multi-level steps is set by setting a wider step width near the step edge and a narrower step width near the step center. Under this design, the height and width of the multi-level steps satisfy the following formula:

[0028]

[0029] Wherein, L represents the total length of the junction terminal, x represents the step width, y represents the step height, T n represents the total height of the junction terminal, and the height of the junction terminal herein does not include the positive electrode thickness.

[0030] It can be understood that in actual application, the number of the multi-stage steps is limited, and the actual step height and step width can meet the above formula within a certain error range.

[0031] On the basis of the above embodiment, as Figure 3 shown, the utility model assumes that the potential line of the depletion region edge in the junction terminal expansion area is elliptical distribution, so that the distribution of the carrier in the p-GaN can be calculated according to the charge conservation:

[0032]

[0033] Wherein, ρ (x) represents the charge density distribution of the p-GaN along the x direction, N * A represents the concentration of the acceptor after activation in the p-GaN, Tp-GaN represents the thickness of the p-GaN, and L represents the total length of the junction terminal.

[0034] The utility model embodiment adopts a plurality of rectangular step area junction terminals to fit the elliptical curve, divides the junction terminal expansion structure into a plurality of areas, and makes it approximate to the effect of the elliptical boundary. Since the electric field is more concentrated in the place closer to the edge, this indicates that the potential change at the boundary will be more severe, and from the perspective of mathematical fitting accuracy, at the edge potential severe change, as small rectangular as possible should be used for fitting.

[0035] It should be noted that due to the existence of the edge field concentration effect, the electric field peak value will appear at the edge position, which means that the potential change is most severe at the edge. The utility model embodiment adopts an elliptical terminal to disperse the electric field, and due to the limited number of steps in actual design, only the elliptical shape can be fitted as much as possible. Therefore, at the edge position, the utility model embodiment sets a more intensive step width distribution, taking four steps as an example, from inside to outside, the width ratio of the steps is 9:7:5:3. In order to ensure that the charge amount in each step is similar to the charge amount of the elliptical distribution, the utility model designs each step in its interval to meet the condition that the area of the rectangle is equal to the integral of the elliptical boundary in the interval.

[0036] As Figure 4As shown, the width of the step junction terminal designed in the utility model accords with the principle that the closer to the boundary, the smaller, guarantees to fit with smaller rectangular junction terminal at the boundary as far as possible, since the number of steps is less, in order to guarantee that the charge quantity is similar to the charge quantity deduced, the utility model designs each step in its interval, satisfies the area of rectangle equal to the integral of elliptical boundary in the interval. Figure 4 As shown, also taking four steps as an example, the width and height of each junction terminal can be obtained.

[0037] Table 1 Height and length of JTE

[0038] JTE height and width (nm) JTE1 0.33×120 JTE2 0.61×120 JTE3 0.79×120 JTE4 0.93×120

[0039] In the utility model embodiment, a preparation method of a multistage junction terminal structure of a vertical GaN diode comprises:

[0040] Growth of a GaN junction nucleus layer on a sapphire substrate;

[0041] Growth of a silicon-doped n+-GaN layer on the GaN junction nucleus layer;

[0042] Growth of a silicon-doped n-GaN layer on the n+-GaN layer;

[0043] Growth of a magnesium-doped p-GaN layer on the n-GaN layer;

[0044] Growth of a magnesium-doped p+-GaN layer on the p-GaN layer;

[0045] Etching from the p+-GaN layer to the n+-GaN layer;

[0046] Etching from the p+-GaN layer to the p-GaN layer to form a continuous multistage step;

[0047] Preparation of a positive electrode on the surface of the p+-GaN layer and preparation of a negative electrode on the surface of the n+-GaN layer;

[0048] The size of the multistage step is obtained by fitting an elliptical boundary.

[0049] In the utility model embodiment, the etching from the p+-GaN layer to the n+-GaN layer comprises:

[0050] Deposition of a silicon dioxide mask on the surface of the p+-GaN layer;

[0051] Use of a photolithography technology to transfer the required mesa pattern to the mask and retain the part not covered by the mask;

[0052] Etching from the p+-GaN layer to the n+-GaN layer by chemical etching or physical etching, removing the hierarchical structure not protected by the mask, and forming the required mesa structure;

[0053] The silicon dioxide mask is removed using an acidic solution.

[0054] In the embodiment of the utility model, the etching from the p+-GaN layer to the p-GaN layer forms continuous multistage steps, and the steps include:

[0055] The silicon dioxide mask is deposited on the surface of the p+-GaN layer;

[0056] The required mesa pattern is transferred to the mask using photolithography technology, the silicon dioxide mask is etched, and the p-GaN region required to be exposed is exposed;

[0057] The p-GaN is etched from the p+-GaN layer to the p-GaN layer by using the physical etching ICP mode;

[0058] In the process of forming each step, the photolithography and ICP etching operations are repeated, and finally the hierarchical structure not protected by the mask is removed; the required mesa structure is formed; wherein the size of the multistage steps is obtained by elliptical boundary fitting;

[0059] The silicon dioxide mask is removed using an acidic solution.

[0060] In the embodiment of the utility model, the positive electrode is prepared on the surface of the p+-GaN layer, and the negative electrode is prepared on the surface of the n+-GaN layer, and the steps include:

[0061] The Ni / Au metal is deposited on the surface of the p+-GaN layer, and after the deposition is completed, rapid thermal annealing is carried out;

[0062] The ohmic contact Ti / Al / Ti / Au metal is formed on the surface of the n+-GaN layer.

[0063] In the embodiment of the utility model, the size of the multistage steps is obtained by elliptical boundary fitting, and the steps include:

[0064] The multistage junction terminal expansion structure is divided into a plurality of rectangular regions;

[0065] The plurality of rectangular regions are fitted by an elliptical boundary, and the size of each junction terminal is calculated.

[0066] The following will be described in detail:

[0067] Firstly, the utility model needs to carry out Mesa etching to the device, and the utility model embodiment Mesa etching adopts silicon dioxide (SiO2). Next, by chemical etching or physical etching etc. Method, remove the area exposed to the outside, form the step structure or platform structure. After that, remove silicon dioxide by dry etching method, then clean photoresist and prepare to etch GaN under it.

[0068] Wherein, Mesa etching (Mesa Etching) is a kind of process technology for creating specific geometric shape on the surface of semiconductor material. This process usually involves forming a convex area on the surface of semiconductor material, and this convex area is called "mesa" (Mesa). Mesa etching is commonly used to manufacture semiconductor devices, such as laser diodes, solar cells, high-frequency transistors, etc., and is also used in micro-electro-mechanical systems (MEMS) and nanotechnology fields.

[0069] The basic steps of Mesa etching are as follows: depositing mask material: first deposit a layer of resist or other mask material on the surface of semiconductor material. Patterning mask: use photolithography or other methods to transfer the desired pattern to the mask, leaving the part not covered by the mask. Etching: use chemical etching (wet etching) or plasma etching (dry etching) to remove the semiconductor material not protected by the mask, forming the desired mesa structure. Remove mask: after completing etching, remove the mask material.

[0070] Unlike vertical structure GaN epitaxial structure, the utility model chooses GaN epitaxial wafer of sapphire substrate, and sapphire does not have conductive properties, so the electrode needs to be deposited on the side of the device. Therefore, Mesa etching needs to etch at least n + GaN layer, the etching depth of the embodiment is about 6 μm. After completing Mesa etching, immerse in BOE (HF: HCl = 1:6) solution to remove SiO2 mask. Then, four-step etching process is carried out on p-GaN to realize the design of multi-stage step terminal, and the sequence is from outside to inside, and SiO2 is still selected as mask. Taking the height and length parameters of each JTE in table 1 as an example, the etching time of each JTE is shown in table 2.

[0071] Table 2 Etching time of JTE

[0072] Etch time (s) JTE1 100.8 JTE2 64.8 JTE3 50.4 JTE4 25.2

[0073] In order to minimize the etching damage and achieve precise control, the utility model needs low power ICP slow etching, by reducing the power of ICP, realized the slow ICP etching of 0.33nm / s etching rate. After etching, the SiO2 mask is washed away with BOE. The step after the multi-stage step terminal etching is completed is electrode preparation, and the technology adopted is electron beam evaporation. Since P-type GaN ohmic contact needs high temperature annealing and N-type GaN ohmic contact does not need, the utility model needs to prepare the positive electrode first. The positive electrode of the utility model process adopts Ni / Au, and the thickness is 25 / 50nm. After deposition, rapid thermal annealing (RTP, Rapid thermal annealing) is carried out, and the annealing condition is 600 DEG C temperature in air atmosphere, and annealing is carried out for 200s. Then, the negative electrode ohmic contact is made, and the negative electrode ohmic contact adopts Ti / Al / Ti / Au, and the thickness is 20 / 150 / 50 / 50nm. Thus, the GaN diode device with multi-stage step terminal can be prepared.

[0074] In order to verify the effectiveness of the multi-stage step terminal structure (sample C) proposed by the utility model on the modulation electric field, the utility model prepares two kinds of comparative diodes on the same epitaxial structure: one without junction terminal (sample A), and the other with uniform multi-stage step junction terminal (sample B, same as the simulation model in the third chapter). Figure 5 (a) and (b) compare the highest and average breakdown voltage of the three kinds of devices respectively. Ten times of breakdown voltage tests are carried out for each type of device, and the average value is calculated. The error line represents the range of these breakdown voltage tests. The results show that the average breakdown voltage of the diode with JTE proposed by the utility model is 1280V, wherein Figure 5 1.32kV in (a) is the highest breakdown voltage data in the test, which is higher than the breakdown voltage of the diode without JTE and with uniform JTE.

[0075] The utility model simulates and analyzes the electric field of the three kinds of devices under reverse bias (Silvaco TCAD). When there is no junction terminal structure in the diode, the edge field aggregation phenomenon will cause the electric field intensity at the edge to be higher than that in the internal region of the device, which is called electric field aggregation effect. By observing Figure 6 (a), the utility model can obviously see this effect. However, after introducing the multi-stage step junction terminal structure, as shown in Figure 6 (b) and (c), the electric field aggregation phenomenon is obviously relieved, which shows that the junction terminal structure effectively reduces the internal electric field peak value. Specifically, the electric field peak value of the diode with the multi-stage step terminal structure adopting elliptical boundary fitting is significantly reduced compared with the diode with uniform multi-stage step terminal.

[0076] In conclusion, the diode with the junction termination structure can significantly improve the breakdown voltage of the GaN diode.

[0077] It can be understood that the multi-stage junction termination structure and the preparation method of the vertical GaN diode in the utility model belong to the same utility model concept, and the corresponding features can be mutually quoted, and the utility model does not make specific limitations on this.

[0078] The preferred embodiments of the utility model are described in detail above. It should be understood that those skilled in the art can make many modifications and changes without creative labor according to the concept of the utility model. Therefore, any technical scheme obtained by logical analysis, reasoning or limited experiment on the basis of the prior art according to the concept of the utility model should be within the protection scope determined by the claims.

Claims

1. A multi-stage junction termination structure for a vertical GaN diode, characterized in that, include: A sapphire substrate on which a GaN nucleus layer is grown; a silicon-doped n+-GaN layer is grown on the GaN nucleus layer; a silicon-doped n-GaN layer is grown on the n+-GaN layer; a magnesium-doped p-GaN layer is grown on the n-GaN layer; and a magnesium-doped p+-GaN layer is grown on the p-GaN layer. The p+-GaN layer is etched down to the n+-GaN layer, and a negative electrode is formed on the surface of the n+-GaN layer. The p+-GaN layer is etched down to the p-GaN layer, forming a continuous multi-level step, and a positive electrode is formed on the surface of the p+-GaN layer.

2. The multi-stage junction termination structure of a vertical GaN diode according to claim 1, characterized in that, The dimensions of the multi-level steps are obtained by fitting an elliptical boundary, and the area of ​​the rectangular region formed by the multi-level steps is equal to the integral area of ​​the corresponding elliptical boundary.

3. The multi-stage junction termination structure of a vertical GaN diode according to claim 2, characterized in that, The width of the multi-level steps can be set by setting a higher step height near the edge of the step and a lower step height near the center of the step.

4. The multi-stage junction termination structure of a vertical GaN diode according to claim 2, characterized in that, The method for setting the width of the multi-level steps includes setting a wider step width near the edge of the step and a narrower step width near the center of the step.

5. A multi-stage junction termination structure for a vertical GaN diode according to claim 3 or 4, characterized in that, The height and width of the multi-level steps satisfy the following formula: Where L represents the total length of the junction terminal, x represents the step width, y represents the step height, and T... n This indicates the total height of the terminal.

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