Waveform generator and test equipment
By pre-setting pulse signal generation structures at different frequencies, the problems of resource waste and high cost of existing waveform generators are solved, and a low-cost and efficient testing solution is achieved.
Patent Information
- Application Number
- CN202520328043.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-02-27
- Publication Date
- 2025-11-28
- Estimated Expiration
- 2035-02-27
AI Technical Summary
While existing arbitrary waveform generators can generate pulse signals of various frequencies, only a few specific frequencies are needed in transceiver module testing, resulting in wasted resources and high costs.
Design a waveform generator that pre-sets a preset number of pulse signal generation structures of different frequencies for testing, and controls the pulse generation module to output pulse signals of specific frequencies through a processing module, thereby reducing resource waste and cost.
This reduces the cost of testing transceiver modules, avoids resource waste, and improves driving capabilities.
Smart Images
Figure CN223611598U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] Embodiments of the present application relate to the field of testing, and particularly to a waveform generator and testing equipment. BACKGROUND
[0002] The transceiver module is a module for receiving and transmitting signals, and often works in a pulse transceiving state. In order to ensure the performance of the transceiver module, the transceiver module needs to be tested. The test often needs to use a pulse signal of a specified frequency for testing. In the existing scheme, an arbitrary waveform generator is used for testing. A tester operates the arbitrary waveform generator so that the arbitrary waveform generator can output the required pulse signal to complete the test.
[0003] However, in the existing scheme, although the arbitrary waveform generator can generate many pulse signals of different frequencies, the actual test of the transceiver module often only needs to use a few pulse signals of specific frequencies, which causes waste of resources of the arbitrary waveform generator, and the cost of the arbitrary waveform generator is relatively high, which brings unnecessary expenses. CONTENT OF THE UTILITY MODEL
[0004] Embodiments of the present application provide a waveform generator and testing equipment for reducing the cost of testing a transceiver module.
[0005] The first aspect of the embodiments of the present application provides a waveform generator, comprising: a processing module and a pulse generation module;
[0006] An input end of the pulse generation module is connected with the processing module, and an output end of the pulse generation module is a port for outputting a pulse signal. The pulse generation module is configured to output one of a plurality of pulse signals of different frequencies.
[0007] The processing module is configured to control the pulse generation module to output a pulse signal of a specific frequency corresponding to a test instruction for a transceiver module to be tested according to the test instruction.
[0008] Optionally, the pulse generation module comprises a generation unit and a plurality of frequency units.
[0009] The generation unit is connected with each of the frequency units, and the processing module is connected with the generation unit and the plurality of frequency units. An output end of the generation unit is the output end of the pulse generation module. Each of the frequency units cooperates with the generation unit to generate a pulse signal of a corresponding frequency. The frequencies corresponding to each of the frequency units are different.
[0010] Optionally, the frequency unit comprises a first chip, a first resistor, a second resistor, and a first capacitor.
[0011] One end of the first resistor is connected with a power supply, one end of the second resistor, one end of the first capacitor and a power supply end of the first chip respectively, the other end of the first resistor is connected with the generating unit and a clock end of the first chip respectively, the other end of the second resistor is connected with the processing module and a transmission end of the first chip respectively, the other end of the first capacitor and a ground end of the first chip are grounded, and the in-phase pulse end and the anti-phase pulse end of the first chip are connected to the generating unit.
[0012] Optionally, if the number of the frequency units is four, the generating unit comprises a second chip, a third chip, a third resistor, a fourth resistor, a fifth resistor and a sixth resistor.
[0013] The first input end, the second input end, the third input end and the fourth input end of the second chip are connected with one of the frequency units respectively, the frequency units connected with the first input end, the second input end, the third input end and the fourth input end of the second chip are different from each other, one end of the third resistor is connected with the first input end of the second chip, one end of the fourth resistor is connected with the second input end of the second chip, one end of the fifth resistor is connected with the third input end of the second chip, one end of the sixth resistor is connected with the fourth input end of the second chip, the other end of the third resistor, the other end of the fourth resistor, the other end of the fifth resistor and the other end of the sixth resistor are connected with a power supply, the common input end of the second chip is connected with the processing module, the inhibit output end, the negative power supply end and the common ground end of the second chip are grounded, and the first control end and the second control end of the second chip are connected with the processing module.
[0014] The first input end, the second input end, the third input end and the fourth input end of the third chip are connected with one of the frequency units respectively, the frequency units connected with the first input end, the second input end, the third input end and the fourth input end of the third chip are different from each other, the fifth input end, the sixth input end, the seventh input end and the eighth input end of the third chip are connected with one of the frequency units respectively, the frequency units connected with the fifth input end, the sixth input end, the seventh input end and the eighth input end of the third chip are different from each other, the first output end of the third chip is used for connecting one end of the first input end, the second input end, the third input end and the fourth input end of the third chip, the second output end of the third chip is used for connecting one end of the fifth input end, the sixth input end, the seventh input end and the eighth input end of the third chip, the inhibit output end, the negative power supply end and the common ground end of the third chip are grounded, and the first control end and the second control end of the third chip are connected with the processing module.
[0015] Optionally, the waveform generator further comprises a power module and a level conversion module.
[0016] An output end of the pulse generation module is connected to the level conversion module, an output end of the level conversion module serves as an output end of the waveform generator, the power module is connected to the processing module and the level conversion module respectively, the power module is configured to provide a voltage signal to the level conversion module, and the level conversion module is configured to convert and output a pulse signal of a specific frequency provided by the pulse generation module according to the voltage signal.
[0017] Optionally, the level conversion module comprises a fourth chip, a fifth chip, a seventh resistor, an eighth resistor, a second capacitor, a third capacitor, a fourth capacitor and a fifth capacitor.
[0018] A first power end of the fourth chip is connected to the power module and one end of the second capacitor respectively, the other end of the second capacitor and a ground end of the fourth chip are both grounded, the first power end of the fourth chip has the same level as a first signal end of the fourth chip, a second power end of the fourth chip is connected to the power supply and one end of the third capacitor respectively, the other end of the third capacitor and one end of the seventh resistor are both grounded, the other end of the seventh resistor is connected to an input-output direction end of the fourth chip, the second power end of the fourth chip has the same level as a second signal end of the fourth chip, the first signal end of the fourth chip serves as the output end of the waveform generator, and the second signal end of the fourth chip is connected to the output end of the pulse generation module.
[0019] A first power end of the fifth chip is connected to the power module and one end of the fourth capacitor respectively, the other end of the fourth capacitor and a ground end of the fifth chip are both grounded, the first power end of the fifth chip has the same level as a first signal end of the fifth chip, a second power end of the fifth chip is connected to the power supply and one end of the fifth capacitor respectively, the other end of the fifth capacitor and one end of the eighth resistor are both grounded, the other end of the eighth resistor is connected to an input-output direction end of the fifth chip, the second power end of the fifth chip has the same level as a second signal end of the fifth chip, the first signal end of the fifth chip serves as the output end of the waveform generator, and the second signal end of the fifth chip is connected to the output end of the pulse generation module.
[0020] Optionally, the waveform generator further comprises a level selection module.
[0021] The power module is connected to the level conversion module through the level selection module, the processing module is connected to the level selection module, and the level selection module is configured to output a corresponding level according to a signal output of the processing module.
[0022] The level selection module comprises at least one selection unit, the output ends of all the selection units are connected to each other to serve as the output end of the level selection module and connected to the level conversion module, the first input end of each selection unit is connected to the power supply module, and the second input end of each selection unit is connected to the processing module.
[0023] Optionally, the selection unit comprises a ninth resistor, a tenth resistor, an eleventh resistor, a triode, a first Pmos tube and a second Pmos tube.
[0024] The drain of the first Pmos tube serves as the output end of the selection unit, the first Pmos tube and the second Pmos tube both have a parasitic diode, the anode of the parasitic diode of the first Pmos tube is connected to the drain of the first Pmos tube, the cathode of the parasitic diode of the first Pmos tube is connected to the source of the first Pmos tube, the source of the first Pmos tube is connected to one end of the ninth resistor, the source of the second Pmos tube and the cathode of the parasitic diode of the second Pmos tube respectively, the drain of the second Pmos tube serves as the first input end of the selection unit, the other end of the ninth resistor is connected to the gate of the first Pmos tube, the gate of the second Pmos tube and the collector of the triode respectively, the gate of the triode is connected to one end of the tenth resistor, the other end of the tenth resistor serves as the second input end of the selection unit and is connected to one end of the eleventh resistor, and the other end of the eleventh resistor and the emitter of the triode are both connected to ground.
[0025] Optionally, the waveform generator further comprises a storage module.
[0026] The storage module is connected to the processing module, wherein the storage module comprises a sixth chip, a twelfth resistor, a thirteenth resistor and a sixth capacitor.
[0027] The three output ends and the ground end of the sixth chip are all connected to ground, the power supply end of the sixth chip is connected to a power supply, one end of the sixth capacitor, one end of the twelfth resistor and one end of the thirteenth resistor respectively, the other end of the sixth capacitor is connected to the write protection end of the sixth chip and ground respectively, the other end of the twelfth resistor is connected to the clock end of the sixth chip, and the other end of the thirteenth resistor is connected to the transmission end of the sixth chip.
[0028] Optionally, the waveform generator further comprises a serial port module.
[0029] The serial port module is connected to the processing module, wherein the serial port module comprises a seventh chip, a seventh capacitor and an eighth capacitor.
[0030] The power supply end of the seventh chip is connected with a power supply, one end of the seventh capacitor is connected with the power supply end of the seventh chip, the other end of the seventh capacitor is connected with the ground, the ground end of the seventh chip is connected with the ground, the transmitting end and the receiving end of the seventh chip are connected with the processing module, the actual power supply end of the seventh chip is connected with the ground through the eighth capacitor, and the positive signal end and the negative signal end of the seventh chip are used for connecting external equipment.
[0031] The second aspect of the embodiment of the application provides a test device, which comprises the waveform generator as described above.
[0032] It can be seen from the above technical solutions that the embodiment of the application has the following advantages:
[0033] The waveform generator of the application is provided with a pulse generation module, and the preset circuit structure in the pulse generation module enables the pulse generation module to output one of the preset number of pulse signals with different frequencies. When the transceiver module to be tested needs to be tested, only a test instruction needs to be input, and the corresponding pulse signal can be output based on the test instruction. The generation structure corresponding to the preset number of pulse signals with different frequencies for testing is set in advance, and the pulse generation module is controlled by the processing module to output when needed. Compared with the cost of an arbitrary waveform generator, the cost is lower, and resource waste is avoided, thereby reducing the economic burden of testing. BRIEF DESCRIPTION OF DRAWINGS
[0034] In order to more clearly illustrate the technical solutions in the embodiments of the application, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments described in the application, and other drawings can also be obtained by those skilled in the art based on these drawings.
[0035] Figure 1 An embodiment schematic diagram of the waveform generator disclosed by the application;
[0036] Figure 2 Another embodiment schematic diagram of the waveform generator disclosed by the application;
[0037] Figure 3 A pulse generation module schematic diagram disclosed by the application;
[0038] Figure 4 A level conversion module schematic diagram disclosed by the application;
[0039] Figure 5 A selection unit schematic diagram of the level selection module disclosed by the application;
[0040] Figure 6 A storage module schematic diagram disclosed by the application;
[0041] Figure 7 a serial port module disclosed in the present application;
[0042] Figure 8 a processing flow chart of a processing module disclosed in the present application. DETAILED DESCRIPTION
[0043] The present application will be further described in detail below with reference to the accompanying drawings.
[0044] Embodiments of the present application provide a waveform generator and test equipment, which are used to reduce the cost of test transceiver modules.
[0045] The transceiver module needs to be tested before use. In the existing scheme, an arbitrary waveform generator is used to generate the required pulse signal to complete the test. However, although the arbitrary waveform generator can generate many pulse signals of different frequencies, only a few pulse signals of specific frequencies are used for testing, which causes resource waste and high cost. In addition, the driving ability of the arbitrary waveform generator itself is weak, and if more transceiver modules need to be accessed for simultaneous testing, the waveform may be deteriorated or lose the driving effect. In order to solve the above problems, the present application provides a waveform generator and test equipment, which pre-sets the generation structure corresponding to the preset number of different frequency pulse signals for testing in advance, and then outputs the pulse signal by the processing module when needed. Compared with the cost of the arbitrary waveform generator, the cost is lower, the resource waste is avoided, and the driving ability is stronger.
[0046] In order to enable the personnel in the technical field to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by the person skilled in the art without creative labor should belong to the scope of protection of the present application.
[0047] The terms "first", "second", "third", "fourth" and the like in the description, claims, and drawings of the present application are used to distinguish similar objects, and do not necessarily indicate a particular order or sequence. It should be understood that the data thus used can be interchanged under appropriate circumstances, so that the embodiments described herein can be implemented in an order other than that illustrated or described herein. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion.
[0048] A waveform generator of the present application will be described below. Please refer to Figure 1 An embodiment of a waveform generator of the present application includes a processing module and a pulse generation module.
[0049] The input end of the pulse generation module is connected with the processing module, the output end of the pulse generation module is taken as the port of the output pulse signal, and the pulse generation module is used for outputting one of the preset number of pulse signals with different frequencies. For example, four required different frequencies, 1 kHz, 5 kHz, 10 kHz and 50 kHz, can be set.
[0050] The processing module is used for controlling the pulse generation module to output the pulse signal with the specific frequency corresponding to the test instruction according to the test instruction for the to-be-tested transceiver module. Specifically, the processing module can be an STM32 type single-chip microcomputer, or other, which is not limited here, and preferably, the processing module is an STM32F103C8T6 single-chip microcomputer.
[0051] The working principle of the embodiment will be illustrated. The processing module receives the test instruction, selects the corresponding structure in the pulse generation module according to the test instruction, and controls the corresponding structure of the pulse generation module to output the pulse signal with the corresponding frequency.
[0052] In the embodiment of the application, the waveform generator is provided with the pulse generation module, the preset circuit structure in the pulse generation module enables the pulse generation module to output one of the preset number of pulse signals with different frequencies, when the to-be-tested transceiver module needs to be tested, only the test instruction needs to be input, and the corresponding pulse signal can be output based on the test instruction. The generation structure corresponding to the preset number of pulse signals with different frequencies for testing is set in advance, and the processing module controls the pulse generation module to output when needed. Compared with the cost of an arbitrary waveform generator, the cost is lower, and resource waste is avoided, and the economic burden of testing is reduced.
[0053] Please refer to Figures 2 to 8 Another embodiment of the waveform generator of the application includes a processing module and a pulse generation module.
[0054] The input end of the pulse generation module is connected with the processing module, the output end of the pulse generation module is taken as the port of the output pulse signal, and the pulse generation module is used for outputting one of the preset number of pulse signals with different frequencies, for example, four required different frequencies, 1 kHz, 5 kHz, 10 kHz and 50 kHz, can be set.
[0055] The processing module is configured to control the pulse generation module to output a pulse signal with a specific frequency corresponding to a test instruction for a transceiver module to be tested according to the test instruction. Specifically, the processing module can be an STM32 type single-chip microcomputer, or other types, which are not limited herein. Preferably, the processing module is an STM32F103C8T6 single-chip microcomputer. The processing module outputs a set of IIC bus (PWM_SCL / PWM_SDA) to the pulse generation module.
[0056] The pulse generation module includes a generation unit and a plurality of frequency units. Specifically, the frequency units can be GP7101 chips, or other types, which are not limited herein.
[0057] The generation unit is connected to each of the frequency units, and the processing module is connected to the generation unit and the plurality of frequency units. An output end of the generation unit serves as an output end of the pulse generation module. Each of the frequency units cooperates with the generation unit to generate a pulse signal with a corresponding frequency. The frequencies corresponding to the frequency units are different from each other.
[0058] In this embodiment, four frequency units are described (only one is shown in the figure for simplicity, Figure 3 The frequency unit includes a first chip U1, a first resistor R1, a second resistor R2, and a first capacitor C1.
[0059] One end of the first resistor R1 is connected to a power supply, one end of the second resistor R2, one end of the first capacitor C1, and a power supply end of the first chip U1, respectively. The other end of the first resistor R1 is connected to the generation unit and a clock end of the first chip U1, respectively. The other end of the second resistor R2 is connected to the processing module and a transmission end of the first chip U1, respectively. The other end of the first capacitor C1 and a ground end of the first chip U1 are both grounded. A non-inverting pulse end and an inverting pulse end of the first chip U1 are both connected to the generation unit. Specifically, the transmission end of the first chip U1 is connected to the PWM_SDA line of the processing module. The clock end of the first chip U1 is connected to a first input end of a second chip U2. The non-inverting pulse end of the first chip U1 is connected to a first input end of a third chip U3. The inverting pulse end of the first chip U1 is connected to a fifth input end of the third chip U3.
[0060] If the number of frequency units is four, the generation unit includes a second chip U2, a third chip U3, a third resistor R3, a fourth resistor R4, a fifth resistor R5, and a sixth resistor R6. Specifically, the second chip U2 and the third chip U3 are CD4052B chips, or other types, which are not limited herein.
[0061] The first input end, the second input end, the third input end and the fourth input end of the second chip U2 are respectively connected with a frequency unit, the frequency units connected with the first input end, the second input end, the third input end and the fourth input end of the second chip U2 are different from each other, one end of the third resistor R3 is connected with the first input end of the second chip U2, one end of the fourth resistor R4 is connected with the second input end of the second chip U2, one end of the fifth resistor R5 is connected with the third input end of the second chip U2, one end of the sixth resistor R6 is connected with the fourth input end of the second chip U2, the other end of the third resistor R3, the other end of the fourth resistor R4, the other end of the fifth resistor R5 and the other end of the sixth resistor R6 are all connected with a power supply, the common input end of the second chip U2 is connected with the processing module, the inhibit output end, the negative power supply end and the common ground end of the second chip U2 are all connected with the ground, the first control end and the second control end of the second chip U2 are both connected with the processing module. Specifically, the common input end of the second chip U2 is connected with the PWM_SCL line of the processing module.
[0062] The first input end, the second input end, the third input end and the fourth input end of the third chip U3 are respectively connected with a frequency unit, the frequency units connected with the first input end, the second input end, the third input end and the fourth input end of the third chip U3 are different from each other, the fifth input end, the sixth input end, the seventh input end and the eighth input end of the third chip U3 are respectively connected with a frequency unit, the frequency units connected with the fifth input end, the sixth input end, the seventh input end and the eighth input end of the third chip U3 are different from each other, the first output end of the third chip U3 is used for connecting one end of the first input end, the second input end, the third input end and the fourth input end of the third chip U3, the second output end of the third chip U3 is used for connecting one end of the fifth input end, the sixth input end, the seventh input end and the eighth input end of the third chip U3, the inhibit output end, the negative power supply end and the common ground end of the third chip U3 are all connected with the ground, the first control end (FREQ_CRTL1) and the second control end (FREQ_CRTL2) of the third chip U3 are both connected with the processing module. Specifically, the first output end of the third chip U3 is connected with the second signal end (B end) of the fourth chip U4 of the level conversion module, the second output end of the third chip U3 is connected with the second signal end (B end) of the fifth chip U5 of the level conversion module.
[0063] Wherein, in order to adjust the voltage (or level) of the finally output pulse signal, the voltage provided by the power supply module can be pre-set, and then a pulse signal with a specific level and a specific frequency is adjusted out. The waveform generator further comprises a power supply module and a level conversion module;
[0064] The output end of the pulse generation module is connected to the level conversion module, the output end of the level conversion module is used as the output end of the waveform generator, the power module is connected with the processing module and the level conversion module respectively, the power module is used for providing a voltage signal to the level conversion module, and the level conversion module is used for converting the pulse signal of a specific frequency provided by the pulse generation module according to the voltage signal and outputting.
[0065] Specifically, the level conversion module comprises a fourth chip U4, a fifth chip U5, a seventh resistor R7, an eighth resistor R8, a second capacitor C2, a third capacitor C3, a fourth capacitor C4 and a fifth capacitor C5. Specifically, the fourth chip U4 and the fifth chip U5 can be SN74LVC1T45 chips, and can also be other chips, which are not limited here.
[0066] The first power supply end of the fourth chip U4 is connected with the power module and one end of the second capacitor C2 respectively, the other end of the second capacitor C2 and the ground end of the fourth chip U4 are both grounded, the level of the first signal end of the fourth chip U4 is the same as that of the first power supply end of the fourth chip U4, the second power supply end of the fourth chip U4 is connected with the power supply and one end of the third capacitor C3 respectively, the other end of the third capacitor C3 and one end of the seventh resistor R7 are both grounded, the other end of the seventh resistor R7 is connected with the input and output direction end of the fourth chip U4, the level of the second signal end of the fourth chip U4 is the same as that of the second power supply end of the fourth chip U4, the first signal end of the fourth chip U4 is used as the output end of the waveform generator, and the second signal end of the fourth chip U4 is connected with the output end of the pulse generation module. Specifically, the first power supply end of the fourth chip U4 is connected with the power module through the level selection module, and in the embodiment, the first power supply end VCCA of the fourth chip U4 is connected with the drain of the first Pmos tube Q1 in the level selection module.
[0067] The first power supply end of the fifth chip U5 is connected with the power module and one end of the fourth capacitor C4 respectively, the other end of the fourth capacitor C4 and the ground end of the fifth chip U5 are both grounded, the level of the first signal end of the fifth chip U5 is the same as that of the first power supply end of the fifth chip U5, the second power supply end of the fifth chip U5 is connected with the power supply and one end of the fifth capacitor C5 respectively, the other end of the fifth capacitor C5 and one end of the eighth resistor R8 are both grounded, the other end of the eighth resistor R8 is connected with the input and output direction end of the fifth chip U5, the level of the second signal end of the fifth chip U5 is the same as that of the second power supply end of the fifth chip U5, the first signal end of the fifth chip U5 is used as the output end of the waveform generator, and the second signal end of the fifth chip U5 is connected with the output end of the pulse generation module. Specifically, the first power supply end of the fifth chip U5 is connected with the power module through the level selection module, and in the embodiment, the first power supply end VCCA of the fifth chip U5 is connected with the drain of the first Pmos tube Q1 in the level selection module.
[0068] The waveform generator further comprises a level selection module.
[0069] The power module is connected with the level conversion module through the level selection module, and the processing module is connected with the level selection module.
[0070] The level selection module comprises at least one selection unit, the output ends of all the selection units are connected with each other to serve as the output end of the level selection module and are connected with the level conversion module, the first input end of each selection unit is connected with the power module, and the second input end of each selection unit is connected with the processing module.
[0071] Specifically, the selection unit comprises a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11, a triode Q3, a first Pmos tube Q1 and a second Pmos tube Q2.
[0072] The drain of the first Pmos tube Q1 serves as the output end of the selection unit, the first Pmos tube Q1 and the second Pmos tube Q2 both have a parasitic diode, the anode of the parasitic diode of the first Pmos tube Q1 is connected with the drain of the first Pmos tube Q1, the cathode of the parasitic diode of the first Pmos tube Q1 is connected with the source of the first Pmos tube Q1, the source of the first Pmos tube Q1 is connected with one end of the ninth resistor R9, the source of the second Pmos tube Q2 and the cathode of the parasitic diode of the second Pmos tube Q2 respectively, the drain of the second Pmos tube Q2 serves as the first input end of the selection unit, the other end of the ninth resistor R9 is connected with the gate of the first Pmos tube Q1, the gate of the second Pmos tube Q2 and the collector of the triode Q3 respectively, the gate of the triode Q3 is connected with one end of the tenth resistor R10, the other end of the tenth resistor R10 serves as the second input end of the selection unit and is connected with one end of the eleventh resistor R11, and the other end of the eleventh resistor R11 and the emitter of the triode Q3 are both connected with the ground.
[0073] Wherein, in order to automatically select, the information of the transceiver module to be tested and the corresponding frequency can be pre-stored in the storage module for convenient calling and inquiry. The waveform generator further comprises a storage module. Specifically, the storage module can be an AT24C02 chip, and can also be other, which is not limited here. The memory thereof is byte-addressed through address bits, and is used to save user operation states, such as the brightness of the screen, the last used duty cycle and frequency information, voltage information corresponding to different measured parts, etc.
[0074] The storage module is connected with the processing module, wherein the storage module comprises a sixth chip U6, a twelfth resistor R12, a thirteenth resistor R13 and a sixth capacitor C6.
[0075] The three output terminals and the ground terminal of the sixth chip U6 are grounded, the power supply terminals of the sixth chip U6 are connected with the power supply, one end of the sixth capacitor C6, one end of the twelfth resistor R12 and one end of the thirteenth resistor R13 respectively, the other end of the sixth capacitor C6 is connected with the write protection terminal and the ground of the sixth chip U6 respectively, the other end of the twelfth resistor R12 is connected with the clock terminal of the sixth chip U6, and the other end of the thirteenth resistor R13 is connected with the transmission terminal of the sixth chip U6.
[0076] Wherein, in order to realize communication, the waveform generator further comprises a serial port module. The serial port module can be a CH340C chip, and can also be other, which is not limited here. The USART_TX and USART_RX of the processing module are converted into USB_DP and USB_DN signals of USB protocol, and communicate with external devices. In this design, the baud rate used is 115200.
[0077] The serial port module is connected with the processing module, wherein the serial port module comprises a seventh chip U7, a seventh capacitor C7 and an eighth capacitor C8.
[0078] The power supply terminal of the seventh chip U7 is connected with the power supply, one end of the seventh capacitor C7 is connected with the power supply terminal of the seventh chip U7, the other end of the seventh capacitor C7 is grounded, the ground terminal of the seventh chip U7 is grounded, the transmitting terminal and the receiving terminal of the seventh chip U7 are connected with the processing module, the actual power supply terminal of the seventh chip U7 is grounded through the eighth capacitor C8, and the positive signal terminal and the negative signal terminal of the seventh chip U7 are used to connect external devices.
[0079] In addition, the waveform generator in the embodiment further comprises an LED module, a key module and an OLED display screen, and can also adopt 8-way in-phase and 8-way anti-phase output.
[0080] Figure 8The specific execution flow of the processing module. When the program is initialized, the processing module will read the parameters of the transceiver module to be tested in the storage module, configure the corresponding correct voltage, and when the key trigger or instruction is transmitted, the processing module modifies the duty cycle and frequency, and displays the updated UI interface on the OLED display screen.
[0081] The working principle of the embodiment is described by example. The processing module receives a test instruction, controls the SG end of the corresponding selection unit to be a high-level signal (selection level) through the 2-4 decoder, then the transistor Q3 is turned on, the gate of the first Pmos tube Q1 and the second Pmos tube Q2 is grounded, and because the source voltage of the two Pmos tubes is greater than the gate voltage, the two Pmos tubes are turned on. The power module supplies power to the VCOM end through the VIN end, the diode of the second Pmos tube Q2 and the first Pmos tube Q1, and the VCOM end is high. On the other side, the processing module transmits information through the PWM_SCL line and the PWM_SDA line, controls the PWM_SCL end of the second chip U2 to be connected to one of the frequency units (for example, PWM_SCL1) through the FREQ_CRTL1 end and the FREQ_CRTL2 end, controls the PWM_COMM end of the third chip U3 to be connected to the PWM1 end of the same frequency unit, and controls the PWMB_COMM end of the third chip U3 to be connected to the PWMB1 end of the same frequency unit. The PWM_COMM end and the PWMB_COMM end of the third chip U3 are both output, and are output to the B end of the fourth chip U4 and the B end of the fifth chip U5 in the level conversion module. Because the DIR pin of the fourth chip U4 and the fifth chip U5 is set to low level, the fourth chip U4 and the fifth chip U5 are both input from the B end and output from the A end. Based on the principle of the fourth chip U4 and the fifth chip U5, the level voltage of the A end is consistent with the VCOM end, and the frequency is consistent with the B end. The A end of the two chips is connected to the external port, so that a pulse signal with a specific level voltage and a specific frequency is output.
[0082] In the embodiment, the waveform generator is provided with a pulse generation module. The preset circuit structure in the pulse generation module enables the pulse generation module to output one of a preset number of pulse signals with different frequencies. When the transceiver module to be tested needs to be tested, only the test instruction needs to be input, and the corresponding pulse signal can be output based on the test instruction. The generation structure corresponding to the preset number of pulse signals with different frequencies for testing is preset in advance, and the pulse generation module is controlled by the processing module to output when needed. Compared with the cost of an arbitrary waveform generator, this embodiment does not cause resource waste and reduces the economic burden of testing.
[0083] In addition, the application also discloses a test device. One embodiment of the test device in the embodiment comprises the waveform generator as described above.
[0084] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the above-described system, device and unit can refer to the corresponding processes in the foregoing embodiments, and will not be repeated here.
[0085] In several embodiments provided in the present application, it should be understood that the disclosed system, device and method can be implemented in other ways. For example, the device embodiments described above are only schematic, for example, the division of units is only a logical function division, and actual implementation can have another division manner, for example, a plurality of units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the units shown or discussed can be indirect coupling or communication connection through some interface, device or unit, and can be electrical, mechanical or other forms.
[0086] The units described as separate components can or can not be physically separate, and the components shown as units can or can not be physical units, that is, they can be located in one place, or can be distributed on a plurality of network units. Part or all of the units can be selected according to actual needs to achieve the purpose of the embodiment scheme.
[0087] In addition, each functional unit in each embodiment of the present application can be integrated into a processing unit, or each unit can exist physically, or two or more units can be integrated into one unit.
[0088] The above, the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: it can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement for part of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application.
Claims
1. A waveform generator, characterized by, The application relates to a test system for a transceiver module. The test system comprises a processing module and a pulse generation module. An input end of the pulse generation module is connected with the processing module, an output end of the pulse generation module is a port for outputting an output pulse signal, and the pulse generation module is used for outputting one of preset pulse signals with different frequencies. The processing module is used for controlling the pulse generation module to output a pulse signal with a specific frequency corresponding to a test instruction for a transceiver module to be tested according to the test instruction.
2. The waveform generator of claim 1, wherein, The pulse generation module comprises a generation unit and a plurality of frequency units. The generation unit is connected with each of the frequency units, the processing module is connected with the generation unit and the plurality of frequency units respectively, and an output end of the generation unit is an output end of the pulse generation module.
3. The waveform generator of claim 2, wherein, Each of the frequency units cooperates with the generation unit to generate a pulse signal with a corresponding frequency, and the frequencies corresponding to the frequency units are different from each other. The frequency unit comprises a first chip, a first resistor, a second resistor and a first capacitor.
4. The waveform generator of claim 2, wherein, One end of the first resistor is connected with a power supply, one end of the second resistor, one end of the first capacitor and a power supply end of the first chip respectively, the other end of the first resistor is connected with the generation unit and a clock end of the first chip respectively, the other end of the second resistor is connected with the processing module and a transmission end of the first chip respectively, the other end of the first capacitor and a ground end of the first chip are grounded, and a same-phase pulse end and an inverse-phase pulse end of the first chip are connected with the generation unit. If the number of the frequency units is four, the generation unit comprises a second chip, a third chip, a third resistor, a fourth resistor, a fifth resistor and a sixth resistor. First, second, third and fourth input ends of the second chip are connected with one of the frequency units respectively, the frequency units connected with the first, second, third and fourth input ends of the second chip are different from each other, one end of the third resistor is connected with the first input end of the second chip, one end of the fourth resistor is connected with the second input end of the second chip, one end of the fifth resistor is connected with the third input end of the second chip, one end of the sixth resistor is connected with the fourth input end of the second chip, the other end of the third resistor, the other end of the fourth resistor, the other end of the fifth resistor and the other end of the sixth resistor are connected with a power supply, a common input end of the second chip is connected with the processing module, an inhibit output end, a negative power supply end and a common ground end of the second chip are grounded, and first and second control ends of the second chip are connected with the processing module. The first input end, the second input end, the third input end and the fourth input end of the third chip are connected with one frequency unit respectively, the frequency units connected with the first input end, the second input end, the third input end and the fourth input end of the third chip are different from each other, the fifth input end, the sixth input end, the seventh input end and the eighth input end of the third chip are connected with one frequency unit respectively, the frequency units connected with the fifth input end, the sixth input end, the seventh input end and the eighth input end of the third chip are different from each other, the first output end of the third chip is used for connecting one end of the first input end, the second input end, the third input end and the fourth input end of the third chip, the second output end of the third chip is used for connecting one end of the fifth input end, the sixth input end, the seventh input end and the eighth input end of the third chip, the disable output end, the negative power supply end and the common ground end of the third chip are grounded, and the first control end and the second control end of the third chip are connected with the processing module.
5. The waveform generator of claim 1, wherein, The waveform generator further comprises a power module and a level conversion module; The output end of the pulse generation module is connected with the level conversion module, the output end of the level conversion module is used as the output end of the waveform generator, the power module is connected with the processing module and the level conversion module respectively, the power module is used for providing a voltage signal to the level conversion module, and the level conversion module is used for converting and outputting the pulse signal of a specific frequency provided by the pulse generation module according to the voltage signal.
6. The waveform generator of claim 5, wherein, The level conversion module comprises a fourth chip, a fifth chip, a seventh resistor, an eighth resistor, a second capacitor, a third capacitor, a fourth capacitor and a fifth capacitor. The first power supply end of the fourth chip is connected with the power module and one end of the second capacitor respectively, the other end of the second capacitor and the ground end of the fourth chip are grounded, the level of the first power supply end of the fourth chip is the same as that of the first signal end of the fourth chip, the second power supply end of the fourth chip is connected with the power supply and one end of the third capacitor respectively, the other end of the third capacitor and one end of the seventh resistor are grounded, the other end of the seventh resistor is connected with the input and output direction end of the fourth chip, the level of the second power supply end of the fourth chip is the same as that of the second signal end of the fourth chip, the first signal end of the fourth chip is used as the output end of the waveform generator, and the second signal end of the fourth chip is connected with the output end of the pulse generation module. The first power supply end of the fifth chip is connected with the power supply module and one end of the fourth capacitor respectively, the other end of the fourth capacitor and the ground end of the fifth chip are grounded, the first power supply end of the fifth chip has the same level as the first signal end of the fifth chip, the second power supply end of the fifth chip is connected with the power supply and one end of the fifth capacitor respectively, the other end of the fifth capacitor and one end of the eighth resistor are grounded, the other end of the eighth resistor is connected with the input and output direction end of the fifth chip, the second power supply end of the fifth chip has the same level as the second signal end of the fifth chip, the first signal end of the fifth chip is used as the output end of the waveform generator, and the second signal end of the fifth chip is connected with the output end of the pulse generation module.
7. The waveform generator of claim 5, wherein, The waveform generator further comprises a level selection module; The power supply module is connected with the level conversion module through the level selection module, and the processing module is connected with the level selection module. The level selection module comprises at least one selection unit, the output ends of all the selection units are connected with each other to serve as the output end of the level selection module and are connected with the level conversion module, the first input end of each selection unit is connected with the power supply module, and the second input end of each selection unit is connected with the processing module.
8. The waveform generator of claim 7, wherein, The selection unit comprises a ninth resistor, a tenth resistor, an eleventh resistor, a triode, a first Pmos tube and a second Pmos tube. The drain of the first Pmos tube serves as the output end of the selection unit, the first Pmos tube and the second Pmos tube both have a parasitic diode, the anode of the parasitic diode of the first Pmos tube is connected with the drain of the first Pmos tube, the cathode of the parasitic diode of the first Pmos tube is connected with the source of the first Pmos tube, the source of the first Pmos tube is connected with one end of the ninth resistor, the source of the second Pmos tube and the cathode of the parasitic diode of the second Pmos tube respectively, the drain of the second Pmos tube serves as the first input end of the selection unit, the other end of the ninth resistor is connected with the gate of the first Pmos tube, the gate of the second Pmos tube and the collector of the triode respectively, the gate of the triode is connected with one end of the tenth resistor, the other end of the tenth resistor serves as the second input end of the selection unit and is connected with one end of the eleventh resistor, and the other end of the eleventh resistor and the emitter of the triode are grounded.
9. The waveform generator of claim 1, wherein, The waveform generator further comprises a storage module; The storage module is connected with the processing module, and the storage module comprises a sixth chip, a twelfth resistor, a thirteenth resistor and a sixth capacitor. The three output terminals and the ground terminal of the sixth chip are grounded, the power supply terminals of the sixth chip are connected with a power supply, one end of a sixth capacitor, one end of a twelfth resistor and one end of a thirteenth resistor respectively, the other end of the sixth capacitor is connected with the write protection terminal and the ground terminal of the sixth chip respectively, the other end of the twelfth resistor is connected with the clock terminal of the sixth chip, and the other end of the thirteenth resistor is connected with the transmission terminal of the sixth chip.
10. The waveform generator of claim 1, wherein, The waveform generator further comprises a serial port module; The serial port module is connected with the processing module, wherein the serial port module comprises a seventh chip, a seventh capacitor and an eighth capacitor; The power supply terminal of the seventh chip is connected with a power supply, one end of the seventh capacitor is connected with the power supply terminal of the seventh chip, the other end of the seventh capacitor is grounded, the ground terminal of the seventh chip is grounded, the transmitting terminal and the receiving terminal of the seventh chip are connected with the processing module, the actual power supply terminal of the seventh chip is grounded through the eighth capacitor, and the positive signal terminal and the negative signal terminal of the seventh chip are used for connecting external devices.
11. A test apparatus, characterized by The waveform generator comprises the waveform generator as claimed in any one of claims 1 to 10.