High-speed quantum random number chip encryption equipment

Abstract

The utility model discloses high-speed quantum random number chip encryption equipment which comprises a quantum random number chip, an FPGA (Field Programmable Gate Array), an encryption and decryption module, a processing module and an interface module, the FPGA is in bidirectional connection with the quantum random number chip, the encryption and decryption module and the processing module, and the FPGA communicates with external equipment through the interface module. The utility model discloses high-speed quantum random number chip encryption equipment which adopts a quantum random number chip as a quantum random number source, so that the generation efficiency of quantum random numbers is greatly improved, the integration level is higher, the acquisition cost of the random numbers is reduced, and the popularization of application products in the fields of commercial passwords and information security is facilitated.

Description

TECHNICAL FIELD

[0001] The utility model relates to quantum encryption equipment and information security technical field, concretely relates to a high -speed quantum random number chip encryption equipment. BACKGROUND

[0002] In the information age, people pay more and more attention to privacy and data security. Traditional data encryption technology can be cracked in theory, especially the data processing speed surge brought by quantum technology development and the optimization of quantum algorithm, which greatly threatens the security of traditional encryption algorithm.

[0003] Quantum random number generator (QRNG) is the only theoretically provable true random number generator so far, based on quantum effect, quantum random number generator has higher security.

[0004] The security of quantum encryption technology is based on the basic principles of quantum mechanics, which provides absolute security guarantee that cannot be eavesdropped and cracked by calculation. However, the existing quantum encryption equipment uses laser light source and detection sampling circuit as the way to provide quantum random number source, and the cost of random number acquisition is relatively high. At the same time, it also leads to low integration of the system, and the efficiency of generating random number is also low. Moreover, the existing quantum encryption equipment also uses the resources in FPGA to encrypt and decrypt the data, which will reduce the ability of FPGA to process data, and make the overall efficiency of the system lower. UTILITY MODEL CONTENT

[0005] The utility model discloses in order to solve the problem of low efficiency of the existing quantum encryption equipment to generate random number, and proposes a high-speed quantum random number chip encryption equipment.

[0006] In order to achieve the above purpose, the technical scheme adopted by the utility model is as follows:

[0007] A high-speed quantum random number chip encryption equipment, including quantum random number chip, FPGA, encryption and decryption module, processing module and interface module;

[0008] The FPGA is bidirectionally connected with the quantum random number chip, the encryption and decryption module and the processing module respectively, and the FPGA communicates with external equipment through the interface module.

[0009] In the above scheme, the quantum random number chip is used as the quantum random number source, which greatly improves the generation efficiency of quantum random number, has higher integration, and also reduces the acquisition cost of random number, which is conducive to the popularization and application of the product.

[0010] Preferably, it further includes a quantum key storage module, which is bidirectionally connected with the processing module.

[0011] Preferably, the interface module includes a PCIe interface.

[0012] Preferably, the interface module further includes a JTAG interface.

[0013] Preferably, it also includes a FLASH memory, which is bidirectionally connected to the FPGA.

[0014] Preferably, the processing module is an MCU.

[0015] Preferably, the quantum random number chip is model QRNG100SPI.

[0016] Preferably, the encryption / decryption module is model ACH512.

[0017] Preferably, the MCU is an STM32F103RCT6.

[0018] The beneficial technical effects of this utility model are:

[0019] This invention provides a high-speed quantum random number chip encryption device. By using a quantum random number chip as the quantum random number source, it significantly improves the generation efficiency of quantum random numbers, has a higher integration level, and reduces the cost of obtaining random numbers, which is conducive to the promotion of commercial cryptography and information security application products. Attached Figure Description

[0020] Figure 1 This is a schematic diagram of the module connection of this utility model;

[0021] The components include: 1. Quantum random number chip; 2. Encryption / decryption module; 3. Processing module; 4. Interface module; 41. PCIE interface; 42. JTAG interface; 5. Quantum key storage module; 6. FLASH memory. Detailed Implementation

[0022] To make the objectives, technical solutions and advantages of this utility model clearer, the present utility model will be further described in detail below with reference to the embodiments. However, the scope of protection of this utility model is not limited to the specific embodiments described below.

[0023] Example 1

[0024] like Figure 1 As shown, a high-speed quantum random number chip encryption device includes a quantum random number chip 1, an FPGA, an encryption / decryption module 2, a processing module 3, and an interface module 4.

[0025] The FPGA is bidirectionally connected with the quantum random number chip 1, the encryption and decryption module 2 and the processing module 3 respectively, and the FPGA communicates with external equipment through the interface module 4.

[0026] In the specific implementation process, the quantum random number chip 1 is used as a quantum random number source, which greatly improves the generation efficiency of quantum random numbers, has higher integration, reduces the acquisition cost of random numbers, and is conducive to the popularization and application of products.

[0027] Embodiment 2

[0028] A high-speed quantum random number chip encryption device, comprising a quantum random number chip 1, an FPGA, an encryption and decryption module 2, a processing module 3 and an interface module 4.

[0029] The FPGA is bidirectionally connected with the quantum random number chip 1, the encryption and decryption module 2 and the processing module 3 respectively, and the FPGA communicates with external equipment through the interface module 4.

[0030] More specifically, it further comprises a quantum key storage module 5, which is bidirectionally connected with the processing module 3.

[0031] In the specific implementation process, the quantum key storage module 5 is used to store the quantum key generated by the MCU.

[0032] More specifically, the interface module 4 comprises a PCIE interface 41.

[0033] In the specific implementation process, the PCIE interface 41 is used to realize high-speed communication between the FPGA and external equipment.

[0034] More specifically, the interface module 4 further comprises a JTAG interface 42.

[0035] In the specific implementation process, the JTAG interface 42 is used for circuit debugging of the FPGA, and the configuration program of the FPGA is downloaded into the FLASH memory 6 (or the RAM memory of the FPGA) through the JTAG interface 42.

[0036] More specifically, it further comprises a FLASH memory 6, which is bidirectionally connected with the FPGA.

[0037] In the specific implementation process, the FLASH memory 6 is used to store the configuration program of the FPGA, which is used to configure the function of the FPGA; when the FPGA is powered on, the function of the FPGA is initialized and defined.

[0038] More specifically, the processing module 3 is an MCU.

[0039] More specifically, the model of the quantum random number chip 1 is QRNG100SPI.

[0040] More specifically, the model of the decryption module 2 is ACH512.

[0041] More specifically, the model of the MCU is STM32F103RCT6.

[0042] In the specific implementation process, first, the FPGA sends a sampling signal to the quantum random number chip 1, and the quantum random number chip 1 generates a quantum source random number sequence consistent with the frequency of the sampling signal into the FPGA after receiving the sampling signal, and the FPGA caches the random number into the internal memory after receiving the quantum source random number sequence.

[0043] Then the FPGA sends a communication signal to the MCU, and after the MCU responds to the communication signal of the FPGA; the FPGA sends a quantum random number source sequence to the MCU; the MCU receives the quantum source random number sequence, and generates a corresponding quantum encryption and decryption key based on the quantum random number source sequence according to the pre-built existing key algorithm and stores it in the key storage module.

[0044] When the data that needs to be encrypted and decrypted enters the FPGA from the external device through the PCIE interface 41, the FPGA establishes communication with the encryption and decryption module 2 and transmits the data to the encryption and decryption module 2; after receiving the data, the encryption and decryption module 2 communicates with the FPGA, and the MCU reads the quantum encryption and decryption key in the key storage module to the encryption and decryption module 2; after receiving the key, the encryption and decryption module 2 encrypts and decrypts the data according to the corresponding requirements; the data encrypted and decrypted by the encryption and decryption module 2 is transmitted back to the FPGA, and the FPGA transmits the data to the external device through the PCIE interface 41.

[0045] In the specific implementation process, the external encryption and decryption module 2 is used to encrypt and decrypt the data, which reduces the resource consumption of the FPGA, improves the data processing capability of the FPGA, and improves the performance of the entire quantum encryption device.

[0046] According to the disclosure and teaching of the above description, those skilled in the art of the present application can also change and modify the above embodiments. Therefore, the present application is not limited to the specific embodiments disclosed and described above, and some modifications and changes of the application should fall within the protection scope of the claims of the application. In addition, although some specific terms are used in the specification, these terms are only for convenience and do not constitute any limitation on the application.

Claims

1. A high-speed quantum random number chip encryption device, characterized by, Quantum random number chip, FPGA, encryption and decryption module, processing module and interface module are included. The FPGA is bidirectionally connected with the quantum random number chip, the encryption and decryption module and the processing module respectively, and communicates with external equipment through the interface module.

2. A high-speed quantum random number chip encryption device according to claim 1, characterized in that, A quantum key storage module is further included, which is bidirectionally connected with the processing module.

3. The high-speed quantum random number chip encryption device of claim 1, wherein, The interface module includes a PCIE interface.

4. A high-speed quantum random number chip encryption device according to claim 3, characterized in that, The interface module further includes a JTAG interface.

5. A high-speed quantum random number chip encryption device according to claim 4, characterized in that, A FLASH memory is further included, which is bidirectionally connected with the FPGA.

6. The high-speed quantum random number chip encryption device of claim 1, wherein, The processing module is an MCU.

7. The high-speed quantum random number chip encryption device of claim 1, wherein, The quantum random number chip is of QRNG100SPI model.

8. The high-speed quantum random number chip encryption device of claim 1, wherein, The encryption and decryption module is of ACH512 model.

9. The high-speed quantum random number chip encryption device of claim 6, wherein, The MCU is of STM32F103RCT6 model.

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