Cell layout device

Abstract

A cellular layout device relates to the technical field of semiconductors. Comprising a SiC Sub layer, a SiC Drift layer, an ohmic contact alloy layer and a front electrode metal layer which are sequentially arranged from bottom to top. The SiC Drift layer is provided with a plurality of P-body regions which are arranged at intervals, respectively extend downwards from the top surface of the SiC Drift layer and are of a cross-shaped structure, and a plurality of P-body regions which are arranged at intervals and respectively extend downwards from the top surface of the SiC Drift layer; the plurality of NP regions are of a cross-shaped structure and respectively extend downwards from the top surface of the P-body region, and a distance is formed between the bottom surface of each NP region and the bottom surface of the P-body region; a channel region is formed in the space between the side surface of the NP region and the side surface of the P-body region; according to the utility model, the P-body region and the NP region adopt the cross layout structure design, and compared with the traditional strip layout, the area of the channel region in the device can be increased by 20%-30%, so that the density of the channel region of a through-flow path can be increased, the through-flow capability of the unit area of the SiC MOSFET device is greatly improved, and the conduction performance of the device is better.

Description

TECHNICAL FIELD

[0001] The utility model relates to the technical field of semiconductor, especially to a cell layout device. BACKGROUND

[0002] With the rapid development of society, the whole world is calling for advocating energy conservation and environmental protection, which also makes the new energy automobile, clean energy and other fields develop very rapidly under the impetus of society, such as the 800V platform of new energy automobile, the high-power application of photovoltaic energy storage inverter, etc., which also promotes the development of power electronics technology field, and the terminal customer begins to put forward more strict requirements for the performance, reliability and the like of power device. However, the traditional Si-based device has been difficult to show better performance, therefore, the third generation semiconductor device represented by SiC benefits from the excellent characteristics of the material, and at the same time, it can also reduce the system volume and size, realize the cost reduction.

[0003] In SiC power devices, SiC MOSFET is the most core product, which benefits from the material characteristics and also has the switching advantage of MOSFET unipolar structure device, so compared with the most commonly used Si MOSFET and Si IGBT switching devices on the market, its performance is more outstanding. However, due to the later development of SiC, compared with Si-based devices, it is not mature enough, therefore, how to increase the channel region density of SiC MOSFET device and improve the current-carrying capacity per unit area of SiC MOSFET device is a technical problem that needs to be solved by the technical personnel in the field at present. CONTENT OF THE UTILITY MODEL

[0004] In view of the above problems, the utility model designs a kind of cell layout device, which greatly increases the channel region density of device and improves the current-carrying capacity per unit area of SiC MOSFET device.

[0005] The technical scheme of the utility model is:

[0006] A kind of cell layout device, including SiC Sub layer, SiC Drift layer, Ohmic contact alloy layer and front electrode metal layer from bottom to top in turn;

[0007] The SiC Drift layer is provided with:

[0008] P-body region, there are several, interval arrangement, and respectively from the top surface of the SiC Drift layer downwardly extending, it is cross-shaped structure;

[0009] NP region, provided with several, cross-shaped structure, respectively from the top surface of the P-body region downwardly extending, the bottom surface with the bottom surface of the P-body region is provided with spacing; The spacing between the side surface of the NP region and the side surface of the P-body region forms a channel region;

[0010] PP region, from the parasitic diode adjacent position The top surface of the NP region extends downwardly and is connected with the P-body region; The depth of the downward extension of the PP region is not less than the depth of the downward extension of the NP region;

[0011] Gate oxide layer, located between the top surface of the adjacent NP region, the bottom surface is connected with the NP region, P-body region and SiC drift layer respectively;

[0012] Poly layer, provided on the top surface of the gate oxide layer;

[0013] Isolation medium layer, located on the top surface of the Poly layer, and the side portion extends downwardly to the top surface of the NP region.

[0014] Specifically, the ohmic contact alloy layer is located between the adjacent isolation medium layer, and the bottom surface is connected with the NP region.

[0015] Specifically, the bottom surface depth of the P-body region (3) is 0.6um-2um.

[0016] Specifically, the bottom surface depth of the NP region (4) is 0.3um-1.6um.

[0017] Specifically, the bottom surface depth of the PP region (5) is 0.3um-1.8um.

[0018] The P-body region and the NP region of the utility model adopt cross-shaped layout structure design, compared with the traditional strip-shaped layout, the area of the channel region in the device can be increased by 20%-30%, so that the channel region density of the through-flow path can be increased, resulting in that the through-flow capacity of the SiC MOSFET device per unit area is greatly improved, and the conduction performance of the device obtains better effect. BRIEF DESCRIPTION OF DRAWINGS

[0019] Figure 1 It is the cross-shaped plane gate SiC MOSFET plan view of the utility model, (the gate oxide layer 6, the Poly layer 7, the isolation medium layer 8, the ohmic contact alloy layer 9 and the front electrode metal layer 10 are hidden in the drawing);

[0020] Figure 2 It is the conventional strip-shaped plane gate SiC MOSFET plan view;

[0021] Figure 3 It is Figure 1 the structure diagram in AA section X direction of

[0022] Figure 4 is Figure 1 a structural view in the Y direction of the BB section of

[0023] Figure 1 is a SiC Sub layer, 2 is a SiC Drift layer, 3 is a P-body region, 4 is an NP region, 5 is a PP region, 6 is a gate oxide layer, 7 is a Poly layer, 8 is an isolation dielectric layer, 9 is an ohmic contact alloy layer, and 10 is a front electrode metal layer. DETAILED DESCRIPTION

[0024] The utility model will be explained in detail below in combination with specific actual cases. The examples of the embodiments are shown in the drawings, and the illustrative embodiments of the utility model and the description thereof are only used to explain the utility model and do not limit the utility model.

[0025] A cell layout device comprises the following steps:

[0026] S100, a SiC Drift layer 2 is grown on the top surface of a SiC Sub layer 1 by epitaxial deposition, the SiC Sub layer 1 serves as a support, and the SiC Drift layer 2 serves as a protective function.

[0027] The conductive type of the SiC Sub layer 1 and the SiC Drift layer 2 in step S100 is N type.

[0028] S200, a P-body region 3 in a cross-shaped structure is formed on the top surface of the SiC Drift layer 2 by Al ion implantation.

[0029] The bottom surface depth of the P-body region 3 in step S200 is 0.6um-2um, and the doping concentration is 1E17-3E18cm -2 .

[0030] S300, an NP region 4 in a cross-shaped structure is formed on the top surface of the P-body region 3 by N ion implantation.

[0031] The bottom surface depth of the NP region 4 in step S300 is 0.3um-1.6um, and the doping concentration is 1E18-3E19cm -2 .

[0032] S400, a PP region 5 is formed on the top surface of the NP region 4 by Al ion implantation.

[0033] The bottom surface depth of the PP region 5 in step S400 is 0.3um-1.8um, and the doping concentration is 1E18-3E19cm -2 .

[0034] S500, by high temperature annealing, P-body region 3, NP region 4 and PP region 5 injection region activation formation;

[0035] The high temperature annealing temperature condition in step S500 is 1600-1900℃.

[0036] S600, a gate oxide layer 6 is formed by dry oxygen oxidation growth on the top surface of both ends of the NP region 4, and NO is introduced during the process to improve the quality of the gate oxide layer;

[0037] The thickness of the gate oxide layer 6 in step S600 is 40-70nm.

[0038] S700, a Poly layer 7 is formed on the top surface of the gate oxide layer 6 by Poly deposition, which is used as the gate electrode of the device;

[0039] The thickness of the Poly layer 7 in step S700 is 300-800nm.

[0040] S800, an isolation medium layer 8 is formed on the top surface of the NP region 4 and the Poly layer 7 by oxide deposition, which is used as the medium for isolating the gate electrode and the source electrode of the device at the source, to avoid short circuit between the two;

[0041] S900, an ohmic contact alloy layer 9 connected with the NP region 4 is formed on the side of the isolation medium layer 8 by Ni metal sputtering or deposition and then rapid thermal annealing;

[0042] The thickness of the Ni metal in step S900 is 100-300nm.

[0043] S1000, a front electrode metal layer 10 is formed on the top surface of the isolation medium layer 8 and the ohmic contact alloy layer 9 by Ti and AlCu metal sputtering or evaporation;

[0044] The thickness of the Ti metal in step S1000 is 0.1-0.6um, and the thickness of the AlCu metal is 2-5um.

[0045] A cell layout device, comprising a SiC Sub layer 1, a SiC Drift layer 2, an ohmic contact alloy layer 9 and a front electrode metal layer 10 arranged in turn from bottom to top;

[0046] The SiC Drift layer 2 is provided with:

[0047] P-body region 3, provided with several, arranged at intervals, and respectively extended downward from the top surface of the SiC Drift layer 2;

[0048] NP region 4, provided with several, respectively from the top surface of the P-body region 3 extends downward, the bottom surface and the bottom surface of the P-body region 3 is provided with spacing; The spacing between the side surface of the NP region 4 and the side surface of the P-body region 3 forms a channel region;

[0049] PP region 5, from the parasitic diode adjacent position of the NP region 4 top surface extends downward, and is connected with P-body region 3; The depth of the downward extension of the PP region 5 is not less than the depth of the downward extension of the NP region 4;

[0050] Gate oxide layer 6, located between the top surface of the adjacent NP region 4, the bottom surface is connected with the NP region 4, P-body region 3 and SiC Drift layer 2 respectively;

[0051] Poly layer 7, provided on the top surface of the gate oxide layer 6;

[0052] Isolation medium layer 8, located on the top surface of the Poly layer 7, and the side portion extends downward to the top surface of the NP region 4.

[0053] The ohmic contact alloy layer 9 is located between the adjacent isolation medium layer 8, and the bottom surface is connected with the NP region 4.

[0054] The bottom surface of the front electrode metal layer 10 is connected with the isolation medium layer 8 and the ohmic contact alloy layer 9 respectively.

[0055] The utility model discloses a cross-shaped layout structure design is adopted to SiCMOSFET, compared with the traditional strip type layout, this design can increase the area of channel region in the device 20%-30% to improve the through-flow capacity of the device nearly 20%, the plane grid SiC MOSFET device on the market at present adopts strip cell layout, only makes channel region in horizontal or vertical one direction, and the cross-shaped layout makes the channel region present serpentine layout, makes channel region in horizontal and vertical, and the channel region density of device is increased greatly, as the increase of channel region density of through-flow path, the through-flow capacity of SiCMOSFET device per unit area is increased greatly, and the conduction performance of device is better.

Claims

1. A cellular layout device, characterized by, The SiC Sub layer (1), the SiC Drift layer (2), the ohmic contact alloy layer (9) and the front electrode metal layer (10) are sequentially arranged from bottom to top. The SiC Drift layer (2) is provided with: A P-body region (3) is provided with a plurality of P-body regions, which respectively extend downward from the top surface of the SiC Drift layer (2) and have a cross-shaped structure. A plurality of NP regions (4) have a cross-shaped structure and respectively extend downward from the top surface of the P-body region (3), and the bottom surface of the NP region (4) is spaced apart from the bottom surface of the P-body region (3); the spacing between the side surface of the NP region (4) and the side surface of the P-body region (3) forms a channel region. A PP region (5) extends downward from the top surface of the NP region (4) adjacent to the parasitic body diode and is connected with the P-body region (3). A gate oxide layer (6) is located on the top surface between adjacent NP regions (4) and is connected with the NP region (4), the P-body region (3) and the SiC Drift layer (2) at the bottom surface. A Poly layer (7) is arranged on the top surface of the gate oxide layer (6). An isolation medium layer (8) is located on the top surface of the Poly layer (7) and extends downward to the top surface of the NP region (4) at the side.

2. A cellular layout device according to claim 1, wherein, The ohmic contact alloy layer (9) is located between adjacent isolation medium layers (8) and is connected with the NP region (4) at the bottom surface.

3. A cellular layout device according to claim 1, wherein, The bottom surface depth of the P-body region (3) is 0.6-2um.

4. A cellular layout device according to claim 1, wherein, The bottom surface depth of the NP region (4) is 0.3-1.6um.

5. A cellular layout device according to claim 1, wherein, The bottom surface depth of the PP region (5) is 0.3-1.8um.

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