Display device

Abstract

Disclosed is a display device including a substrate, a first thin film transistor, and a second thin film transistor. The first thin film transistor is positioned on the substrate and includes a first semiconductor layer and a first gate electrode. The second thin film transistor is positioned on the substrate and includes a second semiconductor layer and a second gate electrode. A first angle between the channel region of the first semiconductor layer and the substrate is different from a second angle between the channel region of the second semiconductor layer and the substrate. The first gate electrode and the second gate electrode are positioned in the same layer.

Description

[0001] Cross Reference to Related Applications

[0002] This application is based on and claims priority to Korean Patent Application No. 10-2023-0186146, filed on December 19, 2023, in the Korean Intellectual Property Office, the disclosure of which is incorporated by reference herein in its entirety. TECHNICAL FIELD

[0003] One or more embodiments relate to a display apparatus. BACKGROUND

[0004] Generally, a display apparatus includes a light emitting element and a pixel circuit for controlling an electrical signal applied to the light emitting element. The pixel circuit includes a thin film transistor (TFT), a capacitor, and a plurality of wirings. The light emitting element emits light in response to the electrical signal applied from the wirings.

[0005] Research into high integration and high reliability of such a display apparatus is being actively conducted. SUMMARY

[0006] Embodiments can provide a display apparatus that is highly integrated and can display high-quality images. However, embodiments are examples and do not limit the scope of the present disclosure.

[0007] Additional aspects will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art upon examination of the following description and drawings, or can be learned by practice of the presented embodiments.

[0008] According to one or more embodiments, a display apparatus includes a substrate, a first thin film transistor positioned on the substrate and including a first semiconductor layer and a first gate electrode, and a second thin film transistor positioned on the substrate and including a second semiconductor layer and a second gate electrode, wherein a first angle between a channel region of the first semiconductor layer and the substrate is different from a second angle between a channel region of the second semiconductor layer and the substrate, and wherein the first gate electrode and the second gate electrode are positioned on the same layer.

[0009] The first angle can be 0° to 5°, and the second angle can be 20° to 90°.

[0010] The display apparatus can further include a lower conductive layer positioned between the substrate and the first semiconductor layer, wherein the second thin film transistor further includes a lower electrode and an upper electrode, wherein the lower conductive layer and the lower electrode are positioned on the same layer, and wherein the lower electrode of the second thin film transistor can be connected to the lower conductive layer.

[0011] A central portion of the second semiconductor layer can be connected to the lower electrode, and a peripheral portion of the second semiconductor layer can be connected to the upper electrode.

[0012] The display apparatus can further include a first insulating layer positioned between the lower electrode and the upper electrode, wherein the first insulating layer includes a first opening extending to the lower electrode, and at least a portion of the second semiconductor layer is positioned in the first opening.

[0013] The display apparatus can further include a second insulating layer covering the second semiconductor layer, wherein a thickness of the second insulating layer is less than a thickness of the first insulating layer.

[0014] The display apparatus can further include a storage capacitor including a first capacitor electrode and a second capacitor electrode, wherein the first capacitor electrode is positioned in a same layer as the first gate electrode and the second gate electrode.

[0015] Each of the first semiconductor layer and the second semiconductor layer can include an oxide semiconductor.

[0016] The display apparatus can further include a third thin film transistor positioned on the substrate and including a third semiconductor layer and a third gate electrode, wherein each of the first semiconductor layer and the second semiconductor layer includes an oxide semiconductor, and the third semiconductor layer includes a silicon semiconductor.

[0017] The third gate electrode can be positioned over the third semiconductor layer and under the first insulating layer, and the first semiconductor layer can be positioned over the first insulating layer.

[0018] According to one or more embodiments, a display apparatus includes a substrate, a first insulating layer positioned on the substrate and including a first opening, a first thin film transistor including a first semiconductor layer positioned on a top surface of the first insulating layer and a first gate electrode, and a second thin film transistor including a second semiconductor layer positioned at least partially in the first opening, a lower electrode positioned under the first insulating layer, an upper electrode positioned over the first insulating layer, and a second gate electrode positioned on the second semiconductor layer, wherein the first gate electrode and the second gate electrode are positioned in a same layer.

[0019] An angle between an inner wall of the first opening and a top surface of the substrate can be 20° to 90°.

[0020] The display apparatus can further include a lower conductive layer positioned between the substrate and the first semiconductor layer, wherein the lower electrode and the lower conductive layer are positioned in a same layer.

[0021] A central portion of the second semiconductor layer can be connected to the lower electrode, and a peripheral portion of the second semiconductor layer can be connected to the upper electrode.

[0022] The display apparatus can further include a second insulating layer covering the first semiconductor layer and the second semiconductor layer, wherein the first gate electrode and the second gate electrode can be positioned on the second insulating layer, and a thickness of the second insulating layer can be less than a thickness of the first insulating layer.

[0023] Each of the first and second semiconductor layers can include an oxide semiconductor.

[0024] The display apparatus can further include a storage capacitor including a first capacitor electrode and a second capacitor electrode, wherein the first capacitor electrode is positioned at the same layer as the first and second gate electrodes.

[0025] The display apparatus can further include a third thin-film transistor positioned on the substrate and including a third semiconductor layer and a third gate electrode, wherein each of the first and second semiconductor layers includes an oxide semiconductor, and the third semiconductor layer includes a silicon semiconductor.

[0026] The third gate electrode can be positioned above the third semiconductor layer and below the first insulating layer, and the first semiconductor layer can be positioned above the first insulating layer.

[0027] The third thin-film transistor can be a driving thin-film transistor. BRIEF DESCRIPTION OF DRAWINGS

[0028] The above and other aspects, features and advantages of certain embodiments will be more apparent from the following description taken in conjunction with the accompanying drawings, in which:

[0029] Figure 1 is a plan view schematically showing a display apparatus according to an embodiment;

[0030] Figure 2 and Figure 3 is an equivalent circuit diagram showing a sub-pixel included in the display apparatus according to an embodiment;

[0031] Figure 4 is a schematic cross-sectional view taken along line I-I' of Figure 1

[0032] Figure 5 , Figure 6 , Figure 7 , Figure 8 , Figure 9 , Figure 10 , Figure 11 , Figure 12 , Figure 13 and Figure 14 are cross-sectional views schematically showing portions of a process of manufacturing a display apparatus according to an embodiment;

[0033] Figure 15 is a cross-sectional view schematically showing a display apparatus according to an embodiment;

[0034] Figure 16 is a cross-sectional view schematically showing a display apparatus according to an embodiment; ​

[0035] Figure 17 is a cross-sectional view schematically illustrating a display apparatus according to an embodiment;

[0036] Figure 18 is a plan view schematically illustrating a portion of a display apparatus according to an embodiment; and

[0037] Figure 19 is a plan view schematically illustrating a comparative example with respect to Figure 18 an embodiment. DETAILED DESCRIPTION

[0038] Reference will now be made in detail embodiments, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to like elements throughout. In this regard, the present embodiments can have different forms and should not be construed as being limited to the descriptions set forth herein. Accordingly, the embodiments are merely descriptive of aspects of the present description, as follows by referring to the figures in which:

[0039] As used herein, the word "or" means a logical "or" and thus includes the possibilities of both "and" and "or" unless the context clearly indicates otherwise. Throughout this disclosure, the expression "at least one of a, b, and c" indicates only a, only b, only c, both a and b, both a and c, both b and c, all of a, b, and c, or variations thereof.

[0040] Since the present disclosure allows various changes and numerous embodiments, some embodiments will be shown in the drawings and described in detail in the detailed description. The effects and features of the present disclosure and methods for achieving them will become apparent by referring to the embodiments described below in detail with reference to the accompanying drawings. However, the present disclosure is not limited to the following embodiments and can be implemented in various forms.

[0041] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings, wherein the same or corresponding elements are denoted by the same reference numerals at all times and repetitive description thereof is omitted.

[0042] Although the terms "first", "second", and the like can be used to describe various elements, the elements should not be limited by these terms. These terms are only used to distinguish one element from another.

[0043] The singular forms "a," "an," and "the" as used herein are intended to include plural forms as well, unless the context clearly indicates otherwise.

[0044] It will also be understood that the terms "comprises" and "comprising" as used herein specify the presence of stated features or components, but do not preclude the presence or addition of one or more other features or components.

[0045] It will also be understood that when a layer, region or component is referred to as being "on" another layer, region or component, it can be directly on the other layer, region or component, or intervening layers, regions or components can also be present.

[0046] The size of the components in the drawings can be arbitrarily increased or reduced for convenience of explanation. For example, since the size and thickness of the components in the drawings are arbitrarily shown for convenience of explanation, the present disclosure is not limited thereto.

[0047] It will be understood that when referring to a layer, region or component being "connected", the layer, region or component can be directly connected, or can be indirectly connected with intervening layers, regions or components. For example, when referring to a layer, region or component being "electrically connected", the layer, region or component can be directly electrically connected, or can be indirectly electrically connected with intervening layers, regions or components.

[0048] In the following embodiments, the x-axis, y-axis and z-axis are not limited to the three axes of a rectangular coordinate system, and can be interpreted in a broader sense. For example, the x-axis, y-axis and z-axis can be perpendicular to each other, or can represent different directions that are not perpendicular to each other.

[0049] Figure 1 is a plan view schematically showing a display apparatus according to an embodiment.

[0050] Referring to Figure 1 The substrate 100 of the display apparatus 10 can be divided into a display area DA and a peripheral area PA around the display area DA. The display apparatus 10 can provide a certain image by using light emitted from a plurality of pixels P positioned in the display area DA.

[0051] An edge of the display area DA can have a substantially rectangular or square shape. Accordingly, the substrate 100 can also have a substantially rectangular or square shape. An edge of the display area DA can have a circular shape, an elliptical shape, or other polygonal shape.

[0052] Although an organic light emitting display apparatus is described as the display apparatus according to an embodiment, the display apparatus of the present disclosure is not limited thereto. In another embodiment, the display apparatus of the present disclosure can be a display apparatus such as an inorganic light emitting display apparatus (or inorganic electroluminescent (EL) display apparatus) or a quantum dot light emitting display apparatus. For example, an emission layer of a light emitting element included in the display apparatus can include an organic material or an inorganic material. In addition, the display apparatus can include a quantum dot positioned in a path of light emitted from the emission layer.

[0053] A plurality of pixels P is positioned in the display area DA. Each pixel P can indicate a sub-pixel. Each pixel P can emit, for example, red light, green light, blue light, or white light.

[0054] Each pixel P can include a pixel circuit including a thin film transistor (TFT) and a storage capacitor. The pixel circuit can be connected to a scan line SL, a data line DL intersecting the scan line SL, and a driving voltage line PL. The scan line SL can extend in an x direction, and the data line DL and the driving voltage line PL can extend in a y direction.

[0055] Each pixel P can emit light by driving the pixel circuit, and the display area DA provides a specific image by the light emitted from the pixel P. The pixel P in the specification can be defined as an emission area that emits red light, green light, blue light, or white light as described above.

[0056] The peripheral area PA is an area in which no pixel P is positioned and which does not provide an image. A built-in driving circuit unit for driving the pixel P, a printed circuit board including a power supply wiring and a driving circuit unit, or a terminal unit to which a driver integrated circuit (IC) is connected can be positioned in the peripheral area PA.

[0057] Figure 2 and Figure 3 is an equivalent circuit diagram illustrating a sub-pixel included in a display apparatus according to an embodiment.

[0058] Referring to Figure 2 The light emitting element LED corresponding to the sub-pixel can be electrically connected to the pixel circuit PC, and the pixel circuit PC can include a first transistor T1, a second transistor T2, and a storage capacitor Cst. The pixel circuit PC can be electrically connected to a signal line and a voltage line. The signal line can include a gate line such as a first scan line SL1 and a data line DL, and the voltage line can include a first voltage line VDDL.

[0059] The second transistor T2 can be electrically connected to the first scan line SL1 and the data line DL. The first scan line SL1 can provide a first scan signal GW to a gate electrode of the second transistor T2. The second transistor T2 can transfer a data signal Dm input from the data line DL to the first transistor T1 according to the first scan signal GW input from the first scan line SL1.

[0060] The storage capacitor Cst can be electrically connected to the second transistor T2 and the first transistor T1, and can store a voltage corresponding to the data signal Dm.

[0061] The first transistor T1 is a driving transistor and can control a driving current flowing through the light emitting element LED. The first transistor T1 can be connected to the first voltage line VDDL and the storage capacitor Cst. The first transistor T1 can control the driving current flowing through the light emitting element LED from the first voltage line VDDL in response to a value of a voltage stored in the storage capacitor Cst. The lower conductive layer BML can be positioned under the first transistor T1. The lower conductive layer BML can be connected to the first electrode of the light emitting element LED and the storage capacitor Cst. However, the disclosure is not limited thereto. The lower conductive layer BML can be connected to the first voltage line VDDL to receive a constant voltage.

[0062] The light emitting element LED can emit light having a certain brightness due to the driving current. The first electrode of the light emitting element LED can be electrically connected to the first transistor T1, and the second electrode of the light emitting element LED can be electrically connected to the second voltage line VSSL that supplies the second power supply voltage VSS.

[0063] Each of the first transistor T1 and the second transistor T2 can be an N-type transistor. For example, each of the first transistor T1 and the second transistor T2 can include a semiconductor layer including an oxide. In some embodiments, the first transistor T1 can be a horizontal channel transistor including a semiconductor layer parallel to a top surface of a substrate, and the second transistor T2 can be a vertical channel transistor including a semiconductor layer having a certain angle with respect to the top surface of the substrate.

[0064] Although the pixel circuit PC includes two transistors and one storage capacitor in Figure 2 , in another embodiment, the pixel circuit PC can include three or more transistors.

[0065] Referring to Figure 3 , the pixel circuit PC can include the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the storage capacitor Cst.

[0066] The pixel circuit PC is electrically connected to signal lines and voltage lines. The signal lines can include gate lines such as the first scan line SL1, the second scan line SL2, the third scan line SL3, and the emission control line EML, and the data line DL. The voltage lines can include the first initialization voltage line VIL1 and the second initialization voltage line VIL2, and the first voltage line VDDL.

[0067] The first voltage line VDDL can transmit the first power supply voltage VDD to the first transistor T1. The first initialization voltage line VIL1 can transmit a first initialization voltage Vint for initializing the first transistor T1 to the pixel circuit PC. The second initialization voltage line VIL2 can transmit a second initialization voltage Vaint for initializing the first electrode of the light emitting element LED to the pixel circuit PC.

[0068] The first transistor T1 can be electrically connected to the first voltage line VDDL via the fifth transistor T5, and can be electrically connected to the light emitting element LED via the sixth transistor T6. The first transistor T1 functions as a driving transistor, and receives a data signal Dm and supplies a driving current to the light emitting element LED according to a switching operation of the second transistor T2.

[0069] The lower conductive layer BML can be positioned under the first transistor T1. The lower conductive layer BML can be connected to one electrode of the third transistor T3 or one electrode of the sixth transistor T6. When one electrode of the third transistor T3 and one electrode of the sixth transistor T6 are positioned in the same layer as the lower conductive layer BML, the electrodes do not need to be connected to a connection member positioned in another layer through a contact hole, thereby achieving high integration. The second transistor T2 is a data writing transistor, and is electrically connected to the first scan line SL1 and the data line DL. The second transistor T2 is electrically connected to the first voltage line VDDL via the fifth transistor T5. The second transistor T2 is turned on according to a first scan signal GW received through the first scan line SL1 to perform a switching operation of transmitting a data signal Dm received through the data line DL to the first node N1.

[0070] The third transistor T3 is electrically connected to the first scan line SL1, and is electrically connected to the light emitting element LED via the sixth transistor T6. The third transistor T3 can be turned on according to a first scan signal GW received through the first scan line SL1 to diode-connect the first transistor T1.

[0071] The fourth transistor T4 is a first initialization transistor, and is electrically connected to the third scan line SL3 and the first initialization voltage line VIL1. The fourth transistor T4 is turned on according to a third scan signal GI received through the third scan line SL3 to initialize a voltage of a gate electrode of the first transistor T1 by transmitting a first initialization voltage Vint from the first initialization voltage line VIL1 to the gate electrode of the first transistor T1. The third scan signal GI can correspond to a first scan signal of another pixel circuit positioned in a previous row of the pixel circuit PC.

[0072] The fifth transistor T5 can be an operation control transistor, and the sixth transistor T6 can be an emission control transistor. The fifth transistor T5 and the sixth transistor T6 are electrically connected to an emission control line EML, and are simultaneously turned on according to an emission control signal EM received through the emission control line EML to form a current path through which a driving current can flow from a first voltage line VDDL to the light emitting element LED.

[0073] The seventh transistor T7 is a second initialization transistor and can be electrically connected to a second scan line SL2, a second initialization voltage line VIL2, and the sixth transistor T6. The seventh transistor T7 can be turned on according to a second scan signal GB received through the second scan line SL2 to initialize the first electrode of the light emitting element LED by transmitting a second initialization voltage Vaint from the second initialization voltage line VIL2 to the first electrode of the light emitting element LED.

[0074] The storage capacitor Cst includes a first capacitor electrode CE1 and a second capacitor electrode CE2. The first capacitor electrode CE1 is electrically connected to the gate electrode of the first transistor T1, and the second capacitor electrode CE2 is electrically connected to the first voltage line VDDL. The storage capacitor Cst can maintain the voltage applied to the gate electrode of the first transistor T1 by storing and maintaining the voltage corresponding to the voltage difference between the first voltage line VDDL and the gate electrode of the first transistor T1.

[0075] Although the third transistor T3 and the fourth transistor T4 among the plurality of transistors (e.g., the transistors T1 to T7) are N-type transistors and the remaining transistors are P-type transistors in Figure 3 , the present disclosure is not limited thereto. Various modifications can be made. For example, the transistors among the plurality of transistors (e.g., the transistors T1 to T7) except for the third transistor T3 and the fourth transistor T4 can be N-type transistors.

[0076] In an embodiment, at least one of the plurality of transistors (e.g., the transistors T1 to T7) can include an oxide-containing semiconductor layer, and the remaining transistors can include a silicon-containing semiconductor layer. For example, each of the third transistor T3 and the fourth transistor T4 can include an oxide semiconductor layer, and the remaining transistors can include a silicon semiconductor layer. However, the present disclosure is not limited thereto. All of the plurality of transistors (e.g., the transistors T1 to T7) can include an oxide semiconductor layer.

[0077] Figure 4 is a schematic cross-sectional view taken along line I-I' of Figure 1 .

[0078] Referring to Figure 4In the display device according to the embodiment, a pixel circuit PC can be positioned on the substrate 100, and an organic light emitting diode OLED can be positioned as a light emitting element connected to the pixel circuit PC.

[0079] The pixel circuit PC according to the present embodiment includes a first thin film transistor TFT1 as a horizontal type transistor and a second thin film transistor TFT2 as a vertical type transistor.

[0080] The horizontal type transistor in the specification refers to a thin film transistor in which a direction of current flow through a semiconductor layer is substantially parallel to a top surface of the substrate 100. That is, an angle between a channel region of the semiconductor layer of the horizontal type transistor and the top surface of the substrate 100 can be in a range from about 0° to about 5°.

[0081] The vertical type transistor in the specification refers to a thin film transistor in which a direction of current flow through a semiconductor layer has a certain angle with respect to a top surface of the substrate 100. That is, an angle between a channel region of the semiconductor layer of the vertical type transistor and the top surface of the substrate 100 can be in a range from about 20° to about 90°, preferably in a range from about 45° to about 90°.

[0082] The first thin film transistor TFT1 is a horizontal type transistor and includes a first semiconductor layer AO1 and a first gate electrode GE1 insulated from the first semiconductor layer AO1. The first thin film transistor TFT1 can further include a first electrode EE1 and a second electrode EE2 connected to a first side and a second side of a channel region of the first semiconductor layer AO1, respectively. One of the first electrode EE1 and the second electrode EE2 can be a source electrode, and the other can be a drain electrode. A lower conductive layer BML overlapping the first semiconductor layer AO1 can be positioned under the first thin film transistor TFT1. The lower conductive layer BML can prevent external light from reaching the first semiconductor layer AO1. The lower conductive layer BML can function as a lower gate electrode. Alternatively, the lower conductive layer BML can be connected to various wirings to provide a voltage, so that driving of the first thin film transistor TFT1 can be stabilized.

[0083] The first semiconductor layer AO1 is provided to be substantially parallel to the top surface of the substrate 100. An angle between the first semiconductor layer AO1 and the top surface of the substrate 100 can be in a range from about 0° to about 5°. A first angle between a channel region of the first semiconductor layer AO1 and the substrate 100 can be different from a second angle between a channel region of the second semiconductor layer AO2 and the substrate 100. The first semiconductor layer AO1 can overlap the first gate electrode GE1, and a length L1 of the channel region of the first semiconductor layer AO1 can be determined by a width of the first gate electrode GE1.

[0084] The first thin film transistor TFT1 can be used as a driving thin film transistor. Since a horizontal transistor has a wider driving range than a vertical transistor and high process reliability, when the first thin film transistor TFT1 as a horizontal transistor is used as a driving thin film transistor, the reliability of the display apparatus can be improved.

[0085] The second thin film transistor TFT2 is a vertical transistor and includes a second semiconductor layer AO2 and a second gate electrode GE2 insulated from the second semiconductor layer AO2. The second thin film transistor TFT2 can further include a lower electrode BE and an upper electrode TE. One of the lower electrode BE and the upper electrode TE can be a source electrode, and the other can be a drain electrode. The lower electrode BE and the upper electrode TE can contact a bottom surface of the second semiconductor layer AO2.

[0086] The lower electrode BE can contact a central portion of the second semiconductor layer AO2. The upper electrode TE can be positioned above the lower electrode BE and can contact a peripheral portion of the second semiconductor layer AO2. A channel region can be formed in the second semiconductor layer AO2 positioned between the upper electrode TE and the lower electrode BE. The channel region of the second semiconductor layer AO2 has a certain angle with respect to a top surface of the substrate 100. The angle θ1 between the channel region of the second semiconductor layer AO2 and the top surface of the substrate 100 can be in a range from about 20° to about 90°, preferably in a range from about 45° to about 90°. The length L2 of the channel region of the second semiconductor layer AO2 can be a length between the lower electrode BE and the upper electrode TE and can be adjusted by the thickness t1 of the first insulating layer 111.

[0087] The second thin film transistor TFT2 can be a switching thin film transistor. When the second thin film transistor TFT2 as a vertical transistor is employed, the length of the channel region can be adjusted vertically, thereby saving space and achieving high integration.

[0088] In the present embodiment, the first gate electrode GE1 of the first thin film transistor TFT1 and the second gate electrode GE2 of the second thin film transistor TFT2 can be formed in the same layer by the same material. In addition, the lower conductive layer BML and the lower electrode BE of the second thin film transistor TFT2 can be formed in the same layer by the same material. Through this configuration, process time and process cost can be minimized.

[0089] Hereinafter, a stack structure of elements included in the display apparatus of the present embodiment will be described.

[0090] The substrate 100 can be formed of an insulating material such as glass, quartz, or a polymer resin. The substrate 100 can be a rigid substrate or a flexible substrate that can be bent, folded, or rolled. The substrate 100 can have a single-layer or multi-layer structure including the above-described materials, and when the substrate 100 has a multi-layer structure, the substrate 100 can further include an inorganic layer. In some embodiments, the substrate 100 can have a structure including an organic material, an inorganic material, and an organic material.

[0091] The lower conductive layer BML and the lower electrode BE of the second thin film transistor TFT2 are positioned on the substrate 100. Each of the lower conductive layer BML and the lower electrode BE can include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), or titanium (Ti), and can have a single-layer or multi-layer structure including the above-described materials. An insulating layer such as a barrier layer can be further positioned between the substrate 100 and the lower conductive layer BML or between the substrate 100 and the lower electrode BE. In an embodiment, the lower conductive layer BML can be connected to the lower electrode BE of the second thin film transistor TFT2. In this case, the lower conductive layer BML and the lower electrode BE are positioned in the same layer, and thus can be directly connected to the lower electrode BE. When the lower conductive layer BML and the lower electrode BE are positioned in different layers, since the lower conductive layer BML and the lower electrode BE should be connected to each other through a contact hole, a space in which the contact hole is to be formed can be additionally required. In the present embodiment, since the contact hole is not required, high integration can be possible. The first insulating layer 111 can be provided on the substrate 100 to cover the lower conductive layer BML and the lower electrode BE. The first insulating layer 111 can include an inorganic material such as an oxide or a nitride, an organic material, or a combination of an organic material and an inorganic material, and can have a single-layer or multi-layer structure including an inorganic material and an organic material. In some embodiments, the first insulating layer 111 can be formed of silicon oxide (SiO2), silicon nitride (SiN x ), or silicon oxynitride (SiO x N y ).

[0092] The first insulating layer 111 can be positioned between the lower electrode BE and the upper electrode TE to insulate the lower electrode BE from the upper electrode TE. That is, the lower electrode BE can be positioned under the first insulating layer 111, and the upper electrode TE can be positioned over the first insulating layer 111. In addition, the length L2 of the channel region of the second semiconductor layer AO2 can be adjusted by using the thickness t1 of the first insulating layer 111. The thickness t1 of the first insulating layer 111 can be adjusted to several hundreds to several thousands In some embodiments, the length L2 of the channel region of the second semiconductor layer AO2 can be smaller than the length L1 of the channel region of the first semiconductor layer AO1. The first insulating layer 111 can be positioned between the lower conductive layer BML and the first semiconductor layer AO1 to insulate the lower conductive layer BML from the first semiconductor layer AO1.

[0093] The first insulating layer 111 can include an opening 111OP extending to the lower electrode BE. The upper electrode TE can be positioned on the first insulating layer 111 around the opening 111OP.

[0094] The upper electrode TE can be positioned on the first insulating layer 111 and can surround at least a portion of the opening 111OP defined in the first insulating layer 111. Portions of the upper electrode TE positioned on both sides of the opening 111OP can be connected to each other. The upper electrode TE can include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), or titanium (Ti), and can have a single layer or a multi-layer structure including the above-described materials.

[0095] The first semiconductor layer AO1 of the first thin film transistor TFT1 can be provided on the first insulating layer 111 to overlap the lower conductive layer BML. The second semiconductor layer AO2 of the second thin film transistor TFT2 can be positioned on a top surface of the upper electrode TE and in the opening 111OP of the first insulating layer 111. The second semiconductor layer AO2 can contact the lower electrode BE through the opening 111OP. The second semiconductor layer AO2 positioned between the lower electrode BE and the upper electrode TE can be a channel region, and a length L2 of the channel region can be adjusted by a thickness t1 of the first insulating layer 111. An angle Θ1 between the channel region of the second semiconductor layer AO2 and a top surface of the substrate 100 can be in a range from about 20° to about 90°, preferably in a range from about 45° to about 90°. Alternatively, an angle Θ1 between an inner surface of the opening 111OP and the top surface of the substrate 100 can be in a range from about 20° to about 90°, preferably in a range from about 45° to about 90°.

[0096] The first semiconductor layer AO1 and the second semiconductor layer AO2 can be formed of the same material. Each of the first semiconductor layer AO1 and the second semiconductor layer AO2 can include an oxide semiconductor. For example, each of the first semiconductor layer AO1 and the second semiconductor layer AO2 can include an oxide of a material selected from Group IVB, Group 12, Group 13, and Group 14 metal elements, such as zinc (Zn), indium (In), gallium (Ga), tin (Sn), cadmium (Cd), germanium (Ge), or hafnium (Hf), and combinations thereof. In some embodiments, the first semiconductor layer AO1 and the second semiconductor layer AO2 can be formed of a Zn-oxide-based material, such as a Zn oxide, an In-Zn oxide, or a Ga-In-Zn oxide. For example, the first semiconductor layer AO1 and the second semiconductor layer AO2 can be formed of, for example, zinc oxide (ZnO), zinc tin oxide (ZTO), zinc indium oxide (ZIO), indium oxide (InO), titanium oxide (TiO), indium gallium zinc oxide (IGZO), or indium zinc tin oxide (IZTO).

[0097] A second insulating layer 113 is provided on the substrate 100 to cover the first semiconductor layer AO1 and the second semiconductor layer AO2. The second insulating layer 113 can be formed of silicon oxide (SiO2), silicon nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), or hafnium oxide (HfO2). A portion of the second insulating layer 113 can be positioned in the opening 111OP of the first insulating layer 111 along the shape of the second semiconductor layer AO2. The thickness t2 of the second insulating layer 113 can be less than the thickness t1 of the first insulating layer 111.

[0098] The first gate electrode GE1 and the second gate electrode GE2 can be positioned on the second insulating layer 113. The first gate electrode GE1 can overlap the first semiconductor layer AO1. The length L1 of the channel region of the first semiconductor layer AO1 can be determined by the width of the first gate electrode GE1. That is, the portion of the first semiconductor layer AO1 overlapping the first gate electrode GE1 can be the channel region.

[0099] The second gate electrode GE2 can overlap the second semiconductor layer AO2. Also, the second gate electrode GE2 can overlap the lower electrode BE. A portion of the second gate electrode GE2 can be positioned in the opening 111OP of the first insulating layer 111.

[0100] The first gate electrode GE1 and the second gate electrode GE2 can be formed of the same material in the same layer. Each of the first gate electrode GE1 and the second gate electrode GE2 can include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), or titanium (Ti), and can have a single layer or a multi-layer structure including the above-described material.

[0101] A third insulating layer 115 can be provided on the substrate 100 to cover the first gate electrode GE1 and the second gate electrode GE2. The third insulating layer 115 can be formed of silicon oxide (SiO2), silicon nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), or hafnium oxide (HfO2).

[0102] A second electrode EE2 can be positioned on the third insulating layer 115. The second electrode EE2 can be connected to the first semiconductor layer AO1. The second electrode EE2 can be a source electrode or a drain electrode of the first thin film transistor TFT1. A portion of the second electrode EE2 can overlap the first gate electrode GE1 to form a capacitor. The second electrode EE2 can be connected to the source region or the drain region of the first semiconductor layer AO1 through a first contact hole CNT1 passing through the third insulating layer 115 and the second insulating layer 113. The first contact hole CNT1 can extend through the first insulating layer 111, and in this case, the second electrode EE2 can be connected to the lower conductive layer BML.

[0103] The second electrode EE2 can include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), or titanium (Ti), and can have a single layer or a multi-layer structure including the above-described material.

[0104] The fourth insulating layer 117 can be provided on the substrate 100 to cover the second electrode EE2. The fourth insulating layer 117 can be formed of silicon oxide (SiO2), silicon nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), or hafnium oxide (HfO2).

[0105] The first electrode EE1 and the first wiring WL1 can be positioned on the fourth insulating layer 117. The first electrode EE1 can be a source electrode or a drain electrode of the first thin film transistor TFT1. The first electrode EE1 can be connected to a source region or a drain region of the first semiconductor layer AO1 through a second contact hole CNT2 passing through the fourth insulating layer 117, the third insulating layer 115, and the second insulating layer 113. The first electrode EE1 can be a part of a wiring such as a driving voltage line. The first wiring WL1 can be connected to the upper electrode TE of the second thin film transistor TFT2. The first wiring WL1 can be a wiring that transmits a data signal or the like. Each of the first electrode EE1 and the first wiring WL1 can include molybdenum (Mo), aluminum (Al), copper (Cu), or titanium (Ti), and can have a single layer or a multi-layer structure.

[0106] The fifth insulating layer 119 can be provided on the substrate 100 to cover the first electrode EE1 and the first wiring WL1. The fifth insulating layer 119 can be formed of silicon oxide (SiO2), silicon nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), or hafnium oxide (HfO2).

[0107] The second wiring WL2 and the connection electrode CM can be positioned on the fifth insulating layer 119. The second wiring WL2 can be connected to the upper electrode TE of the second thin film transistor TFT2. The second wiring WL2 can be connected to the upper electrode TE through a third contact hole CNT3 passing through the fifth insulating layer 119, the fourth insulating layer 117, the third insulating layer 115, and the second insulating layer 113. The connection electrode CM can be connected to the second electrode EE2 of the first thin film transistor TFT1 through a contact hole.

[0108] Each of the second wiring WL2 and the connection electrode CM can include molybdenum (Mo), aluminum (Al), copper (Cu), or titanium (Ti), and can have a single layer or a multi-layer structure.

[0109] A sixth insulating layer 123 can be provided on the substrate 100 to cover the second wiring WL2. The sixth insulating layer 123 can be formed of silicon oxide (SiO2), silicon nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), or hafnium oxide (HfO2). Alternatively, the sixth insulating layer 123 can be formed of an organic material such as acrylic, benzocyclobutene (BCB), or hexamethyldisiloxane (HMDSO). When the sixth insulating layer 123 is formed of an organic insulating material, the sixth insulating layer 123 can planarize a top surface of a protective film covering the first thin film transistor TFT1 and the second thin film transistor TFT2.

[0110] The sixth insulating layer 123 can include a via hole VH extending to the connection electrode CM. The connection electrode CM and a pixel electrode 310 of the organic light emitting diode OLED positioned on the sixth insulating layer 123 can be connected to each other through the via hole VH.

[0111] The organic light emitting diode OLED including the pixel electrode 310, the counter electrode 330, and the intermediate layer 320 positioned between the pixel electrode 310 and the counter electrode 330 and including an emission layer can be positioned on the sixth insulating layer 123. The pixel electrode 310 can be in contact with the connection electrode CM through the via hole VH provided in the sixth insulating layer 123 to be connected to the first thin film transistor TFT1.

[0112] The pixel electrode 310 can be a transparent electrode or a reflective electrode. When the pixel electrode 310 is a transparent electrode, the pixel electrode 310 can include ITO, IZO, ZnO, or In2O3, and when the pixel electrode 310 is a reflective electrode, the pixel electrode 310 can include a reflective film formed of Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, or a compound thereof and a transparent film formed of ITO, IZO, ZnO, or In2O3. In some embodiments, the pixel electrode 310 can have a structure including ITO / Ag / ITO.

[0113] A pixel defining film 125 can be positioned on the sixth insulating layer 123. The pixel defining film 125 defines a pixel by having an opening (i.e., an opening 125OP extending to at least a central portion of the pixel electrode 310) corresponding to each pixel. In addition, the pixel defining film 125 increases a distance between an edge of the pixel electrode 310 and the counter electrode 330 positioned above the pixel electrode 310 to prevent an arc or the like from occurring at the edge of the pixel electrode 310. The pixel defining film 125 can be formed of an organic material such as polyimide or hexamethyldisiloxane (HMDSO).

[0114] The intermediate layer 320 of the organic light emitting diode OLED can include a low molecular weight material or a high molecular weight material. When the intermediate layer 320 includes a low molecular weight material, the intermediate layer 320 can have a single or stacked structure in which a hole injection layer (HIL), a hole transport layer (HTL), an organic emission layer (EML), an electron transport layer (ETL), and an electron injection layer (EIL) are stacked, and can include any one of various organic materials such as copper phthalocyanine (CuPc), N,N'-di(naphthalen-1-yl)-N,N'-diphenyl-benzidine (NPB), or tris(8-hydroxyquinoline)aluminum (Alq3). These layers can be formed by using vacuum deposition.

[0115] When the intermediate layer 320 includes a high molecular weight material, the intermediate layer 320 can have a structure including an HTL and an EML. In this case, the HTL can include poly(3,4-ethylenedioxythiophene) (PEDOT), and the EML can include a polymeric material such as a polyphenylenevinylene (PPV)-based material or a polyfluorene-based material. The intermediate layer 320 can be formed by using screen printing, inkjet printing, laser-induced thermal imaging (LITI), or the like.

[0116] The intermediate layer 320 is not necessarily limited thereto, and can have any one of various structures. The intermediate layer 320 can include a layer integrally formed throughout the plurality of pixel electrodes 310, or can include a layer patterned to correspond to each of the plurality of pixel electrodes 310.

[0117] The counter electrode 330 can face the pixel electrode 310 with the intermediate layer 320 interposed therebetween. That is, the counter electrode 330 can be integrally formed in the plurality of organic light emitting diodes OLED, and can correspond to the plurality of pixel electrodes 310. That is, the pixel electrode 310 can be patterned for each sub-pixel, and the counter electrode 330 can be formed so that a common voltage is applied to all pixels. The counter electrode 330 can be a transparent electrode or a reflective electrode. Holes and electrons injected from the pixel electrode 310 and the counter electrode 330 of the organic light emitting diode OLED can combine in an emission layer of the intermediate layer 320 to generate light.

[0118] A thin film encapsulation layer (not shown) can be further positioned on the organic light emitting diode OLED to seal the organic light emitting diode OLED. The thin film encapsulation layer can be provided by stacking at least one inorganic encapsulation layer and at least one organic encapsulation layer. For example, the thin film encapsulation layer can be provided in a structure in which one organic encapsulation layer is sandwiched between two inorganic encapsulation layers.

[0119] Figures 5 to 14 FIG. 4 is a cross-sectional view schematically illustrating a portion of a process of manufacturing a display apparatus according to an embodiment.

[0120] Referring to Figure 5A lower electrode BE and a lower conductive layer BML are formed on the substrate 100. Each of the lower electrode BE and the lower conductive layer BML can include molybdenum (Mo), aluminum (Al), copper (Cu), or titanium (Ti), and can have a single layer or a multi-layer structure. Each of the lower electrode BE and the lower conductive layer BML can be formed by using any one of various deposition methods such as sputtering, chemical vapor deposition (CVD), or plasma-enhanced vapor deposition (PECVD) and then can be patterned.

[0121] Next, a first insulating layer 111 is formed on the entire surface of the substrate 100 to cover the lower electrode BE and the lower conductive layer BML. The first insulating layer 111 can include an inorganic material such as an oxide or a nitride, an organic material, or a combination of an organic material and an inorganic material, and can have a single layer or a multi-layer structure including an inorganic material and an organic material. In some embodiments, the first insulating layer 111 can be formed of silicon oxide (SiO2), silicon nitride (SiN x ), or silicon oxynitride (SiO x N y ).

[0122] The first insulating layer 111 can be formed by using any one of various deposition methods such as sputtering, chemical vapor deposition (CVD), or plasma-enhanced vapor deposition (PECVD). The thickness t1 of the first insulating layer 111 can be set by considering the length of the channel region of the second thin film transistor. The thickness t1 of the first insulating layer 111 can be several hundreds to several thousands

[0123] Referring Figure 6 After the upper electrode TE is formed on the first insulating layer 111, an opening TEa passing through a central portion of the upper electrode TE and an opening 111OP in the first insulating layer 111 exposing a central portion of the lower electrode BE therethrough are formed.

[0124] The upper electrode TE can be formed on the first insulating layer 111 by using any one of various deposition methods such as sputtering, chemical vapor deposition (CVD), or plasma-enhanced vapor deposition (PECVD) and then can be patterned. The upper electrode TE can be formed to overlap the lower electrode BE.

[0125] Next, an opening OP passing through the central portion of the upper electrode TE and the first insulating layer 111 is formed. The opening TEa of the upper electrode TE and the opening 111OP of the first insulating layer 111 overlap each other. The opening 111OP of the first insulating layer 111 can expose a top surface of the lower electrode BE.

[0126] To form the opening TEa of the upper electrode TE and the opening 111OP of the first insulating layer 111, a photoresist pattern can be formed by a mask process, and a process of etching portions corresponding to the openings can be performed.

[0127] Referring to Figure 7 The first semiconductor layer AO1 and the second semiconductor layer AO2 are formed over the first insulating layer 111. Each of the first semiconductor layer AO1 and the second semiconductor layer AO2 can be formed of an oxide semiconductor, and can be formed by using any of various deposition methods such as sputtering, chemical vapor deposition (CVD), or plasma-enhanced vapor deposition (PECVD) and then can be patterned.

[0128] The first semiconductor layer AO1 can be formed to at least partially overlap with the lower conductive layer BML. The second semiconductor layer AO2 can be positioned in the opening 111OP defined in the first insulating layer 111 to contact the lower electrode BE. The second semiconductor layer AO2 can extend from the inside of the opening 111OP to the top surface of the upper electrode TE. A central portion of the second semiconductor layer AO2 can contact the lower electrode BE, and a peripheral portion of the second semiconductor layer AO2 can contact the upper electrode TE.

[0129] The first semiconductor layer AO1 can be formed substantially parallel to the top surface of the substrate 100 to form a horizontal channel. The second semiconductor layer AO2 can be formed at a certain angle with respect to the top surface of the substrate 100 to form a vertical channel.

[0130] Referring to Figure 8 The second insulating layer 113 is formed over the substrate 100 to cover the first semiconductor layer AO1 and the second semiconductor layer AO2.

[0131] The second insulating layer 113 can be formed of an inorganic insulating material, and can be formed by using any of various deposition methods such as sputtering, chemical vapor deposition (CVD), or plasma-enhanced vapor deposition (PECVD). The thickness t2 of the second insulating layer 113 can be smaller than the thickness t1 of the first insulating layer 111. The thickness t2 of the second insulating layer 113 can be determined so that a portion of the second insulating layer 113 is positioned in the opening 111OP of the first insulating layer 111.

[0132] Next, the first gate electrode GE1 and the second gate electrode GE2 are formed over the second insulating layer 113. Each of the first gate electrode GE1 and the second gate electrode GE2 can be formed of a conductive material, and can be formed by using any of various deposition methods such as sputtering, chemical vapor deposition (CVD), or plasma-enhanced vapor deposition (PECVD) and then can be patterned.

[0133] The first gate electrode GE1 can be formed to overlap with a central portion of the first semiconductor layer AO1. The second gate electrode GE2 can overlap with a central portion of the second semiconductor layer AO2, and can be formed so that at least a portion of the second gate electrode GE2 is positioned in the opening 111OP of the first insulating layer 111.

[0134] A portion of the first semiconductor layer AO1 that does not overlap with the first gate electrode GE1 can be a source region or a drain region. A portion of the second semiconductor layer AO2 that does not overlap with the second gate electrode GE2 can be a source region or a drain region. In addition, a portion of the second semiconductor layer AO2 that directly contacts the lower electrode BE can be a source region or a drain region. The source region or the drain region can be a region that is made to be conductive by increasing a carrier concentration in an oxide semiconductor. The source region and the drain region of the first semiconductor layer AO1 and the second semiconductor layer AO2 can be adjusted by plasma treatment. The plasma treatment can be performed by using a hydrogen (H) based gas, a fluorine (F) based gas, nitrogen, or a combination thereof.

[0135] Hydrogen gas (H2) can penetrate into an oxide semiconductor in a thickness direction to increase a carrier concentration and reduce a surface resistance. In addition, when plasma treatment is performed by using hydrogen gas, oxygen can be removed from a surface and a metal oxide can be reduced to reduce a surface resistance.

[0136] When plasma treatment is performed by using an F based gas, an F component can increase on a surface of an oxide semiconductor, and an oxygen component can be relatively reduced, thereby forming an additional carrier on the surface. Accordingly, a carrier concentration can increase and a surface resistance can decrease. The F based gas can be, but is not limited to, CF4, C4F8, NF3, SF6, or a combination thereof.

[0137] When plasma treatment is performed by using nitrogen, annealing can be simultaneously performed. In some embodiments, the annealing can be performed at a temperature of about 300°C to about 400°C for about 1 hour to 2 hours.

[0138] Referring to Figure 9 A third insulating layer 115 is formed on the entire surface of the substrate 100 to cover the first gate electrode GE1 and the second gate electrode GE2. The third insulating layer 115 can be formed of an inorganic insulating material, and can be formed by using any one of various deposition methods such as sputtering, chemical vapor deposition (CVD), or plasma enhanced vapor deposition (PECVD).

[0139] Next, a first contact hole CNT1 is formed through the third insulating layer 115, the second insulating layer 113, and the first insulating layer 111. The first contact hole CNT1 can overlap the lower conductive layer BML and can expose a top surface of the lower conductive layer BML. The first contact hole CNT1 can be provided to expose a side surface of the first semiconductor layer AO1 positioned on the first insulating layer 111. Alternatively, unlike this, the first contact hole CNT1 can be provided to pass through the first semiconductor layer AO1. To form the first contact hole CNT1, a photoresist pattern can be formed by a mask process, and a process of etching a portion corresponding to the first contact hole CNT1 can be performed.

[0140] Referring to Figure 10 A second electrode EE2 can be formed on the third insulating layer 115. The second electrode EE2 can be connected to the lower conductive layer BML and the first semiconductor layer AO1 through the first contact hole CNT1. The second electrode EE2 can be formed of a conductive material and can be formed by using any one of various deposition methods such as sputtering, chemical vapor deposition (CVD), or plasma-enhanced vapor deposition (PECVD) and then can be patterned.

[0141] Next, a fourth insulating layer 117 can be formed on the entire surface of the substrate 100 to cover the second electrode EE2. The fourth insulating layer 117 can be formed of an inorganic insulating material and can be formed by using any one of various deposition methods such as sputtering, chemical vapor deposition (CVD), or plasma-enhanced vapor deposition (PECVD).

[0142] Next, a second contact hole CNT2 and CNT2' can be formed through the fourth insulating layer 117, the third insulating layer 115, and the second insulating layer 113. To form the second contact holes CNT2 and CNT2', a photoresist pattern can be formed by a mask process, and a process of etching a portion corresponding to the second contact holes CNT2 and CNT2' can be performed. The second contact hole CNT2 can expose a top surface of the first semiconductor layer AO1. The second contact hole CNT2' can expose a top surface of the upper electrode TE.

[0143] Referring to Figure 11 A first wiring WL1 and a first electrode EE1 can be formed on the fourth insulating layer 117. The first wiring WL1 can be connected to the upper electrode TE through the second contact hole CNT2'. The first electrode EE1 can be connected to the first semiconductor layer AO1 through the second contact hole CNT2. Each of the first wiring WL1 and the first electrode EE1 can be formed of a conductive material and can be formed by using any one of various deposition methods such as sputtering, chemical vapor deposition (CVD), or plasma-enhanced vapor deposition (PECVD) and then can be patterned.

[0144] Referring to Figure 12The fifth insulating layer 119 can be formed to cover the first wiring WL1 and the first electrode EE1. The fifth insulating layer 119 can be formed of an inorganic insulating material, and can be formed by using any one of various deposition methods such as sputtering, chemical vapor deposition (CVD), or plasma-enhanced vapor deposition (PECVD).

[0145] Next, a third contact hole CNT3 passing through the fifth insulating layer 119, the fourth insulating layer 117, the third insulating layer 115, and the second insulating layer 113 and a third contact hole CNT3' passing through the fifth insulating layer 119 and the fourth insulating layer 117 can be formed. To form the third contact holes CNT3 and CNT3', a photoresist pattern can be formed by a mask process, and a process of etching portions corresponding to the third contact holes CNT3 and CNT3' can be performed. The third contact hole CNT3 can expose a top surface of the upper electrode TE. The third contact hole CNT3' can expose a top surface of the second electrode EE2.

[0146] Referring to Figure 13 A second wiring WL2 and a connection electrode CM can be formed on the fifth insulating layer 119. The second wiring WL2 can be connected to the upper electrode TE through the third contact hole CNT3. The connection electrode CM can be connected to the second electrode EE2 through the third contact hole CNT3'. Each of the second wiring WL2 and the connection electrode CM can be formed of a conductive material, and can be formed by using any one of various deposition methods such as sputtering, chemical vapor deposition (CVD), or plasma-enhanced vapor deposition (PECVD) and then can be patterned.

[0147] Referring to Figure 14 A sixth insulating layer 123 can be formed to cover the second wiring WL2 and the connection electrode CM. The sixth insulating layer 123 can include a via hole VH extending to the connection electrode CM. The sixth insulating layer 123 can be formed of an organic insulating material, and can be formed by applying, developing, and curing the organic insulating material.

[0148] Next, a pixel electrode 310 can be formed on the sixth insulating layer 123. The pixel electrode 310 can be formed of a conductive material, and can be formed by using any one of various deposition methods and then can be patterned.

[0149] Next, a display apparatus can be completed by performing subsequent processes according to the type of a light emitting element.

[0150] In the method of manufacturing a display apparatus according to an embodiment, since the first gate electrode GE1 of the first thin film transistor TFT1 which is a horizontal type transistor and the second gate electrode GE2 of the second thin film transistor TFT2 which is a vertical type transistor can be formed at the same time in the same process, a display apparatus that minimizes process costs and has a high degree of integration can be provided.

[0151] Figure 15 is a cross-sectional view schematically showing a display device according to an embodiment. In Figure 15 Figure 4

[0152] Referring to Figure 15 In the display device according to the embodiment, a pixel circuit PC can be positioned on the substrate 100, and an organic light emitting diode OLED can be positioned as a light emitting element connected to the pixel circuit PC.

[0153] The pixel circuit PC according to the present embodiment includes a first thin film transistor TFT1 as a horizontal type transistor and a second thin film transistor TFT2 as a vertical type transistor.

[0154] In the present embodiment, the pixel circuit PC can further include a storage capacitor Cst. The storage capacitor Cst can include a first capacitor electrode CE1 and a second capacitor electrode CE2, and a third insulating layer 115 can be positioned between the first capacitor electrode CE1 and the second capacitor electrode CE2.

[0155] The first capacitor electrode CE1 can be formed in the same layer as the first gate electrode GE1 of the first thin film transistor TFT1 and the second gate electrode GE2 of the second thin film transistor TFT2 by the same material.

[0156] The first capacitor electrode CE1 can be positioned on the second insulating layer 113.

[0157] The second capacitor electrode CE2 can be formed in the same layer as the second electrode EE2 of the first thin film transistor TFT1 by the same material. The second capacitor electrode CE2 can be positioned on the third insulating layer 115.

[0158] Figure 16 and Figure 17 is a cross-sectional view schematically showing a display device according to an embodiment. In Figure 16 and Figure 17 Figure 4

[0159] Referring to Figure 16 and Figure 17 In the display device according to the embodiment, a pixel circuit PC can be positioned on the substrate 100, and an organic light emitting diode OLED can be positioned as a light emitting element connected to the pixel circuit PC.

[0160] ​​​​The pixel circuit PC according to the present embodiment can include a first thin film transistor TFT1 as a horizontal transistor and a second thin film transistor TFT2 as a vertical transistor. Each of the first thin film transistor TFT1 and the second thin film transistor TFT2 can be a transistor including an oxide semiconductor.

[0161] With reference to Figure 16 and Figure 17 , the pixel circuit PC can further include a third thin film transistor TFT3.

[0162] The third thin film transistor TFT3 can be a transistor including a silicon semiconductor. The third thin film transistor TFT3 can include a third semiconductor layer AS3 including a silicon semiconductor and a third gate electrode GE3 insulated from the third semiconductor layer AS3. The third thin film transistor TFT3 can include a source electrode SE3 and a drain electrode DE3.

[0163] When the third thin film transistor TFT3 is included, a buffer layer 101 and a gate insulating layer 103 can also be provided on the substrate 100.

[0164] The buffer layer 101 can be positioned on the substrate 100 and can reduce or prevent penetration of foreign matter, moisture, or external air from the bottom of the substrate 100 and can planarize the substrate 100. The buffer layer 101 can include an inorganic material such as an oxide or a nitride, an organic material, or a combination of an organic material and an inorganic material, and can have a single-layer or multi-layer structure including an inorganic material and an organic material. In some embodiments, the buffer layer 101 can be formed of silicon oxide (SiO2), silicon nitride (SiN x ), or silicon oxynitride (SiO x N y ).

[0165] The third semiconductor layer AS3 including a silicon semiconductor can be positioned on the buffer layer 101, and the third semiconductor layer AS3 can include polycrystalline silicon or amorphous silicon. The third semiconductor layer AS3 can include a channel region and source and drain regions doped with impurities.

[0166] The gate insulating layer 103 can be provided to cover the third semiconductor layer AS3. The gate insulating layer 103 can include an inorganic insulating material such as silicon oxide (SiO2), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), aluminum oxide (Al2O3), or titanium oxide (TiO2). The gate insulating layer 103 can have a single-layer or multi-layer structure including an inorganic insulating material.

[0167] A third gate electrode GE3 is positioned on the gate insulating layer 103 to overlap the third semiconductor layer AS3. The third gate electrode GE3 can be formed in the same layer as the lower conductive layer BML and the lower electrode BE of the second thin film transistor TFT2, from the same material. The first insulating layer 111, the second insulating layer 113, and the third insulating layer 115 can be positioned on the third gate electrode GE3.

[0168] The source electrode SE3 and the drain electrode DE3 can be formed in the same layer as the second electrode EE2 of the first thin film transistor TFT1, from the same material. The source electrode SE3 and the drain electrode DE3 can be positioned on the third insulating layer 115.

[0169] When provided with the third thin film transistor TFT3, as shown in Figure 16 , the third thin film transistor TFT3 can not be directly connected to the pixel electrode 310. Alternatively, as shown in Figure 17 , the third thin film transistor TFT3 can be directly connected to the pixel electrode 310.

[0170] In some embodiments, since the third thin film transistor TFT3 includes polycrystalline silicon having excellent reliability, the third thin film transistor TFT3 can be provided as a drive thin film transistor. In this case, the first thin film transistor TFT1 and the second thin film transistor TFT2 can be used as switching transistors. However, the present disclosure is not limited thereto. Various modifications can be made. For example, the second thin film transistor TFT2, which is a vertical thin film transistor, can be used as a drive thin film transistor.

[0171] Figure 18 is a plan view schematically showing a portion of a display apparatus according to an embodiment. Figure 19 is a plan view schematically showing a comparative example with respect to Figure 18 embodiments. In detail, Figure 18 a portion II of Figure 1 is shown as a peripheral region.

[0172] Referring to Figure 18 , embodiments can include a built-in drive thin film transistor TFTd provided as a vertical transistor in a peripheral region.

[0173] The built-in drive thin film transistor TFTd can be a transistor that provides a scan signal or an emission control signal. The built-in drive thin film transistor TFTd includes a lower electrode BEd, an upper electrode TEd, a semiconductor layer AOd, and a gate electrode GEd. An edge of the semiconductor layer AOd can contact the upper electrode TEd, and a central portion of the semiconductor layer AOd can contact the lower electrode BEd to form a vertical channel region CHd in the semiconductor layer AOd.

[0174] Since the vertical transistor can generate a current per unit width that is five times that of the horizontal transistor 5, the area of the peripheral region can be reduced by employing the built-in drive thin film transistor TFTd as a vertical transistor.

[0175] Figure 19 An example in which a built-in drive thin film transistor TFTd' as a horizontal transistor is formed is shown. The built-in drive thin film transistor TFTd' includes a gate electrode GE' connected to the lower conductive layer BML' through a contact hole, and includes a semiconductor layer AO' overlapping the gate electrode GE'.

[0176] In order to constitute the built-in drive thin film transistor TFTd' as a horizontal transistor and generate the same amount of current as the Figure 18 five semiconductor layers AO' should be provided in parallel, so that a wide area is required.

[0177] As described above, according to the embodiments, a display device having high reliability, high integration, and capable of displaying a high-quality image by employing both a vertical channel thin film transistor and a horizontal channel thin film transistor can be provided. However, the embodiments are examples and do not limit the effects of the present disclosure.

[0178] It should be understood that the embodiments described herein should be considered in a descriptive sense only and not for purposes of limitation. Descriptions of features or aspects within each embodiment should typically be considered as being applicable to other similar features or aspects in other embodiments. While embodiments have been described with reference to the figures, it will be understood by those skilled in the art that various changes can be made and equivalents can be substituted for elements thereof without departing from the spirit and scope of the disclosure as defined by the appended claims.

Claims

1. A display device, characterized by comprising: Comprising: a substrate; a first thin film transistor positioned on the substrate and including a first semiconductor layer and a first gate electrode; and a second thin film transistor positioned on the substrate and including a second semiconductor layer and a second gate electrode, wherein a first angle between a channel region of the first semiconductor layer and the substrate is different from a second angle between a channel region of the second semiconductor layer and the substrate, and wherein the first gate electrode and the second gate electrode are positioned on the same layer. The first angle is 0° to 5°, and the second angle is 20° to 90°.

2. The display device of claim 1, wherein, Further comprising a lower conductive layer positioned between the substrate and the first semiconductor layer, 3. The display device of claim 1, wherein, wherein the second thin film transistor further includes a lower electrode and an upper electrode, wherein the lower electrode and the lower conductive layer are positioned on the same layer, and wherein the lower electrode of the second thin film transistor is connected to the lower conductive layer. A central portion of the second semiconductor layer is connected to the lower electrode, and a peripheral portion of the second semiconductor layer is connected to the upper electrode.

4. The display device of claim 3, wherein, Further comprising:

5. The display device of claim 3, wherein, a first insulating layer positioned between the lower electrode and the upper electrode, wherein the first insulating layer includes a first opening extending to the lower electrode, and at least a portion of the second semiconductor layer is positioned in the first opening. Further comprising:

6. The display device of claim 5, wherein, a second insulating layer covering the second semiconductor layer, wherein a thickness of the second insulating layer is less than a thickness of the first insulating layer. Further comprising:

7. The display device of claim 1, wherein, a storage capacitor including a first capacitor electrode and a second capacitor electrode, wherein the first capacitor electrode is positioned on the same layer as the first gate electrode and the second gate electrode. Further comprising:

8. The display device of claim 1, wherein, a third thin film transistor positioned on the substrate and including a third semiconductor layer and a third gate electrode, wherein the third gate electrode is positioned above the third semiconductor layer and below a first insulating layer, and the first semiconductor layer is positioned above the first insulating layer. Comprising:

9. A display device, characterized by a substrate; a first insulating layer positioned on the substrate and including a first opening; a first thin film transistor including a first semiconductor layer and a first gate electrode, the first semiconductor layer being positioned on a top surface of the first insulating layer; and a second thin film transistor including a second semiconductor layer positioned at least partially in the first opening, a lower electrode positioned below the first insulating layer, an upper electrode positioned above the first insulating layer, and a second gate electrode positioned on the second semiconductor layer, wherein the first gate electrode and the second gate electrode are positioned on the same layer. An angle between an inner wall of the first opening and a top surface of the substrate is 20° to 90°.

10. The display device of claim 9, wherein, ​

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