Current sampling circuit and test equipment

Abstract

The utility model discloses a current sampling circuit and test equipment, and belongs to the technical field of battery test. The current sampling circuit comprises a voltage sampling circuit, a sampling holding circuit, an analog-to-digital conversion circuit, a processor and a comparison circuit. The voltage sampling circuit is used for collecting equalizing current of the battery pack, converting the equalizing current into sampling voltage and outputting the sampling voltage; the sampling and holding circuit is used for sampling and holding the maximum sampling voltage of the output sampling voltage; the analog-to-digital conversion circuit is used for performing analog-to-digital conversion on the maximum sampling voltage into digital sampling voltage and outputting the digital sampling voltage; the comparison circuit is used for outputting a PWM signal according to the reference voltage provided by the reference voltage end and the sampling voltage; and the processor is used for analyzing relevant parameters of the equalizing current according to the digital sampling voltage and the PWM signal, wherein the relevant parameters at least comprise a duty ratio, a period and a maximum value. The acquisition efficiency of the equalizing current data of the battery pack is effectively improved, and the acquisition error rate is reduced.

Description

Technical Field

[0001] This application belongs to the field of battery testing technology, specifically relating to a current sampling circuit and testing equipment. Background Technology

[0002] Battery packs are indispensable energy storage devices in electric devices such as electric vehicles and electric tricycles. To increase the energy storage capacity of battery packs, current battery packs are typically composed of multiple individual cells (also known as battery cells). Although the consistency of performance such as capacity and charge / discharge current among the multiple individual cells is considered when configuring them, performance differences still exist between the individual cells during actual use.

[0003] Currently, to ensure battery lifespan and safety, battery equalization is performed during use to balance the output voltage and current of individual cells, maintaining overall battery performance. Therefore, functional testing of the configured battery must include testing the battery equalization process. This equalization test includes testing the battery equalization current, which refers to the output current after the equalization process is initiated.

[0004] However, current equalization current testing typically requires manual operation of measuring instruments such as multimeters and oscilloscopes to collect relevant data on the equalization current. This data is then manually entered into a Functional Circuit Test (FCT) device, which calculates parameters such as the current cycle and duty cycle of the equalization current, thus acquiring the equalization current parameters. Clearly, manually collecting battery pack equalization current data suffers from low acquisition efficiency and a high error rate. Utility Model Content

[0005] This application aims to provide a current sampling circuit and testing equipment that can solve the problems of low acquisition efficiency and large error rate in the current method of manually collecting equalization current data of battery packs.

[0006] To solve the above-mentioned technical problems, this application is implemented as follows:

[0007] In a first aspect, embodiments of this application propose a current sampling circuit, including: a voltage sampling circuit, a sample-and-hold circuit, an analog-to-digital converter circuit, a processor, and a comparison circuit;

[0008] The voltage sampling circuit is connected to the battery pack and the sample-and-hold circuit, and is used to collect the equalization current of the battery pack, convert the equalization current into a sampling voltage, and output the sampling voltage.

[0009] The sample-and-hold circuit is connected to the analog-to-digital converter circuit and is used to sample and hold the maximum sample voltage of the output sample voltage.

[0010] The analog-to-digital conversion circuit is also connected to the processor and is used to convert the maximum sampling voltage analog-to-digital to a digital sampling voltage and output the digital sampling voltage.

[0011] The comparison circuit is connected to the voltage sampling circuit and the reference voltage terminal, and is used to output a pulse width modulation (PWM) signal according to the magnitude of the reference voltage provided by the reference voltage terminal and the sampled voltage.

[0012] The processor is used to analyze the relevant parameters of the equalization current based on the digital sampling voltage and the PWM signal. The relevant parameters include at least the duty cycle, period, and maximum value.

[0013] Optionally, the sample-and-hold circuit includes: a first-stage voltage follower, a second-stage voltage follower, a holding capacitor, and a clearing module;

[0014] The first-stage voltage follower is connected to the voltage sampling circuit and the second-stage voltage follower. One end of the holding capacitor is connected to the connection path between the first-stage voltage follower and the second-stage voltage follower. One end of the holding capacitor is also connected to the clearing module. The other end of the holding capacitor is grounded. The clearing module is also connected to the processor.

[0015] The zeroing module is used to control the discharge and reset of the holding capacitor under the control of the processor;

[0016] The first-stage voltage follower, the second-stage voltage follower, and the holding capacitor are used to sample and hold the maximum sampled voltage of the output sampled voltage after the holding capacitor is reset.

[0017] Optionally, the first-stage voltage follower includes: a first operational amplifier, a first diode, a first resistor, and a first capacitor; the input terminal of the first operational amplifier is connected to the voltage sampling circuit through the first resistor, and the output terminal is connected to the second-stage voltage follower; the first diode and the first capacitor are respectively connected to the input terminal and the output terminal of the first operational amplifier.

[0018] The second-level voltage follower includes: a second operational amplifier and a second resistor; the input terminal of the second operational amplifier is connected to the output terminal, one end of the second resistor is connected to the input terminal of the first operational amplifier, and the other end of the second resistor is connected to the output terminal of the second operational amplifier.

[0019] Optionally, the sample-and-hold circuit further includes a low-pass filter; the low-pass filter is connected to the second-stage voltage follower and is used to perform noise filtering on the maximum sampled voltage output by the second-stage voltage follower, and output the processed maximum sampled voltage.

[0020] Optionally, the comparison circuit includes a comparator; the comparator is connected to the voltage sampling circuit and the reference voltage terminal, and is used to output a PWM signal according to the magnitude of the reference voltage and the sampled voltage.

[0021] Optionally, the comparison circuit further includes a third resistor and a fourth resistor; the third resistor is connected to the voltage sampling circuit and the comparator respectively, and the fourth resistor is connected to the reference voltage terminal and the comparator respectively.

[0022] Optionally, the current sampling circuit further includes an anti-interference circuit; the anti-interference circuit is connected to the comparison circuit and the processor, and is used to filter and despiking the PWM signal output by the comparison circuit, and output the processed PWM signal.

[0023] Optionally, the anti-interference circuit includes: a second capacitor and a Schmitt inverter; one end of the second capacitor is connected to the output terminal of the comparator circuit and the input terminal of the Schmitt inverter respectively, the other end of the second capacitor is grounded, and the output terminal of the Schmitt inverter is connected to the processor.

[0024] Optionally, the current sampling circuit further includes a voltage follower; the voltage follower is connected to the sample-and-hold circuit and the analog-to-digital converter circuit respectively, and is used to output the maximum sampled voltage in a voltage-following manner.

[0025] Secondly, embodiments of this application provide a testing device, which includes the current sampling circuit described in any of the first aspects.

[0026] In this embodiment, the equalization current of the battery pack is converted into a sampling voltage by a voltage sampling circuit, so that the sample-and-hold circuit can use and hold the maximum value of the output sampling voltage and output the maximum sampling voltage to the analog-to-digital converter (ADC). Then, the processor obtains the digital sampling voltage after analog-to-digital conversion of the maximum sampling voltage through the ADC, and determines the maximum value of the equalization current based on the analysis of the digital sampling voltage. Furthermore, the comparison circuit can also receive the sampling voltage converted by the voltage sampling circuit, and output a PWM signal after square wave shaping of the sampling voltage based on the reference voltage and the magnitude of the sampling voltage. This allows the processor to determine parameters such as the period and duty cycle of the equalization current by analyzing the period and duty cycle of the PWM signal. In this technical solution, the current acquisition circuit can be used to automatically acquire relevant parameters of the equalization current of the battery pack to obtain the equalization current data of the battery pack. Compared with the manual acquisition method in related technologies, this can effectively improve the acquisition efficiency of the equalization current data of the battery pack and reduce the acquisition error rate.

[0027] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description

[0028] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which:

[0029] Figure 1 This is a schematic diagram of the structure of a current sampling circuit provided in an embodiment of this application;

[0030] Figure 2 This is a schematic diagram of a sample-and-hold circuit provided in an embodiment of this application;

[0031] Figure 3 This is a schematic diagram of another sample-and-hold circuit provided in an embodiment of this application;

[0032] Figure 4 This is a schematic diagram of another current sampling circuit provided in an embodiment of this application. Detailed Implementation

[0033] The embodiments of this application will now be described in detail. Examples of these embodiments are illustrated in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0034] The terms "first" and "second" in the specification and claims of this application may explicitly or implicitly include one or more of the features. In the description of this application, unless otherwise stated, "multiple" means two or more. Furthermore, "and / or" in the specification and claims indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0035] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection between two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0036] Please refer to Figure 1 The diagram illustrates a schematic representation of a current sampling circuit provided in an embodiment of this application. Figure 1 As shown, the current sampling circuit 1 includes: a voltage sampling circuit 101, a sample and hold circuit 102, an analog-to-digital conversion circuit 103, a processor 104, and a comparator circuit 105.

[0037] The voltage sampling circuit 101 is connected to the battery pack and the sample-and-hold circuit 102. The voltage sampling circuit 101 is used to acquire the equalization current Ib of the battery pack, convert the equalization current Ib into a sampled voltage Vb, and output it.

[0038] The sample-and-hold circuit 102 is connected to the analog-to-digital converter circuit 103. The sample-and-hold circuit 102 is used to acquire the maximum sample voltage of the sample voltage Vb and hold the maximum output sample voltage to the analog-to-digital converter circuit 103.

[0039] The analog-to-digital converter (ADC) circuit 103 is also connected to the processor 104. The ADC circuit 103 converts the maximum sampling voltage analog-to-digital into a digital sampling voltage and outputs the digital sampling voltage to the processor 104. Optionally, the ADC circuit 103 may include an analog-to-digital converter (ADC). The ADC can be used to determine the data voltage corresponding to the maximum sampling voltage based on the relationship between the maximum sampling voltage and multiple quantization levels (i.e., grades) corresponding to the analog voltage range in the ADC, thereby obtaining the digital sampling voltage and realizing circuit digitization. The data voltage corresponding to the maximum sampling voltage is the data voltage corresponding to the target quantization level, which is the quantization level corresponding to the analog voltage range where the maximum sampling voltage is located.

[0040] Comparator circuit 105 is connected to voltage sampling circuit 101 and reference voltage terminal VEQ. Comparator circuit 105 outputs a pulse width modulation (PWM) signal based on the reference voltage provided by reference voltage terminal VEQ and the sampled voltage. Specifically, by adjusting the magnitude of the reference voltage provided by reference voltage terminal VEQ, comparator circuit 105 can perform square wave rectification on the sampled voltage according to the magnitudes of the reference voltage and the sampled voltage to output the rectified PWM signal. Optionally, the magnitude of the reference voltage can be 0.5 times the sampled voltage.

[0041] Processor 104 is used to analyze relevant parameters of the equalization current Ib based on the digitally sampled voltage and PWM signal. These relevant parameters include at least the duty cycle, period, and maximum value. Optionally, processor 104 can be a microcontroller unit (MCU) or a digital signal processor (DSP).

[0042] Optionally, the processor 104 can be used to convert the digital sampling voltage output by the analog-to-digital converter 103 into an analog sampling voltage.

[0043] Since the sample-and-hold circuit 102 always holds the maximum sampled voltage of the output sampled voltage Vb, the processor 104 determines the analog sampled voltage obtained by inverting the digital sampled voltage as the maximum value of the sampled voltage Vb. This maximum value of the sampled voltage Vb indicates the maximum value (peak value) of the equalization current Ib. The processor 104 can directly determine that the value of the analog sampled voltage is the maximum value of the equalization current Ib. Optionally, the processor 104 can further convert the analog sampled voltage obtained by inverting the digital sampled voltage into a sampled current value to obtain the maximum value of the equalization current Ib.

[0044] Optionally, the processor 104 is further configured to indirectly measure the duty cycle and period of the equalization current Ib based on the PWM signal via an input capture function. The input capture function enables the processor 104 to capture the timer's count value when a specific event (such as the rising or falling edge of the PWM signal) occurs, and then calculate the period and duty cycle of the PWM signal by capturing the count values ​​of two key events (such as the start and end of one signal cycle of the PWM signal).

[0045] Specifically, the processor 104 can optionally be used to calculate the period of the PWM signal by capturing the count values ​​at two edges (e.g., from the rising edge to the next rising edge) of one signal cycle of the PWM signal through a capture timer, and determine the period of the PWM signal as the period of the balancing current Ib. The period T satisfies: T = (x1 - x2) × T0 ÷ k. x1 represents the count value captured in the second capture. x2 represents the count value captured in the first capture. T0 represents the clock period of the timer. k represents the prescaler factor, i.e., the division coefficient of the timer clock source.

[0046] The processor 104 is also used to calculate the count value corresponding to the high-level duration of the PWM signal by capturing the count values ​​at adjacent rising and falling edges of the PWM signal using a timer, and then calculate the duty cycle of the PWM signal, determining the duty cycle of the PWM signal as the duty cycle of the balancing current Ib. The duty cycle C of the PWM signal satisfies: C = (x3 ÷ x4) × 100%. x3 represents the count value corresponding to the high-level duration. x4 represents the timer count value corresponding to the period of the PWM signal, i.e., x1 - x2.

[0047] In this embodiment, the equalization current of the battery pack is converted into a sampling voltage by a voltage sampling circuit, so that the sample-and-hold circuit can use and hold the maximum value of the output sampling voltage and output the maximum sampling voltage to the analog-to-digital converter (ADC). Then, the processor obtains the digital sampling voltage after analog-to-digital conversion of the maximum sampling voltage through the ADC, and determines the maximum value of the equalization current based on the analysis of the digital sampling voltage. Furthermore, the comparison circuit can also receive the sampling voltage converted by the voltage sampling circuit, and output a PWM signal after square wave shaping of the sampling voltage based on the reference voltage and the magnitude of the sampling voltage. This allows the processor to determine parameters such as the period and duty cycle of the equalization current by analyzing the period and duty cycle of the PWM signal. In this technical solution, the current acquisition circuit can be used to automatically acquire relevant parameters of the equalization current of the battery pack to obtain the equalization current data of the battery pack. Compared with the manual acquisition method in related technologies, this can effectively improve the acquisition efficiency of the equalization current data of the battery pack and reduce the acquisition error rate.

[0048] In this embodiment of the application, the voltage sampling circuit 101 is used to collect the equalization current Ib of the battery pack, convert the equalization current Ib into a sampling voltage Vb, and output the sampling voltage Vb.

[0049] Optionally, such as Figure 1As shown, the voltage sampling circuit 101 may include a sampling resistor Ri. One end of the sampling resistor Ri is connected to the battery pack, the sample-and-hold circuit 102, and the comparator circuit 105, and the other end of the sampling resistor Ri is grounded. The sampling resistor Ri is used to convert the equalization current Ib of the battery pack into a sampling voltage Vb according to its resistance value, and outputs the sampling voltage Vb to the sample-and-hold circuit 102 and the comparator circuit 105.

[0050] For example, the current output terminal AFE_B_C of the battery pack is used to provide the equalizing current Ib. One end of the sampling resistor Ri can be connected to the current output terminal AFE_B_C, the sample-and-hold circuit 102, and the comparator circuit 105, while the other end of the sampling resistor Ri is grounded.

[0051] In this embodiment, the sample-and-hold circuit 102 is used to acquire the maximum sample voltage of the sample voltage Vb and hold the maximum sample voltage output to the analog-to-digital converter circuit 103 and the processor 104.

[0052] Optionally, such as Figure 2 As shown, the sample-and-hold circuit 102 may include: a first-stage voltage follower 1021, a second-stage voltage follower 1022, a holding capacitor Ck, and a clearing module 1023.

[0053] The first-stage voltage follower 1021 is connected to the voltage sampling circuit 101 and the second-stage voltage follower 1022. One end of the holding capacitor Ck is connected to the connection path between the first-stage voltage follower 1021 and the second-stage voltage follower 1022. One end of the holding capacitor Ck is also connected to the reset module 1023, and the other end of the holding capacitor Ck is grounded. The reset module 1023 is also connected to the processor 104.

[0054] The reset module 1022 is used to control the discharge and reset of the holding capacitor Ck under the control of the processor 104. The first-stage voltage follower 1021, the second-stage voltage follower 1022, and the holding capacitor Ck are used to sample and hold the maximum sampling voltage of the output sampling voltage Vb after the holding capacitor Ck is reset, based on the capacitance storage charge characteristics of the holding capacitor Ck.

[0055] Further optional, please refer to Figure 3The first-stage voltage follower 1021 includes: a first operational amplifier U1, a first diode D1, a first resistor R1, and a first capacitor C1. The input terminal of the first operational amplifier U1 is connected to the voltage sampling circuit 101 through the first resistor R1. The output terminal of the first operational amplifier U1 is connected to the second-stage voltage follower 1022. The first diode D1 and the first capacitor C1 are respectively connected to the input terminal and the output terminal of the first operational amplifier U1. That is, one end of the first diode D1 is connected to the input terminal of the first operational amplifier U1, and the other end of the first diode D1 is connected to the output terminal of the first operational amplifier U1. One end of the first capacitor C1 is connected to the input terminal of the first operational amplifier U1, and the other end of the first capacitor C1 is connected to the output terminal of the first operational amplifier U1.

[0056] In this design, the first capacitor C1 serves as a compensation capacitor to improve the stability of the output signal of the first operational amplifier U1. The first diode D1 is used to accelerate the response speed of the first operational amplifier, thereby increasing the charging speed of the holding capacitor Ck. The first-stage voltage follower 1021 is used to provide a voltage follower output for the sampled voltage Vb, outputting a first-stage output voltage equal to the sampled voltage Vb to the holding capacitor Ck. The holding capacitor Ck stores charge under the action of the first-stage output voltage to maintain the maximum sampling voltage of the output sampled voltage Vb.

[0057] The second-stage voltage follower 1022 includes a second operational amplifier U2 and a second resistor R2. The input terminal of the second operational amplifier U2 is connected to its output terminal. One end of the second resistor R2 is connected to the input terminal of the first operational amplifier U1, and the other end is connected to the output terminal of the second operational amplifier U2. The second-stage voltage follower 1022 is used to receive the maximum value of the first-stage output voltage (i.e., the maximum value of the sampled voltage Vb) through the holding capacitor Ck, and outputs the maximum sampled voltage to the analog-to-digital converter circuit 103.

[0058] In an alternative case, such as Figure 2 As shown, the sample-and-hold circuit 102 further includes an anti-reverse element 1024. The anti-reverse element 1024 is connected to both the first-stage voltage follower 1021 and the holding capacitor Ck. The anti-reverse element 1024 is used to prevent the holding capacitor Ck from discharging into the first-stage voltage follower 1021. Optionally, the anti-reverse element 1024 includes a second diode D2. The anode of the second diode D2 is connected to the first-stage voltage follower 1021, and the cathode of the second diode D2 is connected to the holding capacitor Ck.

[0059] For example, such as Figure 3As shown, the positive input terminal of the first operational amplifier U1 can be connected to the voltage sampling circuit 101 through the first resistor R1. The inverting input terminal of the first operational amplifier U1 can be connected to one end of the first capacitor C1 and the anode of the first diode D1. The output terminal of the first operational amplifier U1 is connected to the other end of the first capacitor C1, the cathode of the first diode D1, and the anode of the second diode D2. The cathode of the second diode D2 is connected to one end of the holding capacitor Ck, and the other end of the holding capacitor Ck is grounded. The positive power supply terminal of the first operational amplifier U1 is connected to the positive power supply terminal and one end of the third capacitor C3, and the other end of the third capacitor C3 is grounded. The positive power supply terminal is used to provide a 12V voltage. The negative power supply terminal of the first operational amplifier U1 is connected to the negative power supply terminal and one end of the fourth capacitor C4, and the other end of the fourth capacitor C4 is grounded. The negative power supply terminal is used to provide a -12V voltage.

[0060] As a further example, such as Figure 3 As shown, one end of the second resistor R2 is connected to the inverting input terminal of the first operational amplifier U1, and the other end of the second resistor R2 is connected to the output terminal of the second operational amplifier U2. The non-inverting input terminal of the second operational amplifier U2 is connected to the holding capacitor Ck. The inverting input terminal of the second operational amplifier U2 is connected to its output terminal.

[0061] Optionally, such as Figure 2 As shown, the sample-and-hold circuit 102 also includes a low-pass filter 1025. The low-pass filter 1025 is connected to the second-stage voltage follower 1022. The low-pass filter 1025 is used to filter out noise from the maximum sampled voltage output by the second-stage voltage follower 1022, and outputs the processed maximum sampled voltage Vo.

[0062] Further optional, such as Figure 3 As shown, the low-pass filter 1025 includes a fifth capacitor C5 and a fifth resistor R5. The fifth resistor R5 is connected to one end of the second-stage voltage follower 1022 and one end of the fifth capacitor C5, while the other end of the fifth capacitor C5 is grounded. The fifth capacitor C5 and the fifth resistor R5 are used to perform noise filtering on the maximum sampling voltage output by the second-stage voltage follower 1022, resulting in a processed maximum sampling voltage Vo.

[0063] In some embodiments, please refer to Figure 3 The reset module 1023 includes a sixth resistor R6 and a switch module. One end of the sixth resistor R6 is connected to the holding capacitor Ck, and the other end of the sixth resistor R6 is grounded through the switch module.

[0064] The switching module is connected to the processor 104 and is used to control whether the holding capacitor Ck is grounded under the control of the processor 104. The processor 104 controls the switching module to close or open. When closed, the switching module controls the holding capacitor Ck to be grounded through the sixth resistor R6 to release the charge stored in the holding capacitor Ck, release the voltage of the holding capacitor Ck, and achieve discharge and reset of the holding capacitor Ck. When open, the switching module controls the holding capacitor Ck to disconnect from ground. Thus, before the current sampling circuit begins to collect equalization current data, the switching module first enters the closed state to control the holding capacitor Ck to discharge to ground, thereby resetting the sampling and holding circuit. Then, it enters the open state to control the holding capacitor Ck to disconnect from ground, and the current sampling circuit begins to collect equalization current data.

[0065] Optionally, such as Figure 3 As shown, the switching module includes: a magnetic switch RY1, a third diode D3, a switching transistor Q1, and a seventh resistor R7. The magnetic switch RY1 includes an electromagnet and a braking block. One end of the braking block is connected to the sixth resistor R6, and the other end is grounded. One end of the electromagnet is grounded, and the other end is connected to the power supply terminal through the switching transistor Q1, which provides the power supply voltage. The third diode D3 is connected in parallel with the electromagnet.

[0066] The control terminal of the switching transistor Q1 is connected to the control signal terminal via the seventh resistor R7. The control signal terminal is connected to the processor 104. The control signal terminal receives the on or off signals output by the processor 104. The on signal controls the switching transistor Q1 to conduct, connecting the electromagnet to the power supply terminal, causing the electromagnet to be energized and generate a magnetic field, attracting the brake block to close, thereby grounding the holding capacitor Ck. The off signal controls the switching transistor Q1 to disconnect the electromagnet from the power supply terminal, de-energizing the electromagnet, disengaging the brake block, and thus grounding the holding capacitor Ck.

[0067] For example, the switching transistor Q1 is a PMOS transistor. The source of the switching transistor Q1 is connected to the power supply terminal, which provides a +12V power supply voltage. The gate of the switching transistor Q1 is connected to the control signal terminal, used to receive the turn-on or turn-off signal provided by the control signal terminal. The drain of the switching transistor Q1 is grounded through an electromagnet, and the drain of the switching transistor Q1 is also connected to the cathode of the third diode D3, the anode of the third diode D3 is grounded.

[0068] Thus, before the current sampling circuit begins acquiring equalization current data, the control signal terminal outputs a turn-on signal. Upon receiving the turn-on signal, switch Q1 turns on, connecting the electromagnet to the power supply terminal, closing the brake block, and resetting the holding capacitor Ck to ground. Afterward, the control signal terminal outputs a turn-off signal. Switch Q1 receives the turn-off signal and turns off, disconnecting the electromagnet from the power supply terminal, opening the brake block, disconnecting the holding capacitor Ck from ground, and the current sampling circuit begins acquiring equalization current data.

[0069] In some embodiments, such as Figure 4 As shown, the current sampling circuit 1 further includes an eighth resistor R8. The sample-and-hold circuit 102 is also connected to the voltage sampling circuit 101 through the eighth resistor R8. The eighth resistor R8 is used to limit the current flowing into the sample-and-hold circuit 102, that is, the eighth resistor R8 is used to provide current limiting for the sample-and-hold circuit 102, protecting the sample-and-hold circuit 102. Based on this, the sample-and-hold circuit 102 can be used to receive the first test voltage V1 after the sampling voltage Vb passes through the eighth resistor R8, sample the maximum sampling voltage of the first test voltage V1, and hold the first test voltage V1 output to the analog-to-digital converter circuit 103 and the processor 104.

[0070] In this embodiment, the comparator circuit 105 outputs a PWM signal based on the reference voltage provided by the reference voltage terminal VEQ and the sampled voltage. Since the rising and falling slopes of the battery pack's balancing current are both small, making it inconvenient to sample the duty cycle, the comparator circuit 105 shapes the balancing current into a PWM signal with larger rising and falling slopes, so that the processor 104 can sample the duty cycle of the balancing current and improve sampling efficiency.

[0071] Optionally, such as Figure 4 As shown, the comparator circuit 105 includes a comparator OP1. The comparator OP1 is connected to the voltage sampling circuit 101 and the reference voltage terminal VEQ. The comparator OP1 outputs a PWM signal based on the magnitudes of the reference voltage and the sampled voltage.

[0072] In an optional configuration, comparator OP1 is used to directly compare the magnitudes of the reference voltage and the sampled voltage, and outputs a PWM signal based on the comparison result. For example, the inverting input of comparator OP1 is connected to the voltage sampling circuit 101, and the non-inverting input of comparator OP1 is connected to the reference voltage terminal VEQ. Comparator OP1 compares the magnitudes of the reference voltage and the sampled voltage; when the sampled voltage is greater than the reference voltage, it outputs a low-level signal; when the sampled voltage is less than the reference voltage, it outputs a high-level signal to output the PWM signal.

[0073] In another alternative scenario, please refer to [link / reference]. Figure 4The comparator circuit 105 further includes a third resistor R3 and a fourth resistor R4. The third resistor R3 is connected to both the voltage sampling circuit 101 and the comparator OP1. The fourth resistor R4 is connected to both the reference voltage terminal VEQ and the comparator OP1. The comparator OP1 receives the second test voltage V2 after the sampled voltage Vb passes through the third resistor R3, and receives the input reference voltage Veq after the reference voltage passes through the fourth resistor R4. The comparator OP1 compares the magnitudes of the second test voltage V2 and the input reference voltage Veq, and outputs a PWM signal based on the comparison result.

[0074] For example, the inverting input of comparator OP1 is connected to the voltage sampling circuit 101 through the third resistor R3, and the non-inverting input of comparator OP1 is connected to the reference voltage terminal VEQ through the fourth resistor R4. Comparator OP1 is used to compare the magnitude of the input reference voltage Veq and the second test voltage V2. When the second test voltage V2 is greater than the input reference voltage Veq, it outputs a low-level signal; when the second test voltage V2 is less than the input reference voltage Veq, it outputs a high-level signal to output a PWM signal. The input reference voltage Veq can be 0.5 times the second test voltage V2.

[0075] Further optional, such as Figure 1 As shown, the current sampling circuit 1 further includes an anti-interference circuit 106. The anti-interference circuit 106 is connected to the comparator circuit 105 and the processor 104. The anti-interference circuit 106 is used to filter and smooth the PWM signal output by the comparator circuit 105, and output the processed PWM signal.

[0076] Optionally, such as Figure 4 As shown, the anti-interference circuit 106 includes a second capacitor C2 and a Schmitt inverter CR1. One end of the second capacitor C2 is connected to both the output of the comparator circuit 105 and the input of the Schmitt inverter CR1. The other end of the second capacitor C2 is grounded. The output of the Schmitt inverter CR1 is connected to the processor 104. For example, as... Figure 4 As shown, one end of the second capacitor C2 can be connected to the output of comparator OP1 and the input of Schmitt inverter CR1 respectively, and the other end of the second capacitor C2 is grounded.

[0077] In some embodiments of this application, such as Figure 1 As shown, the current sampling circuit 1 further includes a voltage follower 107. The voltage follower 107 is connected to the sample-and-hold circuit 102 and the analog-to-digital converter circuit 103, respectively. The voltage follower 107 is used to output a voltage follower of the maximum sampled voltage to improve the signal stability of the maximum sampled voltage and facilitate sampling by the analog-to-digital converter circuit 103.

[0078] Optionally, such as Figure 4As shown, the voltage follower 107 includes a third operational amplifier OP2. The positive input of the third operational amplifier OP2 is connected to the sample-and-hold circuit 102. The inverting input of the third operational amplifier OP2 is connected to its output. The output of the third operational amplifier OP2 is also connected to the analog-to-digital converter circuit 103. The third operational amplifier OP2 is used to provide a voltage follower output for the maximum sampled voltage, thereby improving the signal stability of the maximum sampled voltage and facilitating sampling by the analog-to-digital converter circuit 103.

[0079] For ease of understanding, the following will be used as... Figure 4 The current sampling circuit shown further illustrates the principle of the circuit in this application. For example... Figure 4 As shown, in the current sampling circuit 1, one end of the sampling resistor Ri is connected to the current output terminal AFE_B_C of the battery pack and the eighth resistor R8 and the third resistor R3, respectively. The other end of the sampling resistor Ri is grounded. The eighth resistor R8 is also connected in sequence to the sample-and-hold circuit 102, the voltage follower 107, the ADC 103, and the processor 104. The sample-and-hold circuit 102 is also directly connected to the processor 104. The third resistor R3 is also connected to the comparator OP1. The third resistor R3 is connected to the reference voltage terminal VEQ and the comparator OP1, respectively. The comparator OP1 is also connected to one end of the second capacitor C2 and the input terminal of the Schmitt inverter CR1, respectively. The other end of the second capacitor C2 is grounded. The output terminal of the Schmitt inverter CR1 is connected to the processor 104.

[0080] In this circuit, before the current sampling circuit 1 begins sampling the equalization current data, the processor 104 controls the sample-and-hold circuit 102 to discharge and reset the holding capacitor, in preparation for sampling the equalization current data. The current sampling circuit 1 begins sampling the equalization current data. The equalization current Ib of the battery pack generates a first test voltage V1 after passing through the sampling resistor Ri and the eighth resistor R8. The sample-and-hold circuit 102 samples the first test voltage V1 and holds the maximum value of the first test voltage V1. The maximum value of the first test voltage V1 is converted from analog to digital by the ADC 103 and then output to the processor 104. The processor 104 then performs an inverse conversion on the maximum value of the first test voltage V1 to obtain an analog sampling voltage. The processor 104 determines the maximum value of the equalization current Ib as the value of the analog sampling voltage.

[0081] Furthermore, the equalizing current Ib of the square wave is fed through the sampling resistor Ri and the third resistor R3 to generate the second test voltage V2. The reference voltage provided by the reference voltage terminal VEQ is fed through the fourth resistor R4 to generate the input reference voltage Viq. Comparator OP1 compares the second test voltage V2 with the input reference voltage Viq. If the second test voltage V2 is greater than the input reference voltage Viq, it outputs a low-level signal; otherwise, it outputs a high-level signal, causing comparator OP1 to output a PWM signal. The second capacitor C2 and the Schmitt trigger inverter CR1 work together to filter and smooth the PWM signal, outputting the processed PWM signal to processor 104. Processor 104 indirectly measures the duty cycle and period of the equalizing current Ib based on the PWM signal through the input capture function.

[0082] In this embodiment, the equalization current of the battery pack is converted into a sampling voltage by a voltage sampling circuit, so that the sample-and-hold circuit can use and hold the maximum value of the output sampling voltage and output the maximum sampling voltage to the analog-to-digital converter (ADC). Then, the processor obtains the digital sampling voltage after analog-to-digital conversion of the maximum sampling voltage through the ADC, and determines the maximum value of the equalization current based on the analysis of the digital sampling voltage. Furthermore, the comparison circuit can also receive the sampling voltage converted by the voltage sampling circuit, and output a PWM signal after square wave shaping of the sampling voltage based on the reference voltage and the magnitude of the sampling voltage. This allows the processor to determine parameters such as the period and duty cycle of the equalization current by analyzing the period and duty cycle of the PWM signal. In this technical solution, the current acquisition circuit can be used to automatically acquire relevant parameters of the equalization current of the battery pack to obtain the equalization current data of the battery pack. Compared with the manual acquisition method in related technologies, this can effectively improve the acquisition efficiency of the equalization current data of the battery pack and reduce the acquisition error rate.

[0083] This application also provides a testing device. The testing device includes the current sampling circuit provided in this application embodiment. Optionally, the testing device includes... Figure 1 or Figure 4 The current sampling circuit is shown. For example, the test equipment can be various battery testing equipment such as an FCT device. Since the test equipment includes the current sampling circuit provided in the embodiments of this application, it possesses the technical effects of this current sampling circuit, which will not be elaborated upon here.

[0084] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0085] Although embodiments of this application have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of this application, the scope of which is defined by the claims and their equivalents.

Claims

1. A current sampling circuit, characterized in that, include: Voltage sampling circuit, sample and hold circuit, analog-to-digital converter circuit, processor, and comparator circuit; The voltage sampling circuit is connected to the battery pack and the sample-and-hold circuit, and is used to collect the equalization current of the battery pack, convert the equalization current into a sampling voltage, and output the sampling voltage. The sample-and-hold circuit is connected to the analog-to-digital converter circuit and is used to sample and hold the maximum sample voltage of the output sample voltage. The analog-to-digital conversion circuit is also connected to the processor and is used to convert the maximum sampling voltage analog-to-digital to a digital sampling voltage and output the digital sampling voltage. The comparison circuit is connected to the voltage sampling circuit and the reference voltage terminal, and is used to output a pulse width modulation (PWM) signal according to the magnitude of the reference voltage provided by the reference voltage terminal and the sampled voltage. The processor is used to analyze the relevant parameters of the equalization current based on the digital sampling voltage and the PWM signal. The relevant parameters include at least the duty cycle, period, and maximum value.

2. The current sampling circuit according to claim 1, characterized in that, The sample-and-hold circuit includes: a first-stage voltage follower, a second-stage voltage follower, a holding capacitor, and a clearing module; The first-stage voltage follower is connected to the voltage sampling circuit and the second-stage voltage follower. One end of the holding capacitor is connected to the connection path between the first-stage voltage follower and the second-stage voltage follower. One end of the holding capacitor is also connected to the clearing module. The other end of the holding capacitor is grounded. The clearing module is also connected to the processor. The zeroing module is used to control the discharge and reset of the holding capacitor under the control of the processor; The first-stage voltage follower, the second-stage voltage follower, and the holding capacitor are used to sample and hold the maximum sampled voltage of the output sampled voltage after the holding capacitor is reset.

3. The current sampling circuit according to claim 2, characterized in that, The first-stage voltage follower includes: a first operational amplifier, a first diode, a first resistor, and a first capacitor; the input terminal of the first operational amplifier is connected to the voltage sampling circuit through the first resistor, and the output terminal is connected to the second-stage voltage follower; the first diode and the first capacitor are respectively connected to the input terminal and the output terminal of the first operational amplifier. The second-level voltage follower includes: a second operational amplifier and a second resistor; the input terminal of the second operational amplifier is connected to the output terminal, one end of the second resistor is connected to the input terminal of the first operational amplifier, and the other end of the second resistor is connected to the output terminal of the second operational amplifier.

4. The current sampling circuit according to claim 2 or 3, characterized in that, The sample-and-hold circuit further includes: a low-pass filter; The low-pass filter is connected to the second-stage voltage follower and is used to perform noise filtering on the maximum sampled voltage output by the second-stage voltage follower, and output the processed maximum sampled voltage.

5. The current sampling circuit according to claim 1, characterized in that, The comparison circuit includes: a comparator; The comparator is connected to the voltage sampling circuit and the reference voltage terminal, and is used to output a PWM signal according to the magnitude of the reference voltage and the sampled voltage.

6. The current sampling circuit according to claim 5, characterized in that, The comparison circuit further includes: a third resistor and a fourth resistor; The third resistor is connected to the voltage sampling circuit and the comparator, respectively, and the fourth resistor is connected to the reference voltage terminal and the comparator, respectively.

7. The current sampling circuit according to claim 1, characterized in that, The current sampling circuit further includes: an anti-interference circuit; The anti-interference circuit is connected to the comparator circuit and the processor, and is used to filter and despiking the PWM signal output by the comparator circuit, and output the processed PWM signal.

8. The current sampling circuit according to claim 7, characterized in that, The anti-interference circuit includes: a second capacitor and a Schmitt inverter; One end of the second capacitor is connected to the output of the comparator circuit and the input of the Schmitt inverter, respectively, and the other end of the second capacitor is grounded. The output of the Schmitt inverter is connected to the processor.

9. The current sampling circuit according to claim 1, characterized in that, The current sampling circuit further includes: a voltage follower; The voltage follower is connected to the sample-and-hold circuit and the analog-to-digital converter circuit respectively, and is used to output the maximum sampled voltage as a voltage follower.

10. A testing device, characterized in that, The test equipment includes the current sampling circuit as described in any one of claims 1 to 9.

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