Device for operating LED display
By using a combination of ping-pong line buffers and frame buffers in LED displays, the problems of high hardware cost and frame latency in traditional LED displays are solved, achieving the effects of cost reduction and flicker reduction.
Patent Information
- Application Number
- CN202422286449.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Priority Date
- 2023-10-25
- Filing Date
- 2024-09-18
- Publication Date
- 2025-12-02
- Estimated Expiration
- 2034-09-18
AI Technical Summary
The ping-pong frame buffer in traditional LED display drivers increases hardware costs and causes frame delay. Existing technologies are difficult to effectively reduce LED flicker and cannot avoid frame delay.
By employing a combination of ping-pong line buffers and frame buffers, and by alternating between storing and displaying scan line data in the line buffer and frame buffer, the SRAM hardware cost is reduced and the latency is reduced from one frame to one scan line.
It effectively reduces SRAM hardware costs by half and reduces latency from one frame to one scan line, improving refresh rate and reducing flickering issues.
Smart Images
Figure CN223624720U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to a device for operating an LED display. Background Technology
[0002] Because LED displays have a faster response time than liquid crystal displays (LCDs), they are prone to flickering. Traditional LED driver architectures incorporate a ping-pong frame buffer (a reciprocating frame buffer memory) to reduce LED flicker at higher refresh rates. This ping-pong frame buffer stores video data, allowing each scan section to be lit simultaneously, and each line to be refreshed several times within a frame, thus reducing or eliminating LED flicker.
[0003] However, ping-pong frame buffers increase cost and may lead to further frame latency. Specifically, the size of the static random-access memory (SRAM) of a ping-pong frame buffer is directly proportional to the capacity of the number of driven pixels (e.g., twice the capacity). However, with ping-pong frame buffers, a one-frame delay is unavoidable. Therefore, there is an urgent need to develop a new method or device to reduce flicker in LED displays. Utility Model Content
[0004] The purpose of this utility model is to introduce some concepts in a simplified form, which will be further described in detail below. Its main purpose is not to identify key or essential features of the claimed subject matter, nor is it intended to be used as an auxiliary means to determine the scope of the claimed subject matter.
[0005] According to an exemplary embodiment, a method for operating an LED display is provided, which uses a ping-pong row buffer and a frame buffer to halve the SRAM hardware cost and reduce latency from one frame to one scan line. Specifically, the method includes: storing Nth scan line data in a row buffer, where N is a natural number equal to or greater than 1; storing the Nth scan line data in a frame buffer; displaying the Nth scan line data stored in the row buffer; storing (N+1)th scan line data in the row buffer while displaying the Nth scan line data stored in the row buffer; storing the (N+1)th scan line data in the frame buffer; displaying the (N+1)th scan line data stored in the row buffer; storing the (N+2)th scan line data in the row buffer while displaying the (N+1)th scan line data stored in the row buffer; storing the (N+2)th scan line data in the frame buffer; and simultaneously displaying the (N+2)th scan line data stored in the row buffer.
[0006] Furthermore, in an exemplary embodiment, the method further includes: displaying the Nth scan line data stored in the frame buffer; displaying the (N+1)th scan line data stored in the frame buffer; and displaying the (N+2)th scan line data stored in the frame buffer. Additionally, the scan line data stored in the frame buffer, from the Nth scan line data to the (N+2)th scan line data, are displayed sequentially in the same order as previously displayed from the line buffer. The Nth scan line data is stored in at least one line buffer, where N is a natural number equal to or greater than 1; the Nth scan line data stored in at least one line buffer is displayed; while displaying the Nth scan line data stored in at least one line buffer, the Nth scan line data is stored in at least one frame buffer, and the (N+1)th scan line data is stored in at least one line buffer; the (N+1)th scan line data stored in the at least one line buffer is displayed; while displaying the (N+1)th scan line data stored in at least one line buffer, the (N+1)th scan line data is stored in at least one frame buffer, and the (N+2)th scan line data is stored in at least one line buffer; the (N+2)th scan line data stored in the at least one line buffer is displayed; and while displaying the (N+2)th scan line data stored in the at least one line buffer, the (N+2)th scan line data is stored in at least one frame buffer, and the above steps are repeated until the (N+M)th scan line data stored in the line buffer is displayed, where M is a predetermined natural number greater than N. The method also includes displaying the scan line data stored in the frame buffer in the order of the Nth scan line data to the (N+M)th scan line data, where M is a predetermined natural number.
[0007] In another exemplary embodiment, the method may include: storing Nth scan line data in a line buffer, where N is a natural number equal to or greater than 1; displaying the Nth scan line data stored in the line buffer; while displaying the Nth scan line data stored in the line buffer, storing the Nth scan line data in a frame buffer and storing the (N+1)th scan line data in the line buffer; displaying the (N+1)th scan line data stored in the line buffer; while displaying the (N+1)th scan line data stored in the line buffer, storing the (N+1)th scan line data in the frame buffer and storing the (N+2)th scan line data in the line buffer; displaying the (N+2)th scan line data stored in the line buffer; and while displaying the (N+2)th scan line data stored in the line buffer, storing the (N+2)th scan line data in the frame buffer.
[0008] Furthermore, in an exemplary embodiment, the scan line data stored in the frame buffer is displayed sequentially from the Nth scan line data to the (N+M)th scan line data, in the same order as previously displayed from the line buffer. The line buffer is a ping-pong line buffer, configured to be toggle at each step of storing scan line data. Scan line data is stored from the line buffer into the frame buffer. The size of the line buffer is configured to store each scan line data from the Nth scan line data to the (N+M)th scan line data. The size of the frame buffer is configured to store all scan line data from the Nth scan line data to the (N+M)th scan line data.
[0009] According to another exemplary embodiment, an LED display device is provided. The device includes: a line buffer; a frame buffer; a processor; and a storage device communicatively coupled to the processor. The storage device can store operable instructions executed by the processor to perform the following steps: storing Nth scan line data in the line buffer, where N is a natural number equal to or greater than 1; storing the Nth scan line data in the frame buffer; displaying the Nth scan line data stored in the line buffer; while displaying the Nth scan line data stored in the line buffer, storing (N+1)th scan line data in the line buffer; storing (N+1)th scan line data in the frame buffer; displaying the (N+1)th scan line data stored in the line buffer; while displaying the (N+1)th scan line data stored in the line buffer, storing (N+2)th scan line data in the line buffer; storing (N+2)th scan line data in the frame buffer; and simultaneously displaying the (N+2)th scan line data stored in the line buffer.
[0010] In another exemplary embodiment, the storage device may store operable instructions executed by the processor to perform the following steps: storing the Nth scan line data in a line buffer, where N is a natural number equal to or greater than 1; displaying the Nth scan line data stored in the line buffer; while displaying the Nth scan line data stored in the line buffer, storing the Nth scan line data in a frame buffer and storing the (N+1)th scan line data in the line buffer; displaying the (N+1)th scan line data stored in the line buffer; while displaying the (N+1)th scan line data stored in the line buffer, storing the (N+1)th scan line data in a frame buffer and storing the (N+2)th scan line data in the line buffer; displaying the (N+2)th scan line data stored in the line buffer; and simultaneously storing the (N+2)th scan line data in the frame buffer while displaying the (N+2)th scan line data stored in the line buffer.
[0011] Furthermore, in one exemplary embodiment, when the processor executes an operable instruction, the storage device may store the instruction to further perform the following steps: displaying the Nth scan line data stored in the frame buffer; displaying the (N+1)th scan line data stored in the frame buffer; and simultaneously displaying the (N+2)th scan line data stored in the frame buffer. The processor displays the scan line data stored in the frame buffer sequentially from the Nth scan line data to the (N+2)th scan line data in the same order as previously displayed from the line buffer. When the processor executes an operable instruction, the storage device stores the instruction to store the Nth scan line data in at least one line buffer, where N is a natural number equal to or greater than 1; display the Nth scan line data stored in at least one line buffer; during the display of the Nth scan line data stored in at least one line buffer, store the Nth scan line data in at least one frame buffer, and store the (N+1)th scan line data in at least one line buffer; display the (N+1)th scan line data stored in the at least one line buffer; during the display of the (N+1)th scan line data stored in at least one line buffer, store the Nth scan line data in at least one frame buffer, and store the (N+1)th scan line data in at least one line buffer; display the (N+1)th scan line data stored in at least one line buffer; during the display of the (N+1)th scan line data stored in at least one line buffer, store the (N+1)th scan line data in at least one line buffer; during the display of the (N+1)th scan line data stored in at least one line buffer, store the (N+1)th scan line data in at least one line buffer, and ..., and store the (N+1)th scan line data in at least one line buffer, and store the (N+1)th scan line data in at least one line buffer, and store the (N+1)th scan line data in at least one line buffer, and store the (N+1)th scan line data in at least one line buffer, and store the (N+1)th scan line data in During the display of (N+1) scan line data, the (N+1)th scan line data is stored in at least one frame buffer, and the (N+2)th scan line data is stored in at least one line buffer; the (N+2)th scan line data stored in the at least one line buffer is displayed; and during the display of the (N+2)th scan line data stored in the at least one line buffer, the (N+2)th scan line data is stored in at least one frame buffer, and the above steps are repeated until the (N+M)th scan line data stored in the line buffer is displayed, where M is a predetermined natural number greater than N. When the processor executes an operable instruction, the storage device stores the instruction to further execute the display of the scan line data stored in the frame buffer from the Nth scan line data to the (N+M)th scan line data, where M is a predetermined natural number.
[0012] Furthermore, in one exemplary embodiment, the processor displays the scan line data stored in the frame buffer sequentially from the Nth scan line to the (N+M)th scan line, in the same order as previously displayed from the line buffer. The line buffer is a ping-pong line buffer configured to be toggle at each step of storing the scan line data. Scan line data is stored from the line buffer into the frame buffer. The size of the line buffer is configured to store each scan line from the Nth to the (N+M)th scan line. The size of the frame buffer is configured to store all scan line data from the Nth to the (N+M)th scan line. Attached Figure Description
[0013] The advantages of the embodiments of the present invention will become apparent from the following detailed description of exemplary embodiments, which should be considered in conjunction with the accompanying drawings.
[0014] Figure 1 This is a schematic diagram of the data transmission sequence of the LED display in an exemplary embodiment of the present invention.
[0015] Figure 2 This is a schematic diagram of the data transmission sequence from subframe S0_F0 to S5_F0 and then to S0_F1, drawn according to an exemplary embodiment.
[0016] Figure 3 A schematic diagram of segmented transactions in subframe S0_F0 drawn according to an exemplary embodiment.
[0017] Figure 4 A schematic diagram of segmented transactions in subframe S1_F0 drawn according to an exemplary embodiment.
[0018] Figure 5 This is a schematic diagram of segmented transactions in subframes S2_F0 to S5_F0 and S0_F1, drawn according to an exemplary embodiment.
[0019] Figure 6 This is a schematic block diagram of an LED driver component in an exemplary embodiment.
[0020] Figure 7 A timing diagram of a driving scheme drawn according to an exemplary embodiment. Detailed Implementation
[0021] Various aspects of this utility model have been disclosed in the following description and accompanying drawings with reference to specific embodiments of the utility model. An alternative embodiment may be devised without departing from the spirit or scope of the utility model. Furthermore, well-known elements of exemplary embodiments of the utility model will not be described in detail or omitted in this specification to avoid obscuring the relevant details of the utility model. In addition, several terms used herein will be discussed below for ease of understanding of this patent specification.
[0022] As used herein, the term "exemplary" means "serving as an example, instance, or illustration," and the embodiments described herein are not limiting but merely exemplary. It should be understood that the described embodiments are not necessarily to be construed as being more preferred or advantageous than other embodiments. Furthermore, the terms "embodiment of the present invention," "embodiment," or "utility invention" do not require that all embodiments of the present invention include the features, advantages, or modes of operation discussed.
[0023] Furthermore, many embodiments are described based on sequences of actions performed by elements of, for example, computing devices. It will be appreciated that the various actions described herein can be performed by specific circuitry (e.g., application-specific integrated circuits (ASICs)), program instructions executed by one or more processors, or a combination of both. Moreover, these sequences of actions described herein can be considered entirely contained in any form of computer-readable storage medium storing a corresponding set of computer instructions that, when executed, cause the associated processor to perform the functions described herein. Therefore, various aspects of this invention can be implemented in many different forms, all of which are considered to fall within the scope of the claims. Furthermore, for each embodiment described herein, a corresponding form of any such embodiment can be described herein as, for example, "logically configured" to perform the described actions.
[0024] Various exemplary embodiments of a scrambling progressive scan architecture for an LED driver are disclosed according to an exemplary embodiment and generally with reference to the accompanying drawings. According to an exemplary embodiment, the scrambling progressive scan architecture for an LED driver can use a ping-pong line buffer and a frame buffer, which can reduce the SRAM hardware cost by half. This architecture is particularly advantageous for small-pitch or small / miniature LED drivers where large drive pixel capacities are increasingly required. Furthermore, in the exemplary embodiment, using a ping-pong line buffer instead of a frame buffer can reduce the latency from one frame to one scan line.
[0025] Turn now Figure 1 , Figure 1 This is a data transmission sequence diagram of an LED display in an exemplary embodiment. According to the exemplary embodiment, the LED display may include six regions, each region having 180 scan lines as follows:
[0026] DR0 is the driver for all LEDs in region 0 and scan lines 0-179.
[0027] DR1 is the driver for all LEDs in region 1, scan lines 180-359.
[0028] DR2 is the driver for all LEDs in region 2, scan lines 360-539.
[0029] DR3 is the driver for all LEDs in region 3, scan lines 540-719.
[0030] DR4 is the driver for all LEDs in region 4, scan lines 720-899.
[0031] DR5 is the driver for all LEDs in region 5, scan lines 900-1079.
[0032] In an exemplary embodiment, each frame period can be divided into S segments (subframes), and the time span of each segment (T) is... subframe The refresh rate is approximately 1 / frame / segment, which increases the refresh rate from frame rate (Frame_rate) to Frame_rate*S. With a 120Hz frame rate and 6 segments, the refresh rate is 1 / 120 / 6*1e3 = 1.3889 milliseconds. Furthermore, in an exemplary embodiment, each subframe can be vertically divided into Z regions. The number of scan lines in each region is determined by the number of scan regions, which is equal to Total_SCAN / Z. For example, in a 1920 (channels) × 1080 (scan lines) 1K LED display panel divided into 6 regions, each region has 1080 / 6 = 180 scan lines. In the case of vertical scanning, the total number of pixels in each region is 1920(H) × 180(V). H represents the horizontal direction, and V represents the vertical direction.
[0033] Furthermore, according to an exemplary embodiment, each region can be controlled by multiple LED drivers to achieve control over the entire horizontal range. For example, in the case of an LED driver driving 60 (channels) x 180 (scan area) pixels, each region requires 1920 / 60 = 32 LED drivers. With a 120Hz frame rate and 6 segments or subframes, the scan display period is subframe period / scan area = 1 / (120×6) / 180 = 1.3889ms / 180 = 7.716us. In an exemplary embodiment, frame segments are represented in the format "S(segment)_F(frame)". Therefore, the segment of frame_0 is "S0_F0-S5_F0", while "S0_F1-S5_F1" is the segment of frame_1. Furthermore, in an exemplary embodiment, data is represented in the format "F(frame)_S(segment)_Z(area)_CX(scan line)". For example, "F0_S0_Z0_CX0" represents the data for frame 0_segment_0_area 0 and scan line 0. During the display of the next scan line, the new scan line data is transmitted and stored in the ping-pong line buffer.
[0034] According to one exemplary embodiment, when the current scan line is fully displayed and a scan line change signal is triggered, the LED driver triggers the ping-pong line buffer and displays the new scan line data. The new scan line data is stored in the frame buffer. In one exemplary embodiment, switching the ping-pong line buffer and storing the data in the frame buffer do not need to be performed simultaneously. One exemplary embodiment shows that new scan line data can be stored in the frame buffer as soon as the line buffer has been updated. However, allowing both to occur simultaneously allows for better timing control.
[0035] Turn now Figure 2 , Figure 2 This diagram illustrates the data transmission sequence from subframe S0_F0 to S5_F0 and then to S0_F1. According to an exemplary embodiment, each LED driver has a ping-pong row buffer to store the current scan line data and the data for the next scan line. Furthermore, in the exemplary embodiment, a frame buffer can be used to display the same or similar content in subsequent segments (subframes). After filling the row buffer, it can wait for a change in the scan line signal to switch the scan line display content while storing the data in the frame buffer.
[0036] According to an exemplary embodiment, displaying the current scan line data and storing the current scan line data in the frame buffer may occur simultaneously. Therefore, in each scan cycle, the LED driver can display the current scan line data and receive the next scan line data from the line buffer. Once a change scan line signal is received, the LED driver can swap the line buffers to change the displayed content and store that content in the frame buffer. After all scan lines in each region have been displayed in a segment (subframe), the region data for all scan lines may have been stored in the frame buffer, and the stored data can be used for display in subsequent segments.
[0037] Still with Figure 2For reference, according to an exemplary embodiment, data for DR0 can be transmitted and stored in the frame buffer during S0_FN and displayed repeatedly during S1_FN-S5_FN. Data for DR1 can be transmitted and stored in the frame buffer during S1_FN and displayed repeatedly during S2_FN-S5_FN and S0_FN+1. Data for DR2 can be transmitted and stored in the frame buffer during S2_FN and displayed repeatedly during S3_FN-S5_FN and S0_FN+1-S1_FN+1. Data for DR3 can be transmitted and stored in the frame buffer during S3_FN and displayed repeatedly during S4_FN-S5_FN and S0_FN+1-S2_FN+1. Data for DR4 can be transmitted and stored in the frame buffer during S4_FN and displayed repeatedly during S5_FN, S0_FN+1-S3_FN+1. Data from DR5 can be transmitted and stored in the frame buffer during S5_FN, and then repeated in S0_FN+1-S4_FN+1.
[0038] According to an exemplary embodiment, all Frame_N data can be transmitted to the LED driver from the beginning to the end of Frame_N, but the display can start from Frame_N and end within Frame_N+1. Compared to conventional architectures that typically have a one-frame delay, the latency of the exemplary embodiment can be as short as "one scan line".
[0039] Turn now Figure 3-5 , combined Figure 3-5 This document provides a more detailed description of the segmented transactions described above in subframes S0_F0 to S5_F0 and S0_F1. According to an exemplary embodiment, refer to... Figure 3The segmented transaction of subframe S0_F0 can be initiated by storing F0_S0_Z0_CX0 in the line buffer of DR0 (S001). During the display of F0_S0_Z0_CX0 stored in the line buffer, the transaction continues further by storing F0_S0_Z0_CX0 in the DR0 frame buffer (which is stored in the frame buffer once the line buffer is updated), and storing the next scan line data F0_S0_Z0_CX1 in the line buffer (the data transfer of F0_S0_Z0_CX1 can be completed before the display of F0_S0_Z0_CX0 ends) (S002). After displaying F0_S0_Z0_CX0 stored in the DR0 line buffer, the transaction continues further by displaying F0_S0_Z0_CX1 stored in the DR0 line buffer. During the display of F0_S0_Z0_CX1 stored in the line buffer, the transaction continues by storing F0_S0_Z0_CX1 in the frame buffer of DR0 and storing the next scan line data F0_S0_Z0_CX2 in the line buffer. According to the exemplary embodiment, DR1-DR5 are empty. (S003). The above steps are repeated until F0_S0_Z0_CX177 stored in the DR0 line buffer is displayed. When the display of F0_S0_Z0_CX177 stored in the DR0 line buffer ends, the transaction continues to display F0_S0_Z0_CX178. During the display of F0_S0_Z0_CX178 stored in the line buffer, the transaction continues to store F0_S0_Z0_CX178 in the DR0 frame buffer and stores the next scan line data F0_S0_Z0_CX179 (the last data of region_0, frame_0) in the line buffer. DR1-DR5 remain empty. (S004). When DR0 displays the end of F0_S0_Z0_CX178, the transaction continues to display F0_S0_Z0_CX179 and stores F0_S0_Z0_CX179 in the frame buffer of DR0. According to the exemplary embodiment, at this time, all data in Zone_0 and frame_0 should be stored in the frame buffer of DR0. DR1 begins receiving F0_S1_Z1_CX0. DR2-DR5 remain empty. (S005).
[0040] Now for reference Figure 4The segmented transaction now switches from subframe S0_F0 to S1_F0. At the end of displaying F0_S0_Z0_CX179 stored in the DR0 line buffer, the transaction continues to repeatedly display F0_S0_Z0_CX0 from the DR0 frame buffer, and DR1 begins displaying F0_S1_Z1_CX0 from the DR1 line buffer. During the display of F0_S1_Z1_CX0 stored in the DR1 line buffer, the transaction continues to store F0_S1_Z1_CX0 in the DR1 frame buffer and stores the next scan line data F0_S1_Z1_CX1 in the DR1 line buffer. DR2-DR5 are empty. (S006). At the end of displaying F0_S1_Z1_CX0 stored in the DR1 line buffer, the transaction continues to repeatedly display F0_S0_Z0_CX1 from the DR0 frame buffer and F0_S1_Z1_CX1 from the DR1 line buffer. While displaying F0_S1_Z1_CX1 stored in the DR1 row buffer, the transaction continues to store F0_S1_Z1_CX1 in the DR1 frame buffer and stores the next scan row data F0_S1_Z1_CX2 in the DR1 row buffer. DR2-DR5 are empty. (S007). The above steps are repeated until F0_S1_Z1_CX177 stored in the DR1 row buffer is displayed. After the display of F0_S1_Z1_CX177 stored in the DR1 row buffer ends, the transaction continues to repeatedly display F0_S0_Z0_CX178 from the DR0 frame buffer and F0_S1_Z1_CX178 from the DR1 row buffer. During the display of F0_S1_Z1_CX178 stored in the row buffer of DR1, the transaction continues to store F0_S1_Z1_CX178 in the frame buffer of DR1 and stores the next scan row data F0_S1_Z1_CX179 (the last data of region_1, frame_0) in the row buffer of DR1. DR2-DR5 remain empty. (S008). When the display of F0_S1_Z1_CX178 stored in the row buffer of DR1 ends, the transaction continues to repeatedly display F0_S0_Z0_CX179 from the frame buffer of DR0, display F0_S1_Z1_CX179 from the row buffer of DR1, and store F0_S1_Z1_CX179 in the frame buffer of DR1. At this time, all data of Zone_1 and frame_0 are stored in the frame buffer of DR1, and DR2 begins to receive F0_S2_Z2_CX0. DR3-DR5 are empty. (S009).
[0041] Now for reference Figure 5The segmented transaction now switches from subframe S1_F0 to S2_F0. After displaying F0_S1_Z1_CX179 stored in the DR1 line buffer, the transaction continues to repeatedly display F0_S0_Z0_CX0 from the DR0 frame buffer and then repeatedly display F0_S1_Z1_CX0 from the DR1 frame buffer. DR2 begins displaying F0_S2_Z2_CX0 from the DR2 line buffer. While displaying F0_S2_Z2_CX0 stored in the DR2 line buffer, the transaction continues to store F0_S2_Z2_CX0 in the DR2 frame buffer and stores the next scan line data F0_S2_Z2_CX1 in the DR1 line buffer. DR3-DR5 are empty at this point. (S010). Similar steps are repeated until F0_S4_Z4_CX179 stored in the DR4 line buffer is displayed, and the segmented transaction switches from subframe S4_F0 to S5_F0. After displaying F0_S4_Z4_CX179 stored in the DR4 line buffer, the transaction continues to repeatedly display F0_S0_Z0_CX0-F0_S4_Z4_CX0 from the DR0-4 frame buffer. DR5 begins displaying F0_S5_Z5_CX0 from the DR5 line buffer. While displaying F0_S5_Z5_CX0 stored in the DR5 line buffer, the transaction continues to store F0_S5_Z5_CX0 in the DR5 frame buffer and stores the next scan line data F0_S5_Z5_CX1 in the DR1 line buffer. (S011). Similar steps are repeated until F0_S5_Z5_CX178 stored in the DR5 line buffer is displayed. After the display of F0_S5_Z5_CX178 stored in the DR5 line buffer ends, the transaction continues to repeatedly display F0_S0_Z0_CX179-F0_S4_Z4_CX179 from the DR0-4 frame buffer. DR5 begins displaying F0_S5_Z5_CX179 from the DR5 line buffer. During the display of F0_S5_Z5_CX179 stored in the DR5 line buffer, the transaction continues to store F0_S5_Z5_CX179 in the DR5 frame buffer and store F1_S0_Z0_CX0 (the first data of frame_1) in the DR0 line buffer. (S012). The segmentation transaction now switches from subframe S5_F0 to S0_F1. After displaying F0_S5_Z5_CX179 stored in the DR5 line buffer, the transaction continues to repeatedly display F0_S1_Z1_CX0-F0_S5_Z5_CX0 from the frame buffers of DR1-5. DR0 begins displaying F1_S0_Z0_CX0 from the line buffer of DR0.While displaying F1_S0_Z0_CX0 stored in the DR0 row buffer, the transaction continues to store F1_S0_Z0_CX0 in the DR0 frame buffer and stores the next scan row data F1_S0_Z0_CX1 in the DR1 row buffer.
[0042] Now Figure 6 and Figure 7 For reference, Figure 6 This is a schematic block diagram of components in an exemplary embodiment of an LED driver, which provides a 16-bit grayscale LED driver that drives 60×180 pixels. Figure 7 This is a timing diagram of the driving scheme drawn according to an exemplary embodiment. As shown, the SCAN_Change strobe pulse can trigger a change in the scan line content. It can also trigger the FILL_PIN signal of the row buffer. The ping-pong row buffer operation is defined by FILL_PIN. When FILL_PIN = 1, the ping memory is being updated, and the pong memory drives SCAN_DATA. When FILL_PIN = 0, the PING memory drives SCAN_DATA, and the PONG memory drives SCAN_DATA. Simultaneously, the frame buffer write strobe appears after the scan change strobe. It triggers the writing of SCAN_DATA to the frame buffer. The input to the PWM engine comes from SCAN_DATA when DATA_UPDATE = 1; and Frame_BUF_OUT when DATA_UPDATE = 0. The PWM engine calculates the PWM pulse and shifts it into the output channel.
[0043] The above description and accompanying drawings illustrate the principles, preferred embodiments, and operating modes of this utility model. However, this utility model should not be construed as limited to the specific embodiments described above. Additional variations of the above embodiments will be understood by those skilled in the art (e.g., features associated with certain configurations of this utility model may be modified to be associated with any other configuration of this utility model, as needed).
[0044] Therefore, the above embodiments should be considered illustrative rather than restrictive. It should be recognized that those skilled in the art can make modifications to these embodiments without departing from the scope of the invention as defined in the following claims.
Claims
1. A device for operating an LED display, characterized in that, include: At least one row buffer; At least one frame buffer; and At least one processor and at least one storage device communicatively coupled to at least one of the processors, and when at least one of the processors executes an operable instruction, at least one of the storage devices can store the instruction for performing the following steps: Store the Nth scanned row data in at least one row buffer, where N is a natural number equal to or greater than 1; Display the Nth scan row data stored in at least one row buffer; During the display of the Nth scan line data stored in at least one line buffer, the Nth scan line data is stored in at least one frame buffer, and the (N+1)th scan line data is stored in at least one line buffer; Display the (N+1)th scan row data stored in the at least one row buffer; During the display of the (N+1)th scan line data stored in at least one line buffer, the (N+1)th scan line data is stored in at least one frame buffer, and the (N+2)th scan line data is stored in at least one line buffer. Display the (N+2)th scan row data stored in the at least one row buffer; and During the display of the (N+2)th scan line data stored in the at least one row buffer, the (N+2)th scan line data is stored in at least one frame buffer.
2. The apparatus according to claim 1, characterized in that, in, When an operable instruction is executed by the at least one processor, the at least one storage device stores the instruction to further perform the following steps: Display the Nth scan line data stored in the at least one frame buffer; Display the (N+1)th scan line data stored in the at least one frame buffer; and Display the (N+2)th scan line data stored in the at least one frame buffer.
3. The apparatus according to claim 1, characterized in that, The scan line data stored in at least one frame buffer is displayed by at least one processor sequentially from the Nth scan line data to the (N+2)th scan line data in the same order as previously displayed from at least one line buffer.
4. The apparatus according to claim 1, characterized in that, When an operable instruction is executed by the at least one processor, the at least one storage device stores the instruction to repeat the steps until the (N+M)th scan line data stored in the at least one line buffer is displayed, where M is a predetermined natural number greater than N.
5. The apparatus according to claim 4, characterized in that, in, When the at least one processor executes the operable instruction, the at least one storage device stores the instruction to further display the scan line data stored in the at least one frame buffer from the Nth scan line data to the (N+M)th scan line data, where M is a predetermined natural number.
6. The apparatus according to claim 4, characterized in that, The scan line data stored in at least one frame buffer is displayed sequentially by at least one processor from the Nth scan line data to the (N+M)th scan line data in the same order as previously displayed from at least one line buffer.
7. The apparatus according to claim 1, characterized in that, The at least one row buffer is a ping-pong row buffer, which is configured to be toggled at each step of storing at least one scan row of data.
8. The apparatus according to claim 1, characterized in that, At least one scan line data is stored from at least one line buffer into at least one frame buffer.
9. The apparatus according to claim 4, characterized in that, The size of the at least one row buffer is configured to store each scan row data from the Nth scan row data to the (N+M)th scan row data.
10. The apparatus according to claim 4, characterized in that, The size of the at least one frame buffer is configured to store all scan line data from the Nth scan line data to the (N+M)th scan line data.