Back contact battery

Abstract

The utility model discloses a back contact battery. The back contact battery comprises a substrate, a plurality of first conductive parts, a plurality of second conductive parts and an electrode structure, the electrode structure comprises a plurality of P-type main grids and a plurality of N-type main grids. The first conductive parts and the second conductive parts are alternately arranged on the back face of the substrate at intervals. The P-type main grid is arranged corresponding to the first conductive part, and the N-type main grid is arranged corresponding to the second conductive part. The P-type main grid is connected with a power supply cathode, and the N-type main grid is connected with a power supply anode. According to the back contact battery disclosed by the invention, the reverse voltage is accessed to the back electrode during laser scanning, so that part of the electrode can effectively burn through the first conductive part and the second conductive part, the electrode is in effective contact with the first conductive part and the second conductive part, and the contact resistance of the electrode is reduced to improve the battery efficiency. Moreover, the first conductive part and the second conductive part are arranged at intervals, so that a natural air insulator is formed between the first conductive part and the second conductive part, and the back contact battery is prevented from being broken down when reverse voltage is applied.

Description

Technical Field

[0001] This application relates to the field of solar cells, and more particularly to a back contact cell. Background Technology

[0002] In related technologies, back contact (BC) batteries typically employ photoinjection to improve battery efficiency. This involves applying light radiation to the BC battery at a specific heating temperature to activate hydrogen ions at the backsheet, which migrate to the crystalline silicon layer. The activated hydrogen ions saturate the dangling bonds in the silicon layer, thus passivating the BC battery interface and improving efficiency. However, this method suffers from high contact resistance between the electrodes and the silicon layer, resulting in poor efficiency improvement. Utility Model Content

[0003] This application discloses a back contact battery for reducing the contact resistance between the electrode and the crystalline silicon layer, thereby improving battery efficiency.

[0004] To achieve the above objectives, this application discloses a back contact battery, comprising:

[0005] A substrate having a front side and a back side along the thickness direction, the front side being configured for laser scanning;

[0006] Multiple first conductive portions and multiple second conductive portions are provided on the back side. Each first conductive portion and each second conductive portion are alternately spaced along a first direction, and the first conductive portion and the second conductive portion extend along a second direction.

[0007] An electrode structure is provided, comprising multiple P-type main gates and multiple N-type main gates. Each P-type main gate is respectively disposed on the side of each first conductive portion away from the back surface, and each N-type main gate is respectively disposed on the side of each second conductive portion away from the back surface. The P-type main gate is configured to be connected to the negative terminal of the power supply, and the N-type main gate is configured to be connected to the positive terminal of the power supply.

[0008] Wherein, the first direction intersects with the second direction.

[0009] As an optional implementation, the spacing between adjacent first conductive portions and second conductive portions along the first direction is 10μm-200μm.

[0010] As an optional implementation, the first conductive portion includes a first dielectric layer, a first doped layer, and a first passivation layer stacked sequentially in a direction away from the substrate, and the P-type gate is disposed on the first passivation layer;

[0011] The second conductive portion includes a second dielectric layer, a second doped layer, and a second passivation layer stacked sequentially in a direction away from the substrate, and the N-type main gate is disposed on the second passivation layer.

[0012] As an optional implementation, the first passivation layer extends from one side surface of the first doped layer away from the substrate to cover the first dielectric layer and both sides of the first doped layer in the first direction;

[0013] The second passivation layer extends from one side of the second doped layer away from the substrate to cover the second dielectric layer and the two sides of the second doped layer in the first direction.

[0014] As an optional implementation, the first passivation layer includes a first passivation surface portion and two first passivation side portions. The first passivation surface portion is located on one side surface of the first doped layer in the direction away from the substrate, and the two first passivation side portions are respectively located on the two sides of the first dielectric layer and the first doped layer in the first direction. The second passivation layer includes a second passivation surface portion and two second passivation side portions. The second passivation surface portion is located on one side surface of the second doped layer in the direction away from the substrate, and the two second passivation side portions are respectively located on the two sides of the second dielectric layer and the second doped layer in the first direction.

[0015] The thickness of each of the two first passivated side portions in the first direction is 1nm-20nm, and the thickness of each of the two second passivated side portions in the first direction is 1nm-20nm; and / or,

[0016] In the first direction, the distance between one of the first passivated side portions and an adjacent second passivated side portion is d1, wherein 10μm≤d1≤200μm.

[0017] As an optional implementation, the first conductive portion further includes a first antireflection layer, the first antireflection layer being disposed on the side of the first passivation layer opposite to the first doped layer, and the P-type main gate being disposed on the first antireflection layer; and

[0018] The second conductive portion further includes a second antireflection layer, which is disposed on the side of the second passivation layer away from the second doped layer, and the N-type main gate is disposed on the second antireflection layer.

[0019] As an optional implementation, the first antireflection layer extends from one side surface of the first passivation layer away from the substrate to cover both sides of the first passivation layer in the first direction;

[0020] The second antireflection layer extends from one side of the second passivation layer away from the substrate to cover both sides of the second dielectric layer and the second doped layer in the first direction.

[0021] As an optional implementation, the first antireflection layer extends from one side surface of the first passivation layer away from the substrate to cover both sides of the first passivation layer in the first direction;

[0022] The second antireflection layer extends from one side of the second passivation layer away from the substrate to cover both sides of the second dielectric layer and the second doped layer in the first direction.

[0023] As an optional implementation, the first antireflection layer includes a first antireflection surface portion and two first antireflection side portions. The first antireflection surface portion is stacked on the first passivation surface portion along the thickness direction, and the two first antireflection side portions are respectively stacked on the two first passivation side portions along the first direction. The second antireflection layer includes a second antireflection surface portion and two second antireflection side portions. The second antireflection surface portion is stacked on the second passivation surface portion along the thickness direction, and the two second antireflection side portions are respectively stacked on the two second passivation side portions along the first direction.

[0024] The thickness of both first antireflective side portions in the first direction is 20nm-200nm, and the thickness of both second antireflective side portions in the first direction is 20nm-200nm; and / or

[0025] In the first direction, the distance between one of the first antireflective side portions and an adjacent second antireflective side portion is d2, wherein 10μm≤d2≤200μm.

[0026] As an optional implementation, the electrode structure further includes multiple P-type fine gates and multiple N-type fine gates. The P-type fine gates are connected to the P-type main gate, and the N-type fine gates are connected to the N-type main gate. Each P-type fine gate and each N-type fine gate are alternately spaced along the second direction. The P-type fine gates are sequentially disposed through the first antireflection layer and the first passivation layer along the thickness direction, and the P-type fine gates are connected to the first doped layer.

[0027] The N-type fine gate is disposed along the thickness direction in the second antireflection layer and the second passivation layer, and the N-type fine gate is connected to the second doped layer.

[0028] As an optional implementation, the doping concentration of the first doped layer is greater than the doping concentration of the second doped layer.

[0029] Compared with the prior art, the beneficial effects of this application are as follows:

[0030] This application discloses a back-contact battery, including a substrate, multiple first conductive portions, multiple second conductive portions, and an electrode structure. The multiple first conductive portions and multiple second conductive portions are alternately and sequentially disposed on the back side of the substrate along a first direction. The electrode structure includes multiple P-type main grids and multiple N-type main grids. The P-type main grids are disposed corresponding to the first conductive portions, and the N-type main grids are disposed corresponding to the second conductive portions. The P-type main grids are configured to be connected to the negative terminal of a power supply, and the N-type main grids are configured to be connected to the positive terminal of a power supply. The front side of the substrate is configured for laser scanning. During laser scanning, the back-contact battery disclosed in this application applies a reverse bias voltage to the electrode structure, causing the paste in the electrode structure to burn through the first and second conductive portions. This facilitates good contact between the electrode structure and the crystalline silicon of the first and second conductive portions, reducing the contact resistance between the electrode structure and the crystalline silicon, thereby improving battery efficiency. Furthermore, the spacing between the first and second conductive portions helps prevent breakdown of the back-contact battery when a reverse bias voltage is applied, thus preventing leakage and further improving battery efficiency. Attached Figure Description

[0031] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0032] Figure 1 This is a schematic diagram of the back contact battery structure disclosed in an embodiment of this application;

[0033] Figure 2 This is a schematic diagram of the internal structure of a back contact battery disclosed in an embodiment of this application;

[0034] Figure 3 for Figure 2 A partial structural diagram of the back contact battery;

[0035] Figure 4 This is a schematic diagram of another internal structure of the back contact battery disclosed in an embodiment of this application;

[0036] Figure 5 for Figure 4 A partial structural diagram of the back contact battery;

[0037] Figure 6 This is a top view of the back contact battery disclosed in an embodiment of this application;

[0038] Figure 7 This is a schematic diagram of the structure of the P-type fine gate and the N-type fine gate disclosed in the embodiments of this application.

[0039] Explanation of reference numerals in the attached figures:

[0040] 100. Back contact battery; 1. Substrate; 1a. Front side; 1b. Back side; 2. First conductive portion; 21. First dielectric layer; 22. First doped layer; 23. First passivation layer; 231. First passivated surface portion; 232. First passivated side portion; 24. First antireflection layer; 241. First antireflection surface portion; 242. First antireflection side portion; 3. Second conductive portion; 31. Second dielectric layer; 32. Second doped layer; 33. Second passivation layer; 331. Second passivated surface portion; 332. Second passivated side portion; 34. Second antireflection layer; 341. Second antireflection surface portion; 342. Second antireflection side portion; 4. Electrode structure; 41. P-type main grid; 42. N-type main grid; 43. P-type fine grid; 44. N-type fine grid. Detailed Implementation

[0041] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0042] In this application, the terms "upper," "lower," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. These terms are primarily for the purpose of better describing this application and its embodiments, and are not intended to limit the indicated devices, elements, or components to having a specific orientation, or to be constructed and operated in a specific orientation.

[0043] Furthermore, in addition to indicating location or positional relationship, some of the aforementioned terms may also have other meanings. For example, the term "above" may also be used in some cases to indicate a certain dependency or connection relationship. Those skilled in the art can understand the specific meaning of these terms in this application based on the specific circumstances.

[0044] Furthermore, the terms "installed," "equipped with," and "connected" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral structure; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium, or an internal connection between two devices, components, or parts. Those skilled in the art can understand the specific meaning of these terms in this application based on the specific circumstances.

[0045] Furthermore, the terms "first," "second," etc., are primarily used to distinguish different devices, elements, or components (which may be the same or different in specific type and construction), and are not intended to indicate or imply the relative importance or quantity of the indicated devices, elements, or components. Unless otherwise stated, "a plurality of" means two or more.

[0046] In related technologies, back contact (BC) batteries typically employ photoinjection to improve battery efficiency. This involves applying light radiation to the BC battery at a specific heating temperature to activate hydrogen ions at the backsheet, which migrate to the crystalline silicon layer. The activated hydrogen ions saturate the dangling bonds in the silicon layer, thus passivating the BC battery interface and improving efficiency. However, this method suffers from high contact resistance between the electrodes and the silicon layer, resulting in poor efficiency improvement.

[0047] Based on this, this application applies a reverse bias voltage to the electrode on the back of the BC battery, that is, the positive electrode of the BC battery is connected to the negative electrode of the power supply, and the negative electrode is connected to the positive electrode of the power supply. Under the laser-assisted sintering on the front of the BC battery, the electrode can burn through part of the BC battery, so that the electrode can effectively form good contact with the crystalline silicon layer in the BC battery, thereby reducing the contact resistance between the electrode and the crystalline silicon layer, which is beneficial to improving the battery efficiency.

[0048] However, during the process of applying a reverse bias voltage to the electrodes, excessively high voltage at the electrodes may cause the BC battery to break down, resulting in leakage.

[0049] In this regard, the BC battery in this application separates the part of the BC battery connected to the positive electrode from the part of the BC battery connected to the negative electrode, thereby creating an air gap between the positive and negative electrodes, which improves the insulation performance between the positive and negative electrodes and prevents the reverse bias voltage between the positive and negative electrodes from causing breakdown of the BC battery.

[0050] The technical solution of this application will be further described below with reference to the embodiments and accompanying drawings.

[0051] See Figure 1This application discloses a back contact battery 100, including a substrate 1, a plurality of first conductive portions 2, a plurality of second conductive portions 3, and an electrode structure 4. The substrate 1 has a front side 1a and a back side 1b along the thickness direction Z, and the front side 1a is configured for laser scanning. The plurality of first conductive portions 2 and the plurality of second conductive portions 3 are all disposed on the back side 1b of the substrate 1, and each first conductive portion 2 and each second conductive portion 3 is alternately spaced along a first direction X. Each first conductive portion 2 and each second conductive portion 3 extends along a second direction Y, so that the first conductive portions 2 and the second conductive portions 3 cover the back side 1b of the substrate 1.

[0052] It is understandable that the shape of the base 1 is usually square. Therefore, the first direction X can be the length direction of the base 1, and the second direction Y can be the width direction of the base 1.

[0053] The electrode structure 4 includes multiple P-type main gates 41 and multiple N-type main gates 42. Each P-type main gate 41 is respectively disposed on the side of each first conductive portion 2 facing away from the back of the substrate 1, and each N-type main gate 42 is respectively disposed on the side of each second conductive portion 3 facing away from the back of the substrate 1. In other words, the first conductive portion 2 can support the P-type main gate 41, and the second conductive portion 3 can support the N-type main gate 42. The P-type main gate 41 is configured to be connected to the negative terminal of the power supply, and the N-type main gate 42 is configured to be connected to the positive terminal of the power supply.

[0054] This application discloses a back contact battery 100, in which a P-type main grid 41 and an N-type main grid 42 are respectively supported by a first conductive portion 2 and a second conductive portion 3. When the P-type main grid 41 is connected to the negative terminal of the power supply and the N-type main grid 42 is connected to the positive terminal of the power supply, a reverse bias voltage is formed between the P-type main grid 41 and the N-type main grid 42. After laser scanning of the front side of the substrate 1, it is beneficial for the auxiliary electrode structure 4 to connect with the first conductive portion 2 and the second conductive portion 3, thereby enabling good contact between the electrode structure 4 and the first conductive portion 2, and between the N-type main grid 42 and the second conductive portion 3. In this way, the contact resistance between the electrode structure and the first conductive portion 2 and the second conductive portion 3 is reduced, thereby improving the overall efficiency of the back contact battery 100.

[0055] However, when a reverse bias voltage is applied to the back contact battery 100, the reverse bias voltage may cause the back contact battery 100 to break down, resulting in leakage during use. To address this, this application spacees the first conductive portion 2 and the second conductive portion 3, so that the P-type main grid 41 on the first conductive portion 2 and the N-type main grid 42 on the second conductive portion 3 are also spaced apart, thus forming a natural air medium between the first conductive portion 2 and the second conductive portion 3, providing good insulation. When the first conductive portion 2 carries the P-type main grid 41 and the second conductive portion 3 carries the N-type main grid 42, good insulation is formed between the P-type main grid 41 and the N-type main grid 42, which helps prevent the reverse bias voltage between the P-type main grid 41 and the N-type main grid 42 from causing breakdown of the first conductive portion 2 and the second conductive portion 3, thereby preventing leakage of the back contact battery 100.

[0056] Optionally, the substrate 1 may be a P-type silicon substrate 1 or an N-type silicon substrate 1, and this application does not make a specific limitation.

[0057] It should be noted that, in Figure 1 In the example, X indicates the first direction X, Y indicates the second direction Y, and Z indicates the thickness direction Z of the back contact battery 100, or the thickness direction Z of the substrate 1. The first direction X can be the length direction of the back contact battery 100, and the second direction Y can be the width direction of the back contact battery 100.

[0058] In order to form a good insulating gap between the first conductive part 2 and the second conductive part 3, in some embodiments, the distance between adjacent first conductive parts 2 and second conductive parts 3 along the first direction X is D, wherein 10μm≤D≤200μm. For example, D can be 10μm-30μm, 20μm-40μm, 30μm-50μm, 40μm-60μm, 50μm-70μm, 60μm-80μm, 70μm-90μm, 80μm-100μm, 90μm-110μm, 100μm -120μm, 110μm-130μm, 120μm-140μm, 130μm-150μm, 140μm-160μm, 150μm-170μm, 160μm-180μm, 170μm-190μm, 180μm-200μm. For example, D can be 10μm, 20μm, 30μm, 40μm, 50μm, 60μm, 70μm, 80μm, 90μm, 100μm, 110μm, 120μm, 130μm, 140μm, 150μm, 160μm, 170μm, 180μm, 190μm, 200μm, etc. This application sets the spacing D between two adjacent first conductive portions 2 and second conductive portions 3 within 10μm-200μm, which facilitates the formation of a good insulating spacing between the first conductive portions 2 and second conductive portions 3, thereby effectively improving the insulation performance between the first conductive portions 2 and second conductive portions 3 and preventing reverse bias voltage from causing breakdown of the first conductive portions 2 and second conductive portions 3.

[0059] Please see Figure 2 and Figure 3 In some embodiments, the first conductive portion 2 includes a first dielectric layer 21, a first doped layer 22, and a first passivation layer 23 sequentially stacked along the direction away from the substrate 1, with a P-type main gate 41 disposed on the first passivation layer 23. The second conductive portion 3 includes a second dielectric layer 31, a second doped layer 32, and a second passivation layer 33 sequentially stacked along the direction away from the substrate 1, with an N-type main gate 42 disposed on the second passivation layer 33. This application provides a first passivation layer 23 on the surface of the first doped layer 22 and a second passivation layer 33 on the surface of the second doped layer 32. By providing passivation layers on the first conductive portion 2 and the second conductive portion 3, it is beneficial to optimize the conductivity of the back side of the back contact battery 100 and reduce charge loss during the electrode transport process.

[0060] Optionally, the materials of the first dielectric layer 21 and the second dielectric layer 31 may include at least one of various dielectric materials, such as silicon oxide, magnesium fluoride, amorphous silicon, polycrystalline silicon, silicon carbide, silicon nitride, silicon oxynitride, aluminum oxide, or titanium oxide. Specifically, the dielectric layer may be composed of a silicon oxide layer containing silicon oxide. This is because the silicon oxide layer has excellent passivation properties, which can minimize the recombination loss of minority carriers on the semiconductor substrate surface, and is a thin film with excellent durability for subsequent high-temperature processes.

[0061] Optionally, the first doped layer 22 and the second doped layer 32 can be polycrystalline silicon layers containing doped elements or microcrystalline silicon layers containing doped elements, etc. The doping concentrations of the first doped layer 22 and the second doped layer 32 are different, with the doping concentration of the first doped layer 22 being greater than that of the second doped layer 32. This application achieves this by doping the first doped layer 22 with a higher element concentration, resulting in a P-type conductive region in the first conductive portion 2 where the first doped layer 22 is located, which is beneficial for meeting the conductivity requirements of the P-type main gate 41. Conversely, the second doped layer 32 achieves this by having a lower element doping concentration, resulting in an N-type conductive region in the second conductive portion 3 where the second doped layer 32 is located, which is beneficial for meeting the conductivity requirements of the N-type main gate 42. Furthermore, the difference in doping concentration between the first doped layer 22 and the second doped layer 32 facilitates the formation of a PN junction between the first conductive portion 2 and the second conductive portion 3.

[0062] Optionally, the materials of the first passivation layer 23 and the second passivation layer 33 may be silicon nitride, aluminum oxide, etc., and this application does not make specific limitations.

[0063] Optionally, the materials of the first passivation layer 23 and the second passivation layer 33 may be the same or different, and this application does not make specific limitations here.

[0064] In some embodiments, the first passivation layer 23 extends from one surface of the first doped layer 22 away from the substrate 1 to cover both sides of the first dielectric layer 21 and the first doped layer 22 in the first direction X. The second passivation layer 33 extends from one surface of the second doped layer 32 away from the substrate 1 to cover both sides of the second dielectric layer 31 and the second doped layer 32 in the first direction X. It is understood that because two adjacent first conductive portions 2 and second conductive portions 3 are spaced apart in the first direction X, the two sides of the first dielectric layer 21, the first doped layer 22, the second dielectric layer 31, and the second doped layer 32 in the first direction X are exposed. In this way, the first passivation layer 23 extends from one side surface of the first doped layer 22 to both sides of the first dielectric layer 21 and the first doped layer 22 in the first direction X, and covers both sides of the first dielectric layer 21 and the first doped layer 22 in the first direction X. Similarly, the second passivation layer 33 extends from one side surface of the second doped layer 32 to the second dielectric layer 31 and the second doped layer 32 in the first direction X, and covers both sides of the second dielectric layer 31 and the first doped layer 22 in the second direction Y. In this way, the first passivation layer 23 and the second passivation layer 33 not only provide good passivation for the first conductive portion 2 and the second conductive portion 3, but also, when a reverse bias voltage is applied to the first conductive portion 2 and the second conductive portion 3, the first passivation layer 23 and the second passivation layer 33 in the first direction X and the spacing D can form a good insulating effect, which helps prevent the first conductive portion 2 and the second conductive portion 3 from being broken down by the reverse bias voltage.

[0065] Optionally, the first passivation layer 23 includes a first passivation surface portion 231 and two first passivation side portions 232. The first passivation surface portion 231 is located on one side surface of the first doped layer 22 in the direction away from the substrate 1. The two first passivation side portions 232 are respectively located on the two sides of the first dielectric layer 21 and the first doped layer 22 in the first direction X. The thickness of the two first passivation side portions 232 in the first direction X is 1nm-20nm. The second passivation layer 33 includes a second passivation surface portion 331 and two second passivation side portions 332. The second passivation surface portion 331 is located on one side surface of the second doped layer 32 in the direction away from the substrate 1. The two second passivation side portions 332 are respectively located on the two sides of the second dielectric layer 31 and the second doped layer 32 in the first direction X. The thickness of the two second passivation side portions 332 in the first direction X is 1nm-20nm. It is understood that the two first passivation side portions 232 form sidewalls of a certain thickness on both sides of the first dielectric layer 21 and the first doped layer 22. Similarly, the two second passivation side portions 332 form sidewalls of a certain thickness on both sides of the second dielectric layer 31 and the second doped layer 32. This application improves the insulation performance of the first passivation layer 23 and the second passivation layer 33 by controlling the thickness of the first passivation side portion 232 and the second passivation side portion 332, thereby enhancing the protection effect on the first conductive portion 2 and the second conductive portion 3.

[0066] For example, when the first conductive portion 2 and the second conductive portion 3 do not have the first passivation layer 23 and the second passivation layer 33 formed, taking the formation of the first passivation layer 23 as an example, the first doped layer 22 and the first dielectric layer 21 are spaced apart from the second conductive portion 3 on both sides of the first direction X, thus avoiding space for the first passivation layer 23 to be deposited, so that the first passivation layer 23 can be formed on both sides of the first doped layer 22 and the first dielectric layer 21 in the first direction X. The first passivation layer 23 can be naturally formed on the surfaces of the first doped layer 22 and the first dielectric layer 21 in the first direction X and in the thickness direction Z by chemical vapor deposition. The formation of the side portions of the second passivation layer 33 is similar, and will not be described in detail here.

[0067] For example, the thickness of the first passivated side portion 232 is L1, which can be 1nm-3nm, 2nm-4nm, 3nm-5nm, 4nm-6nm, 5nm-7nm, 6nm-8nm, 7nm-9nm, 8nm-10nm, 9nm-11nm, 10nm-12nm, 11nm-13nm, 12nm-14nm, 13nm-15nm, 14nm-16nm, 15nm-17nm, 16nm-18nm, 17nm-19nm, 18nm-20nm, etc. For example, L1 can be 1nm, 2nm, 3nm, 4nm, 5nm, 6nm, 7nm, 8nm, 9nm, 10nm, 11nm, 12nm, 13nm, 14nm, 15nm, 16nm, 17nm, 18nm, 19nm, and 20nm, etc.

[0068] For example, the thickness of the second passivated side portion 332 is L2, which can be 1nm-3nm, 2nm-4nm, 3nm-5nm, 4nm-6nm, 5nm-7nm, 6nm-8nm, 7nm-9nm, 8nm-10nm, 9nm-11nm, 10nm-12nm, 11nm-13nm, 12nm-14nm, 13nm-15nm, 14nm-16nm, 15nm-17nm, 16nm-18nm, 17nm-19nm, 18nm-20nm, etc. For example, L2 can be 1nm, 2nm, 3nm, 4nm, 5nm, 6nm, 7nm, 8nm, 9nm, 10nm, 11nm, 12nm, 13nm, 14nm, 15nm, 16nm, 17nm, 18nm, 19nm, and 20nm, etc.

[0069] Optionally, when the first conductive portion 2 and the second conductive portion 3 are provided with a first passivated side portion 232 and a second passivated side portion 332 in the first direction X, in the first direction, a first passivated side portion 232 and an adjacent second passivated side portion 332 are adjacent and spaced apart, and the distance between them is d1, wherein 10μm≤d1≤200μm. For example, d1 can be 10μm-30μm, 20μm-40μm, 30μm-50μm, 40μm-60μm, 50μm-70μm, 60μm-80μm, 70μm-90μm, 80μm-100μm, 90μm-110μm, 100μm m-120μm, 110μm-130μm, 120μm-140μm, 130μm-150μm, 140μm-160μm, 150μm-170μm, 160μm-180μm, 170μm-190μm, 180μm-200μm. For example, d1 can be 10μm, 20μm, 30μm, 40μm, 50μm, 60μm, 70μm, 80μm, 90μm, 100μm, 110μm, 120μm, 130μm, 140μm, 150μm, 160μm, 170μm, 180μm, 190μm, 200μm, etc. Setting the distance d1 between one of the first passivated side portions 232 and the adjacent second passivated side portion 332 within 10μm-200μm is beneficial for forming a good insulating distance between the first passivated side portion 232 and the second passivated side portion 332, so as to effectively improve the insulation performance between the first conductive portion 2 and the second conductive portion 3 and prevent the reverse bias voltage from causing breakdown of the first conductive portion 2 and the second conductive portion 3.

[0070] To improve the absorption capacity of the back contact battery 100 for sunlight and reduce its reflection, please refer to [link / reference needed]. Figure 4 and Figure 5 In some embodiments, the first conductive portion 2 further includes a first antireflection layer 24, which is disposed on the side of the first passivation layer 23 opposite to the first doped layer 22, and a P-type main gate 41 is disposed on the first antireflection layer 24. The second conductive portion 3 further includes a second antireflection layer 34, which is disposed on the side of the second passivation layer 33 opposite to the second doped layer 32, and an N-type main gate 42 is disposed on the second antireflection layer 34. By providing the first antireflection layer 24 and the second antireflection layer 34 in the first conductive portion 2 and the second conductive portion 3 respectively, this application enables the back contact battery 100 to effectively absorb sunlight during use, enhances the absorption capacity of the back contact battery 100, and improves the energy conversion efficiency.

[0071] For example, the materials of the first antireflection layer 24 and the second antireflection layer 34 may be magnesium oxide, silicon oxide, aluminum oxide, titanium oxide, zinc oxide, etc.

[0072] Optionally, the first antireflection layer 24 extends from one surface of the first passivation layer 23 away from the substrate 1 to cover both sides of the first passivation layer 23 in the first direction X. The second antireflection layer 34 extends from one surface of the second passivation layer 33 away from the substrate 1 to cover both sides of the second dielectric layer 31 and the second doped layer 32 in the first direction X. Specifically, the first passivation layer 23 includes two first passivation side portions 232 in the first direction X, and a portion of the first antireflection layer 24 extends to the first passivation side portions 232, such that a portion of the first antireflection layer 24 covers the first passivation side portions 232. The second passivation layer 33 includes two second passivation side portions 332 in the first direction X, and a portion of the second antireflection layer 34 extends to the second passivation side portions 332, such that a portion of the second antireflection layer 34 covers the second passivation side portions 332.

[0073] For example, when the first conductive portion 2 and the second conductive portion 3 do not have the first antireflection layer 24 and the second antireflection layer 34 formed, taking the formation of the first antireflection layer 24 as an example, adjacent first passivated side portions 232 and second passivated side portions 332 are spaced apart in the first direction X to avoid space for the first antireflection layer 24 to be deposited, so that the first antireflection layer 24 can be formed on both sides of the first passivation layer 23 in the first direction X. The first antireflection layer 24 can be naturally formed on the first passivated side portions 242 and the first passivated surface portion 241 by chemical vapor deposition. The formation of the side portions of the second antireflection layer 34 is similar, and will not be described in detail here.

[0074] In the first direction X, the first antireflective layer 24, the first passivated side portion 232, the second antireflective layer 34, the second passivated side portion 332, and the spacing D can provide good insulation protection for the first conductive portion 2 and the second conductive portion 3, improve the insulation performance of the first conductive portion 2 and the second conductive portion 3, help prevent the first conductive portion 2 and the second conductive portion 3 from breaking down when a reverse bias voltage is applied, reduce the risk of leakage of the back contact battery 100, and improve the efficiency of the back contact battery 100.

[0075] Optionally, the first antireflection layer 24 includes a first antireflection surface portion 241 and two first antireflection side portions 242. The first antireflection surface portion 241 is stacked on the first passivation surface portion 231 along the thickness direction Z. The two first antireflection side portions 242 are respectively stacked on the two first passivation side portions 232 along the first direction X. The thickness of the two first antireflection side portions 242 in the first direction X is 20nm-200nm. The second antireflection layer 34 includes a second antireflection surface portion 341 and two second antireflection side portions 342. The second antireflection surface portion 341 is stacked on the second passivation surface portion 331 along the thickness direction Z. The two second antireflection side portions 342 are respectively stacked on the two second passivation side portions 332 along the first direction X. The thickness of the two second antireflection side portions 342 in the first direction X is 20nm-200nm.

[0076] In other words, the first anti-reflection side portion 242 is stacked on the first passivation side portion 232 along the first direction X, thereby increasing the thickness of the sidewall of the first conductive portion 2 in the first direction X. Similarly, the second anti-reflection side portion 342 stacked on the second passivation side portion 332 can also increase the thickness of the sidewall of the second conductive portion 3. In this way, the increased thickness of the sidewalls of the first conductive portion 2 and the second conductive portion 3 in the first direction X is beneficial to improving the insulation performance of the sidewalls of the first conductive portion 2 and the second conductive portion 3 in the first direction X, thereby helping to prevent the reverse bias voltage between the P-type main gate 41 and the N-type main gate 42 from causing breakdown of the first conductive portion 2 and the second conductive portion 3.

[0077] For example, the thickness of the first anti-reflection side portion 242 is L3, which can be 20nm-40nm, 30nm-50nm, 40nm-60nm, 50nm-70nm, 60nm-80nm, 70nm-90nm, 80nm-100nm, 90nm-110nm, 100nm-120nm, 110nm-130nm, 120nm-140nm, 130nm-150nm, 140nm-160nm, 150nm-170nm, 160nm-180nm, 170nm-190nm, or 180nm-200nm. For example, d1 can be 20nm, 30nm, 40nm, 50nm, 60nm, 70nm, 80nm, 90nm, 100nm, 110nm, 120nm, 130nm, 140nm, 150nm, 160nm, 170nm, 180nm, 190nm, 200nm, etc.

[0078] For example, the thickness of the second antireflective side portion 342 is L4, which can be 20nm-40nm, 30nm-50nm, 40nm-60nm, 50nm-70nm, 60nm-80nm, 70nm-90nm, 80nm-100nm, 90nm-110nm, 100nm-120nm, 110nm-130nm, 120nm-140nm, 130nm-150nm, 140nm-160nm, 150nm-170nm, 160nm-180nm, 170nm-190nm, or 180nm-200nm. For example, d1 can be 20nm, 30nm, 40nm, 50nm, 60nm, 70nm, 80nm, 90nm, 100nm, 110nm, 120nm, 130nm, 140nm, 150nm, 160nm, 170nm, 180nm, 190nm, 200nm, etc.

[0079] Optionally, when the first conductive portion 2 and the second conductive portion 3 are provided with the first anti-reflection side portion 242 and the second anti-reflection side portion 342 in the first direction X, in the first direction, one of the first anti-reflection side portions 242 and an adjacent second anti-reflection side portion 342 are adjacent and spaced apart, and the distance between them is d2, wherein 10μm≤d2≤200μm. For example, d2 can be 10μm-30μm, 20μm-40μm, 30μm-50μm, 40μm-60μm, 50μm-70μm, 60μm-80μm, 70μm-90μm, 80μm-100μm, 90μm-110μm, 100μm m-120μm, 110μm-130μm, 120μm-140μm, 130μm-150μm, 140μm-160μm, 150μm-170μm, 160μm-180μm, 170μm-190μm, 180μm-200μm. For example, d2 can be 10μm, 20μm, 30μm, 40μm, 50μm, 60μm, 70μm, 80μm, 90μm, 100μm, 110μm, 120μm, 130μm, 140μm, 150μm, 160μm, 170μm, 180μm, 190μm, 200μm, etc. Setting the distance d2 between one of the first antireflective side portions 242 and the adjacent second antireflective side portion 342 within 10μm-200μm is beneficial for forming a good insulating distance between the first antireflective side portion 242 and the second antireflective side portion 342, so as to effectively improve the insulation performance between the first conductive portion 2 and the second conductive portion 3 and prevent the reverse bias voltage from causing breakdown of the first conductive portion 2 and the second conductive portion 3.

[0080] Because different materials of the passivation layer and antireflection layer have different voltage withstand capabilities at different thicknesses, in some embodiments, the dielectric strength of the first passivation layer 23 and the second passivation layer 33 can both be E1, the dielectric strength of the first antireflection layer 24 and the second antireflection layer 34 can both be E2, the dielectric strength of the air at the spacing D can be E3, and the reverse bias voltage is V. The relationship between the antireflection layer, the passivation layer, the spacing D, and the reverse bias voltage can satisfy the following equation: E1*L1+E1*L2+E2*L3+E2*L4+E3*D>V. That is, in the first direction X, the voltage withstand capability formed by the first passivation side portion 232, the second passivation side portion 332, the first antireflection side portion 242, the second antireflection side portion 342, and the spacing D can be greater than the reverse bias voltage applied to the back contact battery 100. This helps to reduce the risk of the first conductive portion 2 and the second conductive portion 3 being broken down when a reverse bias voltage is applied.

[0081] In some embodiments, a P-type main gate 41 is sequentially disposed along the thickness direction Z through a first antireflection layer 24 and a first passivation layer 23, and is connected to a first doped layer 22. An N-type main gate 42 is disposed along the thickness direction Z through a second antireflection layer 34 and a second passivation layer 33, and is connected to a second doped layer 32. It is understood that the first and second doped layers typically contain crystalline silicon. Taking a P-type main gate as an example, after the P-type main gate is connected to the first doped layer, the silver material in the P-type main gate can form a silver-silicon alloy layer with the crystalline silicon in the first doped layer 22, which helps to reduce the contact resistance between the P-type main gate 41 and the first doped layer 22, and is beneficial to improving battery efficiency.

[0082] Please see Figure 6 In some embodiments, the electrode structure 4 further includes multiple P-type fine grids 43 and multiple N-type fine grids 44. A P-type main grid 41 is connected to multiple P-type fine grids 43, and an N-type main grid 42 is connected to multiple N-type fine grids 44. Between adjacent P-type main grids 41 and N-type main grids 42, multiple P-type fine grids 43 and multiple N-type fine grids 44 are alternately arranged along the second direction Y. During use of the back contact battery 100, the multiple P-type fine grids 43 and multiple N-type fine grids 44 can collect the current generated at various points on the back contact battery 100 onto the P-type main grid 41 and N-type main grid 42. Moreover, the alternating arrangement of multiple P-type fine grids 43 and multiple N-type fine grids 44 facilitates further current collection and improves the efficiency of the back contact battery 100.

[0083] Please see Figure 7Specifically, when the front side of the back contact battery 100 is laser-scanned and a reverse bias voltage is applied to the back side, the P-type fine gate 43 located in the first antireflection layer 24 is burned through the first antireflection layer 24 and the first passivation layer 23 under laser induction, and then connects with the first doped layer 22. When the P-type fine gate 43 is connected to the first doped layer 22, a large amount of heat is generated at the contact interface between the P-type fine gate 43 and the first doped layer 22. As a result, the silver material in the P-type fine gate 43 is dispersed into nanoparticles and melted into the first doped layer 22, so that the silver nanoparticles and the silicon material in the first doped layer 22 form a silver-silicon alloy layer, and finally, silver nanodendritic crystals with excellent conductivity are formed in the first doped layer 22. The formation of silver nanodendritic crystals helps to reduce the contact resistance when the P-type fine gate 43 and the first doped layer 22 are connected, thereby improving the efficiency of the back contact battery 100. Similarly, the N-type fine gate 44 is connected to the second doped layer 32 under the support of reverse bias voltage and the induction of laser, and silver nanodendrons are formed in the second doped layer 32, which will not be described in detail here.

[0084] In other words, silver nanodendrons are present at the junctions of the first doped layer 22 with the P-type fine gate 43 and the second doped layer 32 with the N-type fine gate 44.

[0085] To further understand the specific solution of this application, the production process of a back contact battery is used as an example for illustration:

[0086] S1. Clean the substrate containing doped elements;

[0087] S2. Deposit a second dielectric layer on the back side of the substrate, and then deposit an intrinsic polysilicon layer on the second dielectric layer.

[0088] S3. The silicon wafer processed in the above steps is subjected to a second doping treatment, so that the intrinsic polycrystalline silicon layer forms a second doped layer, and a glass layer is also formed on the surface of the second doped layer.

[0089] S4. Remove the glass layer on the surface of the second doped layer by laser scanning to form the second conductive portion;

[0090] S5. Clean the silicon wafer after laser scanning;

[0091] S6. Sequentially deposit a first dielectric layer and an intrinsic polysilicon layer on the back side of the cleaned silicon wafer substrate;

[0092] S7. The silicon wafer processed in the above steps is subjected to a first doping treatment, so that the intrinsic polycrystalline silicon layer deposited in S6 forms a first doped layer, and a glass layer is also formed on the surface of the first doped layer.

[0093] S8. A glass layer on the surface of the first doped layer is removed by laser processing to form a first conductive portion. Then, a gap D is opened between the first conductive portion and the second conductive portion by laser, so that the first conductive portion and the second conductive portion are spaced apart in the first direction.

[0094] S9. Clean the silicon wafer after S8 treatment and form a textured surface on the front side of the substrate;

[0095] S10. Passivation layers are formed on the front and back sides of the silicon wafer, so that the first passivation layer and the second passivation layer are formed on the surface of the first doped layer and the second doped layer. In the first direction, passivation layer sidewalls are formed on the sides of the first doped layer, the first dielectric layer, the second doped layer and the second dielectric layer, and the thickness of the passivation layer sidewalls is controlled.

[0096] S11. A first antireflection layer and a second antireflection layer are formed on the surfaces of the first passivation layer and the second passivation layer. Antireflection layer sidewalls are formed on the sides of the first passivation layer and the second passivation layer in the first direction, and the thickness of the antireflection layer sidewalls is controlled. That is to say, the first conductive part and the second conductive part both have passivation layers and antireflection layers on their sides in the first direction.

[0097] S12. Print P-type main gate and fine gate and N-type main gate and fine gate on the first conductive part and the second conductive part (on the anti-reflection layer), respectively;

[0098] S13. Laser scanning is performed on the front side of the silicon wafer, and a reverse bias voltage is applied between the P-type main gate and the N-type main gate on the back side, so that the P-type fine gate burns through the first conductive part and connects to the first doped layer, and the N-type fine gate burns through the second conductive part and connects to the second doped layer.

[0099] To verify the reliability of the back contact battery of this application, a comparative experiment was conducted using 100 back contact batteries as an example. The specific results are shown in Table 1:

[0100] Table 1

[0101]

[0102] In Table 1 above, Condition 1 involves using the back-contact battery of this application, performing laser scanning on the front side of the back-contact battery, and applying a reverse bias voltage of 10V-30V to the back side. Condition 2 involves using a conventional back-contact battery and undergoing light injection processing. Furthermore, in Table 1, Eff represents the battery efficiency, Voc represents the open-circuit voltage, Isc represents the short-circuit current, Jsc represents the photovoltaic cell's output short-circuit current density under illumination, FF represents the fill factor, Rsh represents the parallel resistance, Rs represents the series resistance, and Irev2 represents the reverse current at -12V.

[0103] As shown in Table 1 above, under condition 1, primarily referring to the battery efficiency Eff, the battery efficiency of the back contact battery in this application is improved by 0.09%. In the field of solar cells, a battery efficiency improvement of 0.1%-0.2% is already a significant improvement. Therefore, the 0.09% improvement in battery efficiency of the back contact battery in this application is a substantial improvement.

[0104] In summary, the back contact battery disclosed in this application effectively improves the contact resistance between the electrode and the battery, and significantly enhances the efficiency of the back contact battery.

[0105] The back contact battery disclosed in the embodiments of this application has been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the back contact battery and its core ideas. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A back-contact battery, characterized in that, include: A substrate having a front side and a back side along the thickness direction, the front side being configured for laser scanning; Multiple first conductive portions and multiple second conductive portions are provided on the back side. Each first conductive portion and each second conductive portion are alternately spaced along a first direction, and the first conductive portion and the second conductive portion extend along a second direction. An electrode structure is provided, comprising multiple P-type main gates and multiple N-type main gates. Each P-type main gate is respectively disposed on the side of each first conductive portion away from the back surface, and each N-type main gate is respectively disposed on the side of each second conductive portion away from the back surface. The P-type main gate is configured to be connected to the negative terminal of the power supply, and the N-type main gate is configured to be connected to the positive terminal of the power supply. Wherein, the first direction intersects with the second direction.

2. The back contact battery as described in claim 1, characterized in that, Along the first direction, the spacing between adjacent first conductive portions and second conductive portions is 10μm-200μm.

3. The back contact battery as described in claim 1, characterized in that, The first conductive portion includes a first dielectric layer, a first doped layer, and a first passivation layer stacked sequentially in a direction away from the substrate, and the P-type main gate is disposed on the first passivation layer; The second conductive portion includes a second dielectric layer, a second doped layer, and a second passivation layer stacked sequentially in a direction away from the substrate, and the N-type main gate is disposed on the second passivation layer.

4. The back contact battery as described in claim 3, characterized in that, The first passivation layer extends from one side of the first doped layer away from the substrate to cover the first dielectric layer and the two sides of the first doped layer in the first direction; The second passivation layer extends from one side of the second doped layer away from the substrate to cover the second dielectric layer and the two sides of the second doped layer in the first direction.

5. The back contact battery as described in claim 4, characterized in that, The first passivation layer includes a first passivation surface portion and two first passivation side portions. The first passivation surface portion is located on one side surface of the first doped layer in the direction away from the substrate. The two first passivation side portions are respectively located on the two sides of the first dielectric layer and the first doped layer in the first direction. The second passivation layer includes a second passivation surface portion and two second passivation side portions. The second passivation surface portion is located on one side surface of the second doped layer in the direction away from the substrate. The two second passivation side portions are respectively located on the two sides of the second dielectric layer and the second doped layer in the first direction. The thickness of each of the two first passivated side portions in the first direction is 1nm-20nm, and the thickness of each of the two second passivated side portions in the first direction is 1nm-20nm; and / or, In the first direction, the distance between one of the first passivated side portions and an adjacent second passivated side portion is d1, wherein 10μm≤d1≤200μm.

6. The back contact battery as described in claim 5, characterized in that, The first conductive portion further includes a first antireflection layer, which is disposed on the side of the first passivation layer opposite to the first doped layer, and the P-type main gate is disposed on the first antireflection layer; and The second conductive portion further includes a second antireflection layer, which is disposed on the side of the second passivation layer away from the second doped layer, and the N-type main gate is disposed on the second antireflection layer.

7. The back contact battery as described in claim 6, characterized in that, The first antireflection layer extends from one side of the first passivation layer away from the substrate to cover both sides of the first passivation layer in the first direction; The second antireflection layer extends from one side of the second passivation layer away from the substrate to cover both sides of the second dielectric layer and the second doped layer in the first direction.

8. The back contact battery as described in claim 7, characterized in that, The first antireflection layer includes a first antireflection surface portion and two first antireflection side portion. The first antireflection surface portion is stacked on the first passivation surface portion along the thickness direction, and the two first antireflection side portion are respectively stacked on the two first passivation side portion along the first direction. The second antireflection layer includes a second antireflection surface portion and two second antireflection side portion. The second antireflection surface portion is stacked on the second passivation surface portion along the thickness direction, and the two second antireflection side portion are respectively stacked on the two second passivation side portion along the first direction. The thickness of both first antireflective side portions in the first direction is 20nm-200nm, and the thickness of both second antireflective side portions in the first direction is 20nm-200nm; and / or In the first direction, the distance between one of the first antireflective side portions and an adjacent second antireflective side portion is d2, wherein 10μm≤d2≤200μm.

9. The back contact battery as described in any one of claims 6-8, characterized in that, The electrode structure further includes multiple P-type fine gates and multiple N-type fine gates. The P-type fine gates are connected to the P-type main gate, and the N-type fine gates are connected to the N-type main gate. Each P-type fine gate and each N-type fine gate are alternately spaced along the second direction. The P-type fine gates are sequentially disposed through the first antireflection layer and the first passivation layer along the thickness direction, and the P-type fine gates are connected to the first doped layer. The N-type fine gate is disposed along the thickness direction in the second antireflection layer and the second passivation layer, and the N-type fine gate is connected to the second doped layer.

10. The back contact battery as described in any one of claims 3-8, characterized in that, The doping concentration of the first doped layer is greater than that of the second doped layer.

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