Low-noise power supply chip with overvoltage current-limiting protection function

Abstract

The utility model provides a low-noise power supply chip with an overvoltage current-limiting protection function in the technical field of optical modules. Comprising a logic controller U1, an overvoltage protection chip U2, a current limiting protection chip U3, a logic gate control chip U4, a logic gate control chip U5, a power management chip U6, a discharge chip U7, an operational amplifier OP1, an operational amplifier OP2, an inductor L1, a PMOS tube Q1, an NMOS tube Q2, an NMOS tube Q3, a PMOS tube Q4, an NMOS tube Q5, an NMOS tube Q6, a capacitor C1, a capacitor C2, a resistor R1, a resistor R2, a power input terminal J1, a working mode selection terminal J2, a chip enabling terminal J3, a voltage ready terminal J4, a grounding terminal J5 and a voltage debugging terminal J6. A power supply output terminal J7, a switch terminal J8, a switch terminal J9 and a reference voltage chip U8. The low-noise power supply circuit has the advantages that the power consumption and the cost of the low-noise power supply circuit are greatly reduced, the integration level of a chip is improved, the use of the chip is reduced, and the PCB layout space of a product is effectively saved.

Description

TECHNICAL FIELD

[0001] The utility model relates to optical module technical field, especially point to a kind of low-noise power supply chip with overvoltage current-limiting protection function. BACKGROUND

[0002] Optical module is photoelectric conversion and electro-optical conversion optoelectronic device, according to the protocol and specification of optical module, the total power input of optical module is generally 3.3V voltage, and 3.3V voltage needs to be converted into multiple different power supply voltages of different levels inside optical module to power different subsystems inside optical module, such as 0.65V, 0.94V, 1.2V, 1.8V, 2.5V, 3.3V, 4V, 5V voltage.

[0003] To realize the voltage conversion of different levels, multiple different power conversion chips will be used inside optical module, and a part of subsystems have high requirements for voltage stability and power supply noise (power supply ripple), such as DSP power supply circuit, clock source, reference level loop, especially with the rate of optical module being improved to 400G&800G&1.6T, the requirement for power supply noise is more stringent, and multiple subsystems require power supply ripple to be controlled below 1mV, and conventional boost (BOOST) power supply chip or buck (DC-DC) power supply chip cannot meet the power supply ripple requirement, so a low-noise power supply chip such as LDO needs to be used after power conversion chip to adjust voltage and control ripple, so as to ensure that power supply ripple meets the design requirement.

[0004] The low-noise power supply circuit used in traditional optical module generally has the following two power supply loops: loop one is a power supply loop with low-noise requirement and greater than 3.3V, and loop two is a power supply loop with low-noise requirement and less than 3.3V. Loop one is composed of a first boost module (refer to Figure 2 ) and a first buck module (refer to Figure 3 ); loop two is composed of a second buck module (refer to Figure 4 ) and a third buck module (refer to Figure 5 ).

[0005] The working principle of loop one from 3.3V to 4V is as follows: by adjusting the resistance value of resistor R12 and resistor R13, 3.3V power supply is boosted to 5V in combination with power supply chip U11 (BOOST chip); by adjusting the resistance value of resistor R15 and resistor R16, 5V power supply is reduced to 4V in combination with power supply chip U12 (LDO chip). VCC5V_EN and VCC4V_EN are used as upper computer control signals to control the enablement of power supply chip U11 and power supply chip U12 to work.

[0006] The working principle of the loop two from 3.3V to 1.2V is as follows: 3.3V power supply is reduced to 1.8V by adjusting the resistance values of resistors R18 and R19 and combining the power supply chip U21 (DC-DC chip); 1.8V power supply is reduced to 1.2V by adjusting the resistance values of resistors R21 and R2 and combining the power supply chip U22 (LDO chip). VCC1V8_EN and VCC1V2_EN are used as upper computer control signals and are used for controlling the power supply chips U21 and U22 to work.

[0007] The traditional low-noise power supply circuit has the following disadvantages: 1. For the needs of voltage increase and voltage reduction, different power supply chips are needed to first perform voltage increase or voltage reduction processing, the voltage increase and voltage reduction circuits are not compatible, the number of chip materials is increased, and thus the circuit cost is increased; 2. The power supply chips of the first power supply (the first voltage increase module and the second voltage reduction module) and the second power supply (the first voltage reduction module and the third voltage reduction module) need to be controlled respectively, in order to keep the circuit stable, the output voltage of the first power supply needs to have sufficient margin, which increases the voltage difference of the LDO chip of the second power supply; since the working principle of the LDO chip is to keep the input and output currents the same, the LDO chip is controlled to work, so as to achieve the goal of stable voltage drop and low noise, thus the energy loss caused by the voltage difference between the output end and the input end of the LDO chip in the loop will be all the heat dissipation of the LDO chip, which causes the LDO chip to generate more heat; 3. The power supply chips of the first power supply and the second power supply need to be controlled independently, and the upper computer IO output EN signal is needed for controlling the power supply chips to work, that is, a large number of IO resources are occupied, and the circuit cost is increased.

[0008] Therefore, how to provide a low-noise power supply chip with overvoltage current limiting protection function, and reduce the power consumption and cost of the low-noise power supply circuit, has become a technical problem to be solved. SUMMARY

[0009] The technical problem to be solved by the utility model lies in providing a low-noise power supply chip with overvoltage current limiting protection function, and reducing the power consumption and cost of the low-noise power supply circuit.

[0010] The utility model discloses a low -noise power supply chip with overvoltage protection current -limiting protection function, including a logic controller U1, an overvoltage protection chip U2, a current -limiting protection chip U3, a logic gate control chip U4, a logic gate control chip U5, a power management chip U6, a discharge chip U7, an operational amplifier OP1, an operational amplifier OP2, an inductance L1, a PMOS tube Q1, a NMOS tube Q2, a NMOS tube Q3, a PMOS tube Q4, a NMOS tube Q5, a NMOS tube Q6, a capacitor C1, a capacitor C2, a resistance R1, a resistance R2, a power input terminal J1, a working mode selection terminal J2, a chip enable terminal J3, a voltage ready terminal J4, a ground terminal J5, a voltage debugging terminal J6, a power output terminal J7, a switch terminal J8, a switch terminal J9 and a reference voltage chip U8;

[0011] The power input terminal J1, the working mode selection terminal J2, the chip enable terminal J3, the voltage ready terminal J4, the ground terminal J5, the voltage debugging terminal J6, the power output terminal J7, the switch terminal J8, the switch terminal J9 and the power input terminal J1 are sequentially connected.

[0012] One end of the inductance L1 is connected with the switch terminal J8, and the other end is connected with the switch terminal J9;One end of the overvoltage protection chip U2 is connected with the logic controller U1, and the other end is connected with the power input terminal J1 and the S pole of the PMOS tube Q1;One end of the logic gate control chip U4 is connected with the logic controller U1, and the other end is connected with the G pole of the PMOS tube Q1;The G pole of the NMOS tube Q2 is connected with the logic gate control chip U4, the S pole is connected with the D pole of the PMOS tube Q1 and the switch terminal J9, and the D pole is connected with the ground terminal J5;The G pole of the NMOS tube Q3 is connected with the logic gate control chip U5, the S pole is connected with the D pole of the PMOS tube Q4 and the switch terminal J8, and the D pole is connected with the ground terminal J5;One end of the logic gate control chip U5 is connected with the logic controller U1, and the other end is connected with the G pole of the PMOS tube Q4;One end of the capacitor C1 is connected with the S pole of the PMOS tube Q4 and the current -limiting protection chip U3, and the other end is connected with the ground terminal J5;

[0013] The pin 1 of the operational amplifier OP2 is connected with the G pole of the NMOS tube Q5, the pin 2 is connected with the pin 2 of the operational amplifier OP1, one end of the capacitor C2, one end of the resistor R1, one end of the resistor R2 and the voltage debugging terminal J6, the pin 4 is connected with the current limiting protection chip U3, and the pin 5 is connected with the logic controller U1 and the discharge chip U7; the D pole of the NMOS tube Q5 is connected with the current limiting protection chip U3, the S pole is connected with the discharge chip U7, the other end of the capacitor C2, the other end of the resistor R1 and the power output terminal J7; the other end of the resistor R2 is connected with the ground terminal J5; the pin 1 of the operational amplifier OP1 is connected with the logic controller U1; one end of the power management chip U6 is connected with the logic controller U1, and the other end is connected with the G pole of the NMOS tube Q6; the S pole of the NMOS tube Q6 is connected with the ground terminal J5, and the D pole is connected with the voltage ready terminal J4; the working mode selection terminal J2 and the chip enable terminal J3 are all connected with the logic controller U1; the reference voltage chip U8 is connected with the pin 3 of the operational amplifier OP1 and the pin 3 of the operational amplifier OP2.

[0014] Further, the pin 1 of the operational amplifier OP1 is an output pin, the pin 2 is a negative input pin, and the pin 3 is a positive input pin.

[0015] Further, the pin 1 of the operational amplifier OP2 is an output pin, the pin 2 is a negative input pin, the pin 3 is a positive input pin, the pin 4 is a positive side power pin, and the pin 5 is a negative side power pin.

[0016] The utility model discloses the advantages are in:

[0017] By setting up low noise power supply chip including logic controller U1, overvoltage protection chip U2, current limiting protection chip U3, logic gate control chip U4, logic gate control chip U5, power management chip U6, discharge chip U7, two operational amplifiers, inductance L1, six MOS tubes, two capacitors, two resistors, nine terminals, the logic controller U1 can control the break -make of MOS tube Q1, MOS tube Q2, MOS tube Q3, MOS tube Q4 through logic gate control chip U4 and logic gate control chip U5 to carry out the switching of boost mode and buck mode, so that low noise power supply chip can be compatible with the demand of boost and buck, need not extra use different power supply chip to handle, reduced the material type of chip, also reduced the occupied number of host computer IO resource, can reduce PCB board area simultaneously, through feedback loop (operational amplifier OP2, resistance R1, resistance R2, capacitor C2), the current size and voltage level of MOS tube Q5 are adjusted in real time, need not like traditional one -level output voltage to keep enough margin, effectively reduces the pressure difference of MOS tube Q5, to reduce the heat power consumption, finally greatly reduces the power consumption and cost of low noise power supply circuit, reduces chip use can greatly save product PCB's board space. Attached Figure Description

[0018] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0019] Figure 1 This is a circuit diagram of a low-noise power supply chip with overvoltage and current limiting protection function according to this utility model.

[0020] Figure 2 This is the circuit diagram of the first boost module of the traditional circuit one.

[0021] Figure 3 This is the circuit diagram of the first step-down module in the traditional circuit.

[0022] Figure 4 This is the circuit diagram of the second step-down module in the traditional loop 2.

[0023] Figure 5 This is the circuit diagram of the third step-down module of the traditional loop two. Detailed Implementation

[0024] The overall concept of the technical solution in this application embodiment is as follows: The switching of PMOS transistors Q1, Q2, Q3, and Q4 is controlled by logic gate control chips U4 and U5 to switch between boost and buck modes. This allows the low-noise power supply chip to be compatible with both boost and buck requirements without the need for additional power supply chips, reducing the types of chip components and the amount of I / O resources required by the host computer, while also reducing the PCB area. The feedback loop adjusts the current and voltage level of NMOS transistor Q5 in real time, eliminating the need for a sufficient margin in the first-stage output voltage as in traditional methods. This effectively reduces the voltage drop across NMOS transistor Q5, lowering heat dissipation and thus reducing the power consumption and cost of the low-noise power supply circuit.

[0025] Please refer to Figures 1 to 5The utility model discloses a preferable embodiment of low noise power supply chip with overvoltage protection and current limiting protection function, including a logic controller U1, an overvoltage protection chip U2, a current limiting protection chip U3, a logic gate control chip U4, a logic gate control chip U5, a power management chip U6, a discharge chip U7, an operational amplifier OP1, an operational amplifier OP2, an inductor L1, a PMOS tube Q1, an NMOS tube Q2, an NMOS tube Q3, a PMOS tube Q4, an NMOS tube Q5, an NMOS tube Q6, a capacitor C1, a capacitor C2, a resistance R1, a resistance R2, a power input terminal J1, a working mode selection terminal J2, a chip enable terminal J3, a voltage ready terminal J4, a ground terminal J5, a voltage debugging terminal J6, a power output terminal J7, a switch terminal J8, a switch terminal J9 and a reference voltage chip U8,

[0026] The logic controller U1 is used for connecting external interface (J2, J3) and logic control, that is, collecting and processing external interface and internal function control signal, and outputting corresponding logic control level, finally making low noise power supply chip output target required output voltage, which collects the signal of each subcircuit through IO port, processes through internal signal logic, and then outputs different levels through the IO port of connecting subcircuit to control the work of corresponding chip and subcircuit, when specifically implementing, the chip that can realize the function can be selected, and is not limited to any type, for example, the logic controller of model SN74LS00D is selected, and the control program is well known to those skilled in the art, which is obtained by those skilled in the art without creative labor;

[0027] The overvoltage protection chip U2 and the current limiting protection chip U3 are used for self-protection of low noise power supply chip, prevent low noise power supply chip from being abnormally damaged during use, when specifically implementing, the chip that can realize the function can be selected, and is not limited to any type, for example, the overvoltage protection chip of model WS3202E61-6 / TR is selected, the current limiting protection chip of model ME6231 C36N4CG is selected, and the control program is well known to those skilled in the art, which is obtained by those skilled in the art without creative labor;

[0028] The logic gate control chip U4 and the logic gate control chip U5 are used for controlling the working mode (PWM / PFM) of the PMOS tube Q1, the NMOS tube Q2, the NMOS tube Q3 and the PMOS tube Q4, the logic gate control chip U4 controls the turn-on and turn-off of the PMOS tube Q1 and the NMOS tube Q2, and the logic gate control chip U5 controls the turn-on and turn-off of the NMOS tube Q3 and the PMOS tube Q4; in the specific implementation, a chip capable of realizing the function can be selected, and is not limited to a specific model, for example, the logic gate control chip with the model number SN74LS00D is selected, and the control program is well known to those skilled in the art, which is obtained by those skilled in the art without creative labor;

[0029] The power management chip U6 is used for outputting a chip ready signal to the outside when the low-noise power supply chip normally outputs a target voltage according to the set requirement; in the specific implementation, an operational amplifier capable of realizing the function can be selected, and is not limited to a specific model, for example, the power management chip with the model number BQ25790 is selected;

[0030] The discharge chip U7 is used for discharging after the low-noise power supply chip is turned off, so as to protect the safety of the low-noise power supply chip and the external loop; in the specific implementation, a chip capable of realizing the function can be selected, and is not limited to a specific model, for example, the discharge chip with the model number UN3E6-230M is selected;

[0031] The reference voltage chip U8 is used for providing the reference voltage (reference level) of the operational amplifier OP1 and the operational amplifier OP2; in the specific implementation, a chip capable of realizing the function can be selected, and is not limited to a specific model, for example, the reference voltage chip with the model number TL4050A41IDBZR is selected;

[0032] The operational amplifier OP1 and the operational amplifier OP2 are used for performing logic operation on the level input through the voltage debugging terminal J6 and the reference voltage, and outputting a level signal to the logic controller U1 and the NMOS tube Q5, so as to control the output voltage of the low-noise power supply chip; in the specific implementation, an operational amplifier capable of realizing the function can be selected, and is not limited to a specific model, for example, the operational amplifier with the model number LM324 is selected;

[0033] The power input terminal J1 is used for chip power input; the working mode selection terminal J2 is used for switching the working mode of the chip including PWM (pulse width modulation) and PFM (pulse frequency modulation); the chip enable terminal J3 is used for controlling the chip to open and close through high and low levels; the voltage ready terminal J4 is used for outputting the working state of the chip, that is, after the chip normally outputs the target voltage, outputting the ready signal through the voltage ready terminal J4; the voltage debugging terminal J6 is used for adjusting the size of the output voltage; the power output terminal J7 is used for chip power output; the switch terminal J8 and the switch terminal J9, that is, the SW pin;

[0034] The power input terminal J1, the working mode selection terminal J2, the chip enable terminal J3, the voltage ready terminal J4, the ground terminal J5, the voltage debugging terminal J6, the power output terminal J7, the switch terminal J8, the switch terminal J9 and the power input terminal J1 are connected in sequence;

[0035] One end of the inductor L1 is connected with the switch terminal J8, and the other end is connected with the switch terminal J9; one end of the overvoltage protection chip U2 is connected with the logic controller U1, and the other end is connected with the power input terminal J1 and the S pole of the PMOS tube Q1; one end of the logic gate control chip U4 is connected with the logic controller U1, and the other end is connected with the G pole of the PMOS tube Q1; the G pole of the NMOS tube Q2 is connected with the logic gate control chip U4, the S pole is connected with the D pole of the PMOS tube Q1 and the switch terminal J9, and the D pole is connected with the ground terminal J5; the G pole of the NMOS tube Q3 is connected with the logic gate control chip U5, the S pole is connected with the D pole of the PMOS tube Q4 and the switch terminal J8, and the D pole is connected with the ground terminal J5; one end of the logic gate control chip U5 is connected with the logic controller U1, and the other end is connected with the G pole of the PMOS tube Q4; one end of the capacitor C1 is connected with the S pole of the PMOS tube Q4 and the current limiting protection chip U3, and the other end is connected with the ground terminal J5;

[0036] Pin 1 of the OP2 is connected with the G pole of the NMOS tube Q5, pin 2 is connected with pin 2 of the OP1, one end of the capacitor C2, one end of the resistor R1, one end of the resistor R2 and the voltage debugging terminal J6, pin 4 is connected with the current limiting protection chip U3, pin 5 is connected with the logic controller U1 and the discharge chip U7; the D pole of the NMOS tube Q5 is connected with the current limiting protection chip U3, the S pole is connected with the discharge chip U7, the other end of the capacitor C2, the other end of the resistor R1 and the power output terminal J7; the other end of the resistor R2 is connected with the ground terminal J5; pin 1 of the OP1 is connected with the logic controller U1; one end of the power management chip U6 is connected with the logic controller U1, and the other end is connected with the G pole of the NMOS tube Q6; the S pole of the NMOS tube Q6 is connected with the ground terminal J5, and the D pole is connected with the voltage ready terminal J4; the working mode selection terminal J2 and the chip enable terminal J3 are all connected with the logic controller U1; the reference voltage chip U8 is connected with pin 3 of the OP1 and pin 3 of the OP2.

[0037] Pin 1 of the OP1 is an output pin, pin 2 is a negative input pin, and pin 3 is a positive input pin.

[0038] Pin 1 of the OP2 is an output pin, pin 2 is a negative input pin, pin 3 is a positive input pin, pin 4 is a positive side power pin, and pin 5 is a negative side power pin.

[0039] The utility model working principle:

[0040] Boost mode:

[0041] 1, the power input terminal J1 is connected with the power supply, the logic controller U1 is started through the chip enable terminal J3, is modulated as the working mode of PWM through the input signal of the working mode selection terminal J2, and the PWM waveform of the output target duty ratio D controls the logic gate control chip U4 and the logic gate control chip U5;

[0042] 2, the logic gate control chip U4 controls the PMOS tube Q1 to keep on according to the PWM waveform, and controls the NMOS tube Q2 to keep off;

[0043] 3, the logic gate control chip U5 controls the conduction and off of the NMOS tube Q3 and the PMOS tube Q4 according to the PWM waveform, and the voltage V1 of the PMOS tube Q4 output can be obtained according to the voltage balance law V1 of the inductor L1 = Vi n / (1-D);

[0044] 4, because the voltage V1 ripple is large, filtering treatment is carried out through the capacitor C1;

[0045] 5. In order to further obtain lower noise output voltage Vout, NMOS Q5 and OP2 real-time according to the reference voltage chip U8 output reference voltage and target voltage adjustment level difference forming feedback loop (OP2, R1, R2, C2), real-time adjustment of the current size and voltage level of NMOS Q5, thereby obtaining low noise stable output voltage Vout;

[0046] Wherein Vout=V1=Vin / (1-D), wherein Vout is output voltage, Vin is input voltage, and D is the duty cycle of the PWM mode waveform.

[0047] Buck mode:

[0048] 1. The power input terminal J1 is connected to the power supply, and the logic controller U1 is started through the chip enable terminal J3, and the input signal of the working mode selection terminal J2 is modulated as the working mode of PWM, and the output target duty cycle D PWM waveform controls the logic gate control chip U4 and the logic gate control chip U5.

[0049] 2. The logic gate control chip U4 controls the conduction and disconnection of the PMOS Q1 and the NMOS Q2 according to the PWM waveform; according to the voltage voltage balance law Vout=Vin*D of the inductor L1, the voltage V1 output by the PMOS Q4 can be obtained.

[0050] 3. The logic gate control chip U5 controls the NMOS Q3 to keep off according to the PWM waveform, and controls the PMOS Q4 to keep on.

[0051] 4. Since the voltage V1 ripple is large, the capacitor C1 is used for filtering processing.

[0052] 5. In order to further obtain lower noise output voltage Vout, NMOS Q5 and OP2 real-time according to the reference voltage chip U8 output reference voltage and target voltage adjustment level difference forming feedback loop (OP2, R1, R2, C2), real-time adjustment of the current size and voltage level of NMOS Q5, thereby obtaining low noise stable output voltage Vout;

[0053] Wherein Vout=V1=Vin*D, wherein Vout is output voltage, Vin is input voltage, and D is the duty cycle of the PWM mode waveform.

[0054] In summary, the advantages of the utility model lie in:

[0055] By setting low noise power supply chip including logic controller U1, overvoltage protection chip U2, current limiting protection chip U3, logic gate control chip U4, logic gate control chip U5, power management chip U6, discharge chip U7, two operational amplifiers, inductor L1, six MOS tubes, two capacitors, two resistors, nine terminals, logic controller U1 can control the on-off of MOS tube Q1, MOS tube Q2, MOS tube Q3, MOS tube Q4 through logic gate control chip U4 and logic gate control chip U5, to switch the boost mode and the buck mode, so that the low noise power supply chip can be compatible with the demand of boost and buck, without additional use of different power supply chips for processing, reducing the material type of chip, also reducing the number of IO resources occupied by the host computer, while reducing the PCB board area; through the feedback loop (operational amplifier OP2, resistor R1, resistor R2, capacitor C2), the current size and voltage level of MOS tube Q5 are adjusted in real time, without maintaining the output voltage of the first stage enough margin like the traditional, effectively reducing the voltage difference of MOS tube Q5, to reduce the heat dissipation, finally greatly reducing the power consumption and cost of low noise power supply circuit, while reducing the use of chip can greatly save the PCB layout space of product.

[0056] Although the specific embodiments of the present application are described above, those skilled in the art should understand that the specific examples described are only illustrative, and are not intended to limit the scope of the present application, and equivalent modifications and changes made by those skilled in the art in accordance with the spirit of the present application should be covered within the scope of the claims of the present application.

Claims

1. A low-noise power supply chip with overvoltage and current limiting protection, characterized in that: The application relates to a power management chip, which comprises a logic controller U1, an overvoltage protection chip U2, a current-limiting protection chip U3, a logic gate control chip U4, a logic gate control chip U5, a power management chip U6, a discharge chip U7, an operational amplifier OP1, an operational amplifier OP2, an inductor L1, a PMOS tube Q1, an NMOS tube Q2, an NMOS tube Q3, a PMOS tube Q4, an NMOS tube Q5, an NMOS tube Q6, a capacitor C1, a capacitor C2, a resistor R1, a resistor R2, a power input terminal J1, a working mode selection terminal J2, a chip enabling terminal J3, a voltage ready terminal J4, a grounding terminal J5, a voltage debugging terminal J6, a power output terminal J7, a switch terminal J8, a switch terminal J9 and a reference voltage chip U8. The power input terminal J1, the working mode selection terminal J2, the chip enabling terminal J3, the voltage ready terminal J4, the grounding terminal J5, the voltage debugging terminal J6, the power output terminal J7, the switch terminal J8, the switch terminal J9 and the power input terminal J1 are sequentially connected. One end of the inductor L1 is connected with the switch terminal J8, and the other end is connected with the switch terminal J9; one end of the overvoltage protection chip U2 is connected with the logic controller U1, and the other end is connected with the power input terminal J1 and the S pole of the PMOS tube Q1; one end of the logic gate control chip U4 is connected with the logic controller U1, and the other end is connected with the G pole of the PMOS tube Q1; the G pole of the NMOS tube Q2 is connected with the logic gate control chip U4, the S pole is connected with the D pole of the PMOS tube Q1 and the switch terminal J9, and the D pole is connected with the grounding terminal J5; the G pole of the NMOS tube Q3 is connected with the logic gate control chip U5, the S pole is connected with the D pole of the PMOS tube Q4 and the switch terminal J8, and the D pole is connected with the grounding terminal J5; one end of the logic gate control chip U5 is connected with the logic controller U1, and the other end is connected with the G pole of the PMOS tube Q4; one end of the capacitor C1 is connected with the S pole of the PMOS tube Q4 and the current-limiting protection chip U3, and the other end is connected with the grounding terminal J5; Pin 1 of the operational amplifier OP2 is connected with the G pole of the NMOS tube Q5, pin 2 is connected with pin 2 of the operational amplifier OP1, one end of the capacitor C2, one end of the resistor R1, one end of the resistor R2 and the voltage debugging terminal J6, pin 4 is connected with the current limiting protection chip U3, pin 5 is connected with the logic controller U1 and the discharge chip U7; the D pole of the NMOS tube Q5 is connected with the current limiting protection chip U3, the S pole is connected with the discharge chip U7, the other end of the capacitor C2, the other end of the resistor R1 and the power output terminal J7; the other end of the resistor R2 is connected with the ground terminal J5; pin 1 of the operational amplifier OP1 is connected with the logic controller U1; one end of the power management chip U6 is connected with the logic controller U1, and the other end is connected with the G pole of the NMOS tube Q6; the S pole of the NMOS tube Q6 is connected with the ground terminal J5, and the D pole is connected with the voltage ready terminal J4; the working mode selection terminal J2 and the chip enable terminal J3 are both connected with the logic controller U1; the reference voltage chip U8 is connected with pin 3 of the operational amplifier OP1 and pin 3 of the operational amplifier OP2.

2. The low-noise power supply chip with overvoltage current-limiting protection function according to claim 1, characterized in that: Pin 1 of the operational amplifier OP1 is an output pin, pin 2 is a negative input pin, and pin 3 is a positive input pin.

3. The low-noise power supply chip with overvoltage current-limiting protection function according to claim 1, characterized in that: Pin 1 of the operational amplifier OP2 is an output pin, pin 2 is a negative input pin, pin 3 is a positive input pin, pin 4 is a positive side power pin, and pin 5 is a negative side power pin.

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