RC-IGBT semiconductor device and layout structure thereof
By placing the diode contact area at the junction of the active and terminal regions in the RC-IGBT, combined with a grooved pad design, the problems of on-state voltage drop and breakdown curve are solved, improving the short-circuit performance and safety of the RC-IGBT.
Patent Information
- Application Number
- CN202423206389.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-25
- Publication Date
- 2025-12-05
- Estimated Expiration
- 2034-12-25
AI Technical Summary
In RC-IGBTs, the integration of diodes occupies the area of the IGBT, leading to increased on-state voltage drop, deterioration of breakdown characteristics and poor short-circuit characteristics, as well as uneven heat distribution and a reduced short-circuit safe operating area.
The first contact area of the integrated diode is set at the boundary between the active area and the terminal area of the chip to avoid occupying the active area, increase the number and perimeter of the contact area, and adopt a grooved emitter pad and isolation gate pad design to improve the uniformity of heat distribution.
It suppresses the sharp increase in conduction voltage drop, prevents breakdown curve reversal, improves short-circuit withstand capability and short-circuit time, and expands the short-circuit safe operating area.
Smart Images
Figure CN223639617U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of semiconductor technology, and in particular to an RC-IGBT semiconductor device and a layout structure thereof. BACKGROUND
[0002] The RC-IGBT (Reverse Conducting IGBT) integrates the IGBT and the diode connected in parallel with the IGBT inside the IGBT chip, greatly reduces the packaging volume, and reduces the chip cost. However, in the RC-IGBT, the performance of the diode and the performance of the IGBT often influence each other. The diode is integrated in the traditional IGBT to form the RC-IGBT. Since the diode in the ordinary RC-IGBT occupies the area of the original IGBT, the IGBT needs to increase the total area of the chip to obtain the same on-state voltage drop, thereby changing the performance parameters and increasing the cost. Moreover, the integration of the diode in the IGBT will worsen the breakdown characteristics of the device, causing the breakdown curve to appear a folding-back phenomenon. In addition, a large amount of heat generated in the FRD (Fast Recovery Diode) region during short circuit will spread to the nearby IGBT region, causing uneven heat distribution, and the short circuit characteristics of the RC-IGBT will become worse, thereby reducing the short circuit safety working area. CONTENT OF THE INVENTION
[0003] The present application aims to provide an RC-IGBT semiconductor device and a layout structure thereof, which can inhibit the sharp increase of the on-state voltage drop of the RC-IGBT, inhibit the folding-back phenomenon of the breakdown curve of the RC-IGBT, improve the short circuit resistance of the device, increase the short circuit time, and expand the short circuit safety working area.
[0004] In a first aspect, the present application provides a layout structure of an RC-IGBT semiconductor device, which comprises: a terminal region; an active region for forming an IGBT device; a first contact region of an integrated diode, which is arranged at the junction between the active region and the terminal region; an emitter pad, which is located at the top of the active region, and one side of the emitter pad is recessed; a gate pad, which is located at the top of the gate region of the IGBT device, and the gate pad is arranged in the recessed type and is isolated from the emitter pad.
[0005] In a second aspect, the present application further provides an RC-IGBT semiconductor device, which is made of the layout structure of the RC-IGBT semiconductor device according to the first aspect.
[0006] The RC-IGBT semiconductor device and the layout structure thereof provided by the application have the first contact area of the integrated diode arranged at the junction area between the chip active area and the terminal area, so that the area of the integrated diode does not occupy the area of the IGBT in the active area, thereby inhibiting the sharp increase of the on-state voltage drop of the RC-IGBT; in addition, the return phenomenon of the breakdown curve of the RC-IGBT is also inhibited; due to the increase of the number and the boundary perimeter of the first contact area of the integrated diode, the heat diffused to the IGBT area is more uniform at the time of short circuit, so that the heat distribution of the whole RC-IGBT device is uniform, thereby improving the short circuit endurance of the device, increasing the short circuit time, and expanding the short circuit safety working area. BRIEF DESCRIPTION OF DRAWINGS
[0007] In order to more clearly illustrate the technical solutions in the specific embodiments or prior art of the present application, the drawings needed to be used in the specific embodiments or prior art description will be briefly introduced as follows. Obviously, the drawings in the following description are some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without creative labor.
[0008] Figure 1 A layout structure diagram of an RC-IGBT semiconductor device in the prior art;
[0009] Figure 2 A layout of the top of an RC-IGBT semiconductor device and a perspective view from the top down and a device cross-sectional view of the semiconductor device thereof provided by an embodiment of the present application;
[0010] Figure 3 Another layout of the top of an RC-IGBT semiconductor device and a perspective view from the top down provided by an embodiment of the present application;
[0011] Figure 4 Another layout of the top of an RC-IGBT semiconductor device and a perspective view from the top down provided by an embodiment of the present application;
[0012] Figure 5 Another layout of the top of an RC-IGBT semiconductor device and a perspective view from the top down provided by an embodiment of the present application. DETAILED DESCRIPTION
[0013] The technical solutions of the present application will be described in detail below in combination with embodiments. Obviously, the described embodiments are only some of the embodiments of the present application, not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor are within the scope of protection of the present application.
[0014] Referring to the cross-sectional view of the RC-IGBT semiconductor device in the prior art and the corresponding layout structure shown in Figure 1 Figure 1 The lower part of in shows the layout at the top of the device and the perspective view from the top down, Figure 1 The upper part of in is the cross-sectional view of the device along the layout A-A'. In the RC-IGBT semiconductor device, the collector short-circuit region 12 forming the first contact region of the fast recovery diode FRD is integrated in the collector region 10 of the IGBT active region 16, and the active region 16 is flanked by the termination region 15; due to the collector short-circuit region 12 occupying the area of the original IGBT active region, the IGBT needs to increase the total area of the chip to obtain the same on-state voltage drop, thereby causing changes in performance parameters and an increase in cost; in addition, integrating the FRD in the IGBT will cause certain deterioration of the breakdown characteristics of the device, causing the breakdown curve to appear a fold-back phenomenon; at the same time, the short-circuit characteristics of the RC-IGBT will also become worse, because a large amount of heat integrated in the FRD region will spread to the nearby IGBT region during short-circuit, causing uneven heat distribution, thereby reducing the short-circuit safe operating area.
[0015] Based on this, the embodiments of the present application provide an RC-IGBT semiconductor device and a layout structure thereof, which can inhibit the sharp increase of the on-state voltage drop of the RC-IGBT, inhibit the fold-back phenomenon of the breakdown curve of the RC-IGBT, improve the short-circuit tolerance of the device, increase the short-circuit time, and expand the short-circuit safe operating area.
[0016] Figure 2 A schematic diagram of an RC-IGBT semiconductor device and the corresponding layout structure provided by the embodiments of the present application, Figure 2 The lower part of in shows the layout at the top of the device and the perspective view from the top down, Figure 2 The upper part of in is the cross-sectional view of the device along the layout A-A'. The layout shows two layers, the solid line is the top layer, and the gate pad 13 and the emitter pad 14 of the IGBT can be seen; the other layer can be seen from the top layer downward, including the collector region 10 of the device and the first contact region 12 of the integrated diode shown by the dashed circle in the layer. In an embodiment, the integrated diode has two contact regions, respectively corresponding to the anode and the cathode of the integrated diode. In an embodiment, the first contact region 12 of the integrated diode has a first conductivity type, for example, an N-type conductivity type.
[0017] Specifically, the layout structure includes a first contact region 12 of an integrated diode, a gate pad 13, an emitter pad 14, a termination region 15, and an active region 16. The active region 16 is used to form an IGBT device. The first contact region 12 of the integrated diode is arranged at an interface region 17 between the active region 16 and the termination region 15. In one embodiment, the first contact region 12 of the integrated diode is a collector short region, which is formed by implanting ions of a first conductive type (for example, N type) into a collector region 10 of a second conductive type (for example, P type) at the interface region 17. The emitter pad 14 is recessed on one side, and is located at the top of the IGBT device and at the top of the active region 16, and is in contact with the emitter metal 1 for leading out the emitter of the IGBT device. Figure 2 The gate pad 13 is also located at the top of the IGBT device and at the top of the gate region. In one embodiment, the gate pad 13 and the emitter pad 14 are at the same level. The gate pad 13 is arranged in the recessed shape and is used to lead out the gate region of the IGBT device, and the gate pad 13 is separated from the emitter pad 14.
[0018] Further, the first contact region 12 of the integrated diode extends along the edge of the emitter pad to form a first interface closed loop, and the gate pad 13 is located outside the first interface closed loop (as shown in Figure 3 ), or the first contact region 12 of the integrated diode extends along the edge of the emitter pad 14 and one side edge of the gate pad 13 to form a second interface closed loop, and the gate pad 13 is located inside the second interface closed loop (as shown in Figure 4 ). Figure 3 The arrangement of the first contact region 12 of the integrated diode at the first interface closed loop excluding the gate pad 13 as shown in
[0019] Further, the first contact region 12 of the integrated diode includes a single row or multiple rows of collector short regions of the first conductive type distributed along the interface region 17. The single row of collector short regions of the first conductive type is as shown in Figure 2 , Figure 3 and Figure 4 , and the multiple rows of collector short regions of the first conductive type are as shown in Figure 5 .
[0020] As can be seen from Figures 2-5 , the single row or multiple rows of collector short regions include multiple sub-regions of specified shapes distributed at intervals along the interface region, and the multiple sub-regions are distributed at equal intervals. Such an arrangement can increase the perimeter of the first contact region 12 of the diode. In one embodiment, the perimeter of the first contact region 12 of the diode is the sum of the perimeters of the multiple specified shapes, and the longer the perimeters of the multiple specified shapes, the better the heat dissipation of the entire device.
[0021] Further, the specified shape includes one of the following: a circle, a triangle, a rectangle, and a polygon. Figure 3 A single-row short-circuit region composed of sub-regions in a circular shape is shown, Figure 4 A single-row short-circuit region composed of sub-regions in a polygonal shape is shown, Figure 5 A double-row short-circuit region composed of sub-regions in a circular shape is shown.
[0022] Under the premise of ensuring the performance of the IGBT, the number and the sum of the perimeters of the first contact regions 12 of the diode should be as large as possible to make the heat distribution uniform and enhance the short-circuit capability. The first contact regions 12 of the diode are arranged at the junction between the terminal region and the active region, without occupying the area of the active region of the IGBT device, which can reduce the forward conduction voltage drop of the device.
[0023] Further, the first conductive type collector short-circuit region 12 includes an N-type conductive type collector short-circuit region or a P-type conductive type collector short-circuit region. In one embodiment, when the first conductive type collector short-circuit region 12 is an N-type conductive type collector short-circuit region, the first conductive type collector short-circuit region 12 corresponds to the cathode of the integrated diode in the RC-IGBT semiconductor device; when the first conductive type collector short-circuit region 12 is a P-type conductive type collector short-circuit region, the first conductive type collector short-circuit region 12 corresponds to the anode of the integrated diode in the RC-IGBT semiconductor device.
[0024] In the layout structure of the RC-IGBT semiconductor device provided by the embodiments of the present application, the first contact region of the integrated diode is arranged at the junction between the active region and the terminal region of the chip, so that the region of the integrated diode does not occupy the region of the IGBT in the active region, thereby suppressing the sharp increase of the conduction voltage drop of the RC-IGBT. In addition, arranging the first conductive type collector short-circuit region at the junction between the active region and the terminal region of the chip also suppresses the folding phenomenon of the breakdown curve of the RC-IGBT, because: when breakdown occurs, the IGBT region away from the diode region is first subjected to impurity injection of the second conductive type, so that the IGBT region collides and ionizes, and then a leakage current is generated. At this time, the temperature rises, and since the BV breakdown voltage is a positive temperature coefficient, the temperature rises, and the BV at this place also rises. The breakdown point gradually shifts to the region with a lower BV, and finally reaches the diode region. Since the diode region does not have a parasitic transistor, it will not cause the folding phenomenon of the breakdown curve. In addition, due to the increase in the number and the boundary perimeter of the FRD region, the heat diffused to the IGBT region is more uniform when short-circuiting, so that the heat distribution of the entire RC-IGBT device is uniform, thereby improving the short-circuit resistance of the device, increasing the short-circuit time, and expanding the short-circuit safety working area.
[0025] Based on the above embodiment of the layout structure, the embodiment of the present application further provides an RC-IGBT semiconductor device made of the layout structure of the RC-IGBT semiconductor device as described in the first aspect. For example, the RC-IGBT semiconductor device is made of the layout structure as shown in the upper half of FIG. 1. Figure 2 The layout structure shown in the lower half is cut along the dotted line, and the cross-sectional view of the device obtained is as shown in the upper half of FIG. 2. Figure 2 As shown in the upper half, 1 is an emitter metal; 2 is an interlayer dielectric layer; 3 is an N-type emitter region; 4-1, 4-2, and 4-3 are P-type emitter regions; 5 is a P-type body region; 6 is an N-type carrier storage layer; 7 is a gate trench; 8 is an N-type lightly doped drift region; 9 is an N-type field stop layer; 10 is a P-type collector region; 11 is a collector metal; and 12 is an N-type collector short-circuit region.
[0026] It should be noted that in other embodiments, the N and P conductivity types in the above embodiments of the semiconductor device can be interchanged.
[0027] The semiconductor device provided by the embodiment of the present application has the same implementation principle and technical effects as the above layout structure embodiment, and for brevity of description, the parts not mentioned in the embodiment of the semiconductor device can be referred to the corresponding content in the above layout structure embodiment.
[0028] In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the present application. In addition, the terms "first", "second", "third" are only for the purpose of description, and cannot be understood as indicating or implying relative importance.
[0029] Finally, it should be noted that: the above-described embodiments are merely specific embodiments of the present application, used to illustrate the technical solutions of the present application, and not to limit them, the protection scope of the present application is not limited thereto, although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that any person skilled in the art within the technical range disclosed by the present application can modify or easily think of changes to the technical solutions recorded in the foregoing embodiments, or make equivalent replacements to some of the technical features; and these modifications, changes or replacements do not make the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application, and all should be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.
Claims
1. A layout structure of an RC-IGBT semiconductor device, characterized by, The layout structure comprises: a terminal region; an active region for forming an IGBT device; a first contact region of an integrated diode disposed at an interface between the active region and the terminal region; an emitter pad located on top of the active region, one side of the emitter pad being recessed; a gate pad located on top of a gate region of the IGBT device, the gate pad being disposed in the recess and isolated from the emitter pad.
2. The layout structure of claim 1, wherein, The first contact region of the integrated diode comprises: a single row or multiple rows of collector short-circuit regions distributed along the interface, the collector short-circuit regions having a first conductivity type.
3. The layout structure of claim 2, wherein, The single row or multiple rows of collector short-circuit regions comprise: a plurality of sub-regions of a specified shape distributed at intervals along the interface.
4. The layout structure of claim 3, wherein, The plurality of sub-regions are distributed at equal intervals.
5. The layout structure of claim 3, wherein, The specified shape comprises one of: a circle, a triangle, a rectangle, a polygon.
6. The layout structure of claim 2, wherein, The first conductivity type comprises: an N-type conductivity type, or a P-type conductivity type.
7. The layout structure of claim 2, wherein, The collector short-circuit regions of the first conductivity type comprise a cathode of an integrated diode in an RC-IGBT semiconductor device.
8. The layout structure of claim 1, wherein, The first contact region of the integrated diode extends along an edge of the emitter pad to form a first interface closed loop, the gate pad being located outside the first interface closed loop.
9. The layout structure of claim 1, wherein, The first contact region of the integrated diode extends along an edge of the emitter pad and one side edge of the gate pad to form a second interface closed loop, the gate pad being located inside the second interface closed loop.
10. An RC-IGBT semiconductor device, characterized by, The semiconductor device is made of the layout structure of the RC-IGBT semiconductor device according to any one of claims 1-9.