Driver circuit controlled by cross-coupling dead time

Abstract

The utility model discloses a driver circuit controlled by cross coupling dead time. The driver circuit comprises a signal input end VIN, an upper arm driving unit, a lower arm driving unit, a first dead time controller, a second dead time controller and a signal output end VOUT, the signal input end VIN is connected with the upper arm driving unit and the lower arm driving unit, the upper arm driving unit and the lower arm driving unit are connected with the signal output end VOUT, the first dead time controller is connected with the upper arm driving unit and the lower arm driving unit, and the second dead time controller is connected with the upper arm driving unit and the lower arm driving unit; each of the upper arm driving unit and the lower arm driving unit comprises a logic module for sequential control; a control signal of the upper arm driving unit controls the conduction or cut-off of the lower arm driving unit through cross coupling of a first dead zone time controller, and meanwhile, a control signal after the conduction or cut-off of the lower arm driving unit controls the conduction or cut-off of the upper arm driving unit through cross coupling; the first dead time controller and the second dead time controller control the dead time by controlling the conduction time difference between the upper arm driving unit and the lower arm driving unit.

Description

Technical Field

[0001] This application belongs to the field of driver technology, specifically referring to a driver circuit for cross-coupled dead time control. Background Technology

[0002] Dead time refers to the time difference between the turn-off states of two transistors during switching in a switching power supply. Its purpose is to prevent short circuits caused by simultaneous conduction of the upper and lower transistors, thus preventing power components from burning out. In high-voltage gate drivers, dead time control between the upper and lower drive units is crucial. If the dead time is too short, conduction will occur between the upper and lower drive units, resulting in simultaneous high current and high voltage on the power devices, leading to a sharp increase in power consumption and damage. If the dead time is too long, the upper and lower drive units will be off for an extended period, making them more susceptible to external signal interference, which may also increase power consumption and, in severe cases, cause malfunctions and irreversible damage to the entire system. Therefore, dead time control in high-voltage gate drivers is extremely important.

[0003] Current dead-time control technologies typically employ resistor-capacitor delays. This involves turning off one power device with a short delay and turning on another with a long delay, using the time difference between the two delays to control the dead time. The drawback of this approach is that during semiconductor device manufacturing, the actual values ​​of resistors and capacitors can deviate significantly from their design values. This can lead to the long and short delays deviating from the design values, resulting in a shorter dead time. This can cause crosstalk between the upper and lower arm drive units, resulting in high current and high voltage on the power devices simultaneously, a sharp increase in power consumption, and potential damage to the devices and the system. In short, the resistor-capacitor delay scheme used in current technologies has relatively poor stability and is prone to significant errors. Utility Model Content

[0004] To overcome the shortcomings of the prior art, this application provides a driver circuit for cross-coupled dead time control, which adopts logic timing control and performs cross-coupling control according to the conduction relationship between the upper arm drive unit and the lower arm drive unit, thereby realizing dead time control.

[0005] This invention provides a driver circuit for cross-coupled dead-time control. The driver circuit includes: a signal input terminal VIN, an upper arm driving unit, a lower arm driving unit, a first dead-time controller, a second dead-time controller, and a signal output terminal VOUT. The signal input terminal VIN is connected to the upper arm driving unit and the lower arm driving unit, and the upper arm driving unit and the lower arm driving unit are connected to the signal output terminal VOUT. The first dead-time controller is connected to the upper arm driving unit and the lower arm driving unit, and the second dead-time controller is connected to the upper arm driving unit and the lower arm driving unit. Both the upper arm driving unit and the lower arm driving unit include logic modules for timing control. The upper arm driving unit includes a first logic circuit module that inverts the level signal at the input terminal. The lower arm driving unit includes a second logic circuit module that inverts the level signal at the input terminal.

[0006] The control signal of the upper arm drive unit controls the conduction or cutoff of the lower arm drive unit through cross-coupling of the first dead time controller. At the same time, the control signal after the lower arm drive unit is turned on or off is cross-coupled to control the conduction or cutoff of the upper arm drive unit. The first dead time controller and the second dead time controller control the dead time by controlling the conduction time difference between the upper arm drive unit and the lower arm drive unit.

[0007] According to the cross-coupled dead-time control driver circuit provided in this application, the upper arm driving unit further includes a first level shifter and a first transistor; the control input terminal of the first level shifter is connected to the signal input terminal VIN, the control output terminal of the first level shifter is connected to the first input terminal of the first logic circuit module, the output terminal of the first logic circuit module is connected to the control input terminal of the first dead-time controller and the gate of the first transistor; the source of the first transistor is connected to the level input terminal of the upper arm driving unit, and the drain of the first transistor is connected to the signal output terminal VOUT;

[0008] The first transistor is a PMOS transistor.

[0009] According to the cross-coupled dead-time control driver circuit provided in this application, the lower arm driving unit further includes a second level shifter and a second transistor; the control input terminal of the second level shifter is connected to the signal input terminal VIN, the control output terminal of the second level shifter is connected to the first input terminal of the second logic circuit module, the output terminal of the second logic circuit module is connected to the control input terminal of the second dead-time controller and the gate of the second transistor; the source of the second transistor is connected to the ground terminal of the lower arm driving unit, and the drain of the second transistor is connected to the signal output terminal VOUT;

[0010] The second transistor is an NMOS transistor.

[0011] According to the cross-coupled dead-time control driver circuit provided in this application, the upper arm driving unit is a high-voltage domain driving unit, and the lower arm driving unit is a low-voltage domain driving unit.

[0012] The first level shifter converts the input power supply voltage VDD and ground GND of the driver circuit into a high-voltage power supply VDD_HIGH and a high-voltage ground GND_HIGH, and the control output terminal of the first level shifter outputs the high-voltage output signal VIN_HIGH.

[0013] The second level shifter converts the input power supply voltage VDD and ground GND of the driver circuit into a low-voltage power supply VDD_LOW and a low-voltage ground GND. The control output terminal of the second level shifter outputs the low-voltage output signal VIN_LOW.

[0014] According to the cross-coupled dead-time control driver circuit provided in this application, the output signal VIN_HIGH of the high-voltage domain and the output signal VIN_LOW of the low-voltage domain have the same phase.

[0015] According to the cross-coupled dead-time control driver circuit provided in this application, the first logic circuit module includes a NAND gate, a first inverter, a second inverter, a third inverter, and a fourth inverter. The first input terminal of the NAND gate is connected to the output signal VIN_HIGH of the high-voltage domain, the second input terminal of the NAND gate is connected to the control output terminal of the second dead-time controller, and the output terminal of the NAND gate is connected to the input terminal of the first inverter. The first inverter, the second inverter, the third inverter, and the fourth inverter are connected in series, and the output terminal of the fourth inverter is connected to the gate of the first transistor. The NAND gate, the first inverter, the second inverter, the third inverter, and the fourth inverter are all connected to the voltage power supply VDD_HIGH of the high-voltage domain and the ground GND_HIGH of the high-voltage domain.

[0016] According to the cross-coupled dead-time control driver circuit provided in this application, the second logic circuit module includes a NOR gate, a fifth inverter, a sixth inverter, a seventh inverter, and an eighth inverter. The first input terminal of the NOR gate is connected to the output signal VIN_LOW of the low-voltage domain, the second input terminal of the NOR gate is connected to the control output terminal of the first dead-time controller, and the output terminal of the NOR gate is connected to the input terminal of the fifth inverter. The fifth inverter, the sixth inverter, the seventh inverter, and the eighth inverter are connected in series, and the output terminal of the eighth inverter is connected to the gate of the second transistor. The NOR gate, the fifth inverter, the sixth inverter, the seventh inverter, and the eighth inverter are all connected to the voltage power supply VDD_LOW of the low-voltage domain and the ground GND of the low-voltage domain.

[0017] According to the driver circuit for cross-coupled dead time control provided in this application, the first dead time controller is a third level shifter, and the second dead time controller is a fourth level shifter;

[0018] The control input terminal of the third level shifter is connected to the output terminal of the third inverter, and the control output terminal of the third level shifter is connected to the second input terminal of the NOR gate. The third level shifter converts the voltage power supply VDD_HIGH of the high voltage domain and the ground GND_HIGH of the high voltage domain into the voltage power supply VDD_LOW of the low voltage domain and the ground GND of the low voltage domain.

[0019] The control input terminal of the fourth level shifter is connected to the output terminal of the seventh inverter, and the control output terminal of the fourth level shifter is connected to the second input terminal of the NAND gate. The fourth level shifter converts the voltage power supply VDD_LOW of the low voltage domain and the ground GND of the low voltage domain into the voltage power supply VDD_HIGH of the high voltage domain and the ground GND_HIGH of the high voltage domain.

[0020] According to the cross-coupled dead-time control driver circuit provided in this application, when the signal input terminal VIN changes from low level to high level, the output signal VIN_LOW of the low-voltage domain makes the same transition, the second transistor is turned off, the fourth level shifter converts the high level of the low-voltage domain input to the control input terminal into the high level of the high-voltage domain and outputs it to the NAND gate, the first transistor is turned on, and the signal output terminal VOUT outputs a high level.

[0021] According to the cross-coupled dead-time control driver circuit provided in this application, when the signal input terminal VIN changes from high level to low level, the output signal VIN_LOW of the low-voltage domain and the output signal VIN_HIGH of the high-voltage domain undergo the same transition. The first transistor is turned off, the third level shifter converts the low level of the high-voltage domain input to the control input terminal to the low level of the low-voltage domain and outputs it to the NOR gate. The second transistor is turned on, and the signal output terminal VOUT outputs a low level.

[0022] The beneficial effects of this utility model are as follows: This application provides a driver circuit with cross-coupling dead-time control. Both the upper arm drive unit and the lower arm drive unit include logic modules for timing control. Cross-coupling control is performed based on the conduction relationship between the upper and lower arm drive units. The upper arm drive unit will only conduct after the lower arm drive unit is turned off, following the switching of the second dead-time controller; or the lower arm drive unit will only conduct after the upper arm drive unit is turned off, following the switching of the first dead-time controller. Therefore, it can effectively ensure that the upper and lower arm drive units will not conduct simultaneously, avoiding the occurrence of crossover between the upper and lower arm drive units, and realizing dead-time control of the driver. Attached Figure Description

[0023] The technical solution and other beneficial effects of this application will become apparent from the following detailed description of specific embodiments in conjunction with the accompanying drawings.

[0024] Figure 1 This is a schematic diagram of the driver circuit for cross-coupled dead time control provided in this embodiment. Detailed Implementation

[0025] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0026] In the description of this application, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," and "counterclockwise," etc., indicating orientation or positional relationships based on the orientation or positional relationships shown in the accompanying drawings, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of the stated features. In the description of this application, "a plurality of" means two or more, unless otherwise explicitly specified.

[0027] The following disclosure provides many different embodiments or examples for implementing different structures of this application. To simplify the disclosure, specific examples of components and arrangements are described below. Of course, these are merely examples and are not intended to limit the scope of this application. Furthermore, reference numerals and / or letters may be repeated in different examples; such repetition is for simplification and clarity and does not in itself indicate a relationship between the various embodiments and / or arrangements discussed. In addition, various specific examples of processes and materials are provided in this application, but those skilled in the art will recognize the application of other processes and / or the use of other materials.

[0028] The embodiments of this application will now be further described in conjunction with the accompanying drawings and specific implementation details.

[0029] Figure 1 This is a schematic diagram of the driver circuit for cross-coupled dead time control provided in an embodiment of this application.

[0030] like Figure 1As shown, the driver circuit provided in this embodiment mainly includes: a signal input terminal VIN, an upper arm driving unit, a lower arm driving unit, a first dead-time controller, a second dead-time controller, and a signal output terminal VOUT; the signal input terminal VIN is connected to the upper arm driving unit and the lower arm driving unit, the upper arm driving unit and the lower arm driving unit are connected to the signal output terminal VOUT, the first dead-time controller is connected to the upper arm driving unit and the lower arm driving unit, and the second dead-time controller is connected to the upper arm driving unit and the lower arm driving unit; both the upper arm driving unit and the lower arm driving unit include logic modules for timing control; only one of the upper arm driving unit and the lower arm driving unit is turned on and outputs a signal from the signal output terminal VOUT.

[0031] The control signal of the upper arm drive unit controls the conduction or cutoff of the lower arm drive unit through cross-coupling of the first dead-time controller. Simultaneously, the control signal after the lower arm drive unit is turned on or off is also cross-coupled to control the conduction or cutoff of the upper arm drive unit. The lower arm drive unit can only be turned on when it is turned off and a corresponding control signal is issued, transmitted to the lower arm drive unit through the first dead-time controller; or, the upper arm drive unit can only be turned on when it is turned off and a corresponding control signal is issued, transmitted to the upper arm drive unit through the second dead-time controller. The first and second dead-time controllers control the dead time by controlling the conduction time difference between the upper arm drive unit and the lower arm drive unit.

[0032] like Figure 1 As shown, the upper arm driving unit includes a first level shifter, a first logic circuit module, and a first transistor PM1. The control input terminal of the first level shifter is connected to the signal input terminal VIN, the control output terminal of the first level shifter is connected to the first input terminal of the first logic circuit module, and the output terminal of the first logic circuit module is connected to the control input terminal of the first dead-time controller and the gate of the first transistor PM1. The source of the first transistor PM1 is connected to the level input terminal of the upper arm driving unit, and the drain of the first transistor PM1 is connected to the signal output terminal VOUT. The first transistor PM1 is a PMOS transistor. When the first transistor PM1 is turned on, the signal output terminal VOUT outputs a high level. The upper arm driving unit includes a first logic circuit module that inverts the level signal at the input terminal.

[0033] The lower arm driving unit includes a second level shifter, a second logic circuit module, and a second transistor NM1. The control input of the second level shifter is connected to the signal input VIN, and the control output of the second level shifter is connected to the first input of the second logic circuit module. The output of the second logic circuit module is connected to the control input of the second dead-time controller and the gate of the second transistor NM1. The source of the second transistor NM1 is connected to the ground of the lower arm driving unit, and the drain of the second transistor NM1 is connected to the signal output VOUT. The second transistor NM1 is an NMOS transistor. When the second transistor NM1 is turned on, the signal output VOUT outputs a low level. The lower arm driving unit includes a second logic circuit module that inverts the level signal at the input terminal.

[0034] Specifically, in this embodiment, the upper arm drive unit is a high-voltage domain drive unit, and the lower arm drive unit is a low-voltage domain drive unit.

[0035] The first level shifter converts the input power supply voltage VDD and ground GND of the driver circuit into a high-voltage power supply VDD_HIGH and a high-voltage ground GND_HIGH, and the control output terminal of the first level shifter outputs the high-voltage output signal VIN_HIGH.

[0036] The second level shifter converts the input power supply voltage VDD and ground GND of the driver circuit into a low-voltage power supply VDD_LOW and a low-voltage ground GND. The control output terminal of the second level shifter outputs the low-voltage output signal VIN_LOW.

[0037] The output signal VIN_HIGH of the high-voltage domain and the output signal VIN_LOW of the low-voltage domain have the same phase.

[0038] The first level shifter converts the input signal VIN at the signal input terminal VIN into a high-voltage domain output signal VIN_HIGH, which is located between the high-voltage power supply VDD_HIGH and the high-voltage ground GND_HIGH. Simultaneously, the second level shifter converts the input signal VIN at the signal input terminal VIN into a low-voltage domain output signal VIN_LOW, which is located between the low-voltage power supply VDD_LOW and the low-voltage ground GND.

[0039] In another embodiment, the upper arm drive unit can be a low-voltage domain drive unit, and the lower arm drive unit can be a high-voltage domain drive unit, which will not be described in detail here.

[0040] like Figure 1As shown, in the first logic circuit module, the first logic circuit module includes a NAND gate NAND1, a first inverter INV1, a second inverter INV2, a third inverter INV3, and a fourth inverter INV4. The first input terminal of the NAND gate NAND1 is connected to the output signal VIN_HIGH of the high-voltage domain, the second input terminal of the NAND gate NAND1 is connected to the control output terminal of the second dead-time controller, and the output terminal of the NAND gate NAND1 is connected to the input terminal of the first inverter INV1. The first inverter INV1, the second inverter INV2, the third inverter INV3, and the fourth inverter INV4 are connected in series. The output terminal of the fourth inverter INV4 is connected to the gate of the first transistor PM1. The NAND gate NAND1, the first inverter INV1, the second inverter INV2, the third inverter INV3, and the fourth inverter INV4 are all connected to the voltage power supply VDD_HIGH of the high-voltage domain and the ground GND_HIGH of the high-voltage domain. The first inverter INV1, the second inverter INV2, the third inverter INV3, and the fourth inverter INV4 sequentially invert the input level signal, converting a high level to a low level or vice versa. When the gate of the first transistor PM1 is high, the first transistor PM1 is turned off.

[0041] In the second logic circuit module, the second logic circuit module includes a NOR gate NOR1, a fifth inverter INV5, a sixth inverter INV6, a seventh inverter INV7, and an eighth inverter INV8. The first input terminal of the NOR gate NOR1 is connected to the output signal VIN_LOW of the low-voltage domain, the second input terminal of the NOR gate NOR1 is connected to the control output terminal of the first dead-time controller, and the output terminal of the NOR gate NOR1 is connected to the input terminal of the fifth inverter INV5. The fifth inverter INV5, the sixth inverter INV6, the seventh inverter INV7, and the eighth inverter INV8 are connected in series. The output terminal of the eighth inverter INV8 is connected to the gate of the second transistor NM1. The NOR gate NOR1, the fifth inverter INV5, the sixth inverter INV6, the seventh inverter INV7, and the eighth inverter INV8 are all connected to the voltage power supply VDD_LOW of the low-voltage domain and the ground GND of the low-voltage domain. The fifth inverter INV5, the sixth inverter INV6, the seventh inverter INV7, and the eighth inverter INV8 sequentially invert the input level signal, converting a high level to a low level or vice versa. When the gate of the second transistor NM1 is low, the second transistor NM1 is turned off.

[0042] like Figure 1 As shown, in this embodiment, the first dead-time controller is a third level shifter, and the second dead-time controller is a fourth level shifter.

[0043] The control input terminal of the third level shifter is connected to the output terminal of the third inverter INV3, and the control output terminal of the third level shifter is connected to the second input terminal of the NOR gate NOR1. The third level shifter converts the voltage power supply VDD_HIGH of the high voltage domain and the ground GND_HIGH of the high voltage domain into the voltage power supply VDD_LOW of the low voltage domain and the ground GND of the low voltage domain.

[0044] The control input terminal of the fourth level shifter is connected to the output terminal of the seventh inverter INV7, and the control output terminal of the fourth level shifter is connected to the second input terminal of the NAND gate NAND1. The fourth level shifter converts the voltage power supply VDD_LOW of the low voltage domain and the ground GND of the low voltage domain into the voltage power supply VDD_HIGH of the high voltage domain and the ground GND_HIGH of the high voltage domain.

[0045] In this embodiment, when the signal input terminal VIN changes from low level to high level, the output signal VIN_LOW of the low-voltage domain undergoes the same transition, the second transistor NM1 is turned off, the fourth level shifter converts the high level of the low-voltage domain input to the control input terminal into the high level of the high-voltage domain and outputs it to the NAND gate NAND1, the first transistor PM1 is turned on, and the signal output terminal VOUT outputs a high level.

[0046] When the signal input terminal VIN changes from high level to low level, the output signal VIN_LOW of the low voltage domain and the output signal VIN_HIGH of the high voltage domain undergo the same transition. The first transistor NM1 is turned off. The third level shifter converts the low level of the high voltage domain input to the control input terminal into the low level of the low voltage domain and outputs it to the NOR gate NOR1. The second transistor NM1 is turned on, and the signal output terminal VOUT outputs a low level.

[0047] The working principle of the cross-coupled dead-time control driver circuit provided in this embodiment is as follows:

[0048] When the input signal VIN at the signal input terminal VIN changes from low to high, the output signal VIN_LOW of the low-voltage domain output by the control output terminal of the second level shifter also undergoes the same transition, that is, the output signal VIN_LOW of the low-voltage domain becomes high. The high-level output signal VIN_LOW of the low-voltage domain passes sequentially through the NOR gate NOR1, the fifth inverter INV5, the sixth inverter INV6, the seventh inverter INV7, and the eighth inverter INV8 in the second logic circuit module, causing the output terminal of the eighth inverter INV8 to output a low level, that is, the gate input of the second transistor NM1 is low, and the second transistor NM1 becomes cut off. Simultaneously, the output of the seventh inverter INV7 becomes a high-level signal. This high-level signal is input to the fourth level shifter, which converts the low-voltage domain high-level signal input to the control input into a high-voltage domain high-level signal and outputs it to the NAND gate NAND1. At this point, both inputs of the NAND gate NAND1 are high-level signals, and its output is low-level. The low-level signal output by the NAND gate NAND1 passes sequentially through the first inverter INV1, the second inverter INV2, the third inverter INV3, and the fourth inverter INV4, causing the output of the fourth inverter INV4 to output a low-level signal. This means the gate input of the first transistor PM1 is low, and the first transistor PM1 becomes conductive. Simultaneously, the signal output VOUT outputs a high-level signal.

[0049] When the input signal VIN at the signal input terminal VIN changes from high to low, the output signal VIN_HIGH of the high-voltage domain output from the control output terminal of the first level shifter and the output signal VIN_LOW of the low-voltage domain output from the control output terminal of the second level shifter also undergo the same transition, except that the voltage domains of their output signals are different, i.e., the output signal VIN_HIGH of the high-voltage domain becomes low. The low-level output signal VIN_HIGH of the high-voltage domain passes sequentially through the NAND gate NAND1, the first inverter INV1, the second inverter INV2, the third inverter INV3, and the fourth inverter INV4 in the first logic circuit module, causing the output terminal of the fourth inverter INV4 to output a high level, i.e., the gate input of the first transistor PM1 is high, and the first transistor PM1 becomes cut off. Simultaneously, the output of the third inverter INV3 becomes a low-level signal. This low-level signal is input to the third level shifter, which converts the low-level signal from the high-voltage domain into a low-level signal from the control input and outputs it to the NOR gate NOR1. At this point, both inputs of the NOR gate NOR1 are low-level signals, and its output is a high-level signal. The high-level signal output by the NOR gate NOR1 passes sequentially through the fifth inverter INV5, the sixth inverter INV6, the seventh inverter INV7, and the eighth inverter INV8, causing the output of the eighth inverter INV8 to be high. This means the gate input of the second transistor NM1 is high, and the second transistor is turned on. Simultaneously, the signal output VOUT outputs a low-level signal.

[0050] In this embodiment, when the input signal VIN at the signal input terminal VIN changes from low level to high level, the second transistor NM1 is first turned off by the second logic circuit module, and then the high-level signal output by the seventh inverter INV7 is used to turn on the first transistor PM1 through the second dead time controller and the first logic circuit module. Thus, a dead time can be formed when the input signal VIN changes from low level to high level, avoiding the simultaneous conduction of the first transistor PM1 and the second transistor NM1.

[0051] Similarly, when the input signal VIN at the signal input terminal VIN changes from high level to low level, the first transistor PM1 is first turned off by the first logic circuit module, and then the low-level signal output by the third inverter INV3 is used to turn on the second transistor NM1 by the first dead time controller and the second logic circuit module. Thus, a dead time can be formed when the input signal VIN changes from high level to low level, avoiding the simultaneous conduction of the first transistor PM1 and the second transistor NM1.

[0052] This application provides a driver circuit with cross-coupled dead-time control. Both the upper arm drive unit and the lower arm drive unit include logic modules for timing control. Cross-coupling control is performed based on the conduction relationship between the upper and lower arm drive units. The upper arm drive unit will only conduct after the lower arm drive unit is turned off, following a transition by the second dead-time controller; or, conversely, the lower arm drive unit will only conduct after the upper arm drive unit is turned off, following a transition by the first dead-time controller. Therefore, it effectively ensures that the upper and lower arm drive units will not conduct simultaneously, avoiding crossover between them and achieving dead-time control of the driver.

[0053] Although preferred embodiments of the present invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including both the preferred embodiments and all changes and modifications falling within the scope of the present invention. Finally, it should be noted that in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or terminal device that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or terminal device. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or terminal device that includes said element.

[0054] The foregoing has provided a detailed description of a cross-coupled dead-time control driver circuit provided in the embodiments of this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only for the purpose of helping to understand the technical solutions and core ideas of this application. Those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. These modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A driver circuit for cross-coupled dead-time control, characterized in that, The driver circuit includes: a signal input terminal VIN, an upper arm driving unit, a lower arm driving unit, a first dead-time controller, a second dead-time controller, and a signal output terminal VOUT. The signal input terminal VIN is connected to the upper arm driving unit and the lower arm driving unit; the upper arm driving unit and the lower arm driving unit are connected to the signal output terminal VOUT; the first dead-time controller is connected to the upper arm driving unit and the lower arm driving unit; the second dead-time controller is connected to the upper arm driving unit and the lower arm driving unit. Both the upper arm driving unit and the lower arm driving unit include logic modules for timing control. The upper arm driving unit includes a first logic circuit module that inverts the input level signal. The lower arm driving unit includes a second logic circuit module that inverts the input level signal. The control signal of the upper arm drive unit controls the conduction or cutoff of the lower arm drive unit through cross-coupling of the first dead time controller. At the same time, the control signal after the lower arm drive unit is turned on or off is cross-coupled to control the conduction or cutoff of the upper arm drive unit. The first dead time controller and the second dead time controller control the dead time by controlling the conduction time difference between the upper arm drive unit and the lower arm drive unit.

2. The driver circuit for cross-coupled dead-time control according to claim 1, characterized in that, The upper arm driving unit further includes a first level shifter and a first transistor; the control input terminal of the first level shifter is connected to the signal input terminal VIN, the control output terminal of the first level shifter is connected to the first input terminal of the first logic circuit module, the output terminal of the first logic circuit module is connected to the control input terminal of the first dead time controller and the gate of the first transistor; the source of the first transistor is connected to the level input terminal of the upper arm driving unit, and the drain of the first transistor is connected to the signal output terminal VOUT. The first transistor is a PMOS transistor.

3. The driver circuit for cross-coupled dead-time control according to claim 2, characterized in that, The lower arm drive unit further includes a second level shifter and a second transistor; the control input terminal of the second level shifter is connected to the signal input terminal VIN, the control output terminal of the second level shifter is connected to the first input terminal of the second logic circuit module, the output terminal of the second logic circuit module is connected to the control input terminal of the second dead time controller and the gate of the second transistor; the source of the second transistor is connected to the ground terminal of the lower arm drive unit, and the drain of the second transistor is connected to the signal output terminal VOUT; The second transistor is an NMOS transistor.

4. The driver circuit for cross-coupled dead-time control according to claim 3, characterized in that, The upper arm drive unit is a high-voltage domain drive unit, and the lower arm drive unit is a low-voltage domain drive unit. The first level shifter converts the input power supply voltage VDD and ground GND of the driver circuit into a high-voltage power supply VDD_HIGH and a high-voltage ground GND_HIGH, and the control output terminal of the first level shifter outputs the high-voltage output signal VIN_HIGH. The second level shifter converts the input power supply voltage VDD and ground GND of the driver circuit into a low-voltage power supply VDD_LOW and a low-voltage ground GND. The control output terminal of the second level shifter outputs the low-voltage output signal VIN_LOW.

5. The driver circuit for cross-coupled dead-time control according to claim 4, characterized in that, The output signal VIN_HIGH of the high-voltage domain and the output signal VIN_LOW of the low-voltage domain have the same phase.

6. The driver circuit for cross-coupled dead-time control according to claim 4, characterized in that, The first logic circuit module includes a NAND gate, a first inverter, a second inverter, a third inverter, and a fourth inverter. The first input of the NAND gate is connected to the output signal VIN_HIGH of the high-voltage domain, the second input of the NAND gate is connected to the control output of the second dead-time controller, and the output of the NAND gate is connected to the input of the first inverter. The first inverter, the second inverter, the third inverter, and the fourth inverter are connected in series, and the output of the fourth inverter is connected to the gate of the first transistor. The NAND gate, the first inverter, the second inverter, the third inverter, and the fourth inverter are all connected to the voltage power supply VDD_HIGH of the high-voltage domain and the ground GND_HIGH of the high-voltage domain.

7. The driver circuit for cross-coupled dead-time control according to claim 6, characterized in that, The second logic circuit module includes a NOR gate, a fifth inverter, a sixth inverter, a seventh inverter, and an eighth inverter. The first input of the NOR gate is connected to the output signal VIN_LOW of the low-voltage domain, the second input of the NOR gate is connected to the control output of the first dead-time controller, and the output of the NOR gate is connected to the input of the fifth inverter. The fifth inverter, the sixth inverter, the seventh inverter, and the eighth inverter are connected in series, and the output of the eighth inverter is connected to the gate of the second transistor. The NOR gate, the fifth inverter, the sixth inverter, the seventh inverter, and the eighth inverter are all connected to the voltage power supply VDD_LOW of the low-voltage domain and the ground GND of the low-voltage domain.

8. The driver circuit for cross-coupled dead-time control according to claim 7, characterized in that, The first dead-time controller is a third level shifter, and the second dead-time controller is a fourth level shifter; The control input terminal of the third level shifter is connected to the output terminal of the third inverter, and the control output terminal of the third level shifter is connected to the second input terminal of the NOR gate. The third level shifter converts the voltage power supply VDD_HIGH of the high voltage domain and the ground GND_HIGH of the high voltage domain into the voltage power supply VDD_LOW of the low voltage domain and the ground GND of the low voltage domain. The control input terminal of the fourth level shifter is connected to the output terminal of the seventh inverter, and the control output terminal of the fourth level shifter is connected to the second input terminal of the NAND gate. The fourth level shifter converts the voltage power supply VDD_LOW of the low voltage domain and the ground GND of the low voltage domain into the voltage power supply VDD_HIGH of the high voltage domain and the ground GND_HIGH of the high voltage domain.

9. The driver circuit for cross-coupled dead-time control according to claim 8, characterized in that, When the signal input terminal VIN changes from low level to high level, the output signal VIN_LOW of the low-voltage domain undergoes the same transition. The second transistor is turned off. The fourth level shifter converts the high level of the low-voltage domain input to the control input terminal into the high level of the high-voltage domain and outputs it to the NAND gate. The first transistor is turned on, and the signal output terminal VOUT outputs a high level.

10. The driver circuit for cross-coupled dead-time control according to claim 8, characterized in that, When the signal input terminal VIN changes from high level to low level, the output signal VIN_LOW of the low voltage domain and the output signal VIN_HIGH of the high voltage domain undergo the same transition. The first transistor is turned off, the third level shifter converts the low level of the high voltage domain input to the control input terminal to the low level of the low voltage domain and outputs it to the NOR gate. The second transistor is turned on, and the signal output terminal VOUT outputs a low level.

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