Back contact heterojunction solar cell

Abstract

The utility model discloses a back contact heterojunction solar cell. The back contact heterojunction solar cell comprises a silicon substrate, and a first main surface of the silicon substrate is provided with a first functional area, an isolation area and a second functional area; the first carrier collection layer is arranged on the first functional region and extends to the isolation region; a first conductive layer disposed on the first carrier collection layer; the second carrier collection layer is arranged on the second functional region and extends to the isolation region, and the second carrier collection layer and the part, extending to the isolation region, of the first carrier collection layer form a stacked structure; a second conductive layer disposed on the second carrier collection layer; the first insulating layer is arranged in the isolation region and is connected with the first carrier collection layer and the second carrier collection layer; the second insulating layer is embedded in the laminated structure and is positioned between the main surface of the first part and the main surface of the second part; the isolation groove at least blocks the electric connection between the first conductive layer and the second conductive layer. According to the structure, the conversion efficiency is effectively improved.

Description

TECHNICAL FIELD

[0001] The utility model relates to a kind of back contact heterojunction solar cells. BACKGROUND

[0002] For back contact heterojunction solar cell, its heterojunction structure and grid line are arranged on the back of solar cell, remove the grid line from the solar light of back contact heterojunction solar cell front surface, increase the absorption efficiency of incident light.

[0003] The existing back contact heterojunction solar cell inevitably needs to set isolation area for n-type functional area and p-type functional area, if the isolation area is not effectively isolated, it will cause the back contact heterojunction solar cell to appear the problem of electric leakage, reduce the conversion efficiency of back contact heterojunction solar cell. UTILITY MODEL CONTENT

[0004] Therefore, the utility model provides a kind of back contact heterojunction solar cell, can effectively guarantee the electric insulation of isolation area, effectively improve the conversion efficiency of back contact heterojunction solar cell.

[0005] In order to solve the above technical problems, the utility model provides the following technical scheme:

[0006] The utility model provides a kind of back contact heterojunction solar cell, comprising:

[0007] Silicon base, wherein the first main surface of the silicon base is arranged with first functional area, isolation area and second functional area;

[0008] First carrier collection layer, set on the first functional area and extend to the isolation area;

[0009] First conductive layer, set on the first carrier collection layer;

[0010] Second carrier collection layer, set on the second functional area and extend to the isolation area, wherein the conductive type of the first carrier collection layer and the second carrier collection layer is opposite, and the first part of the second carrier collection layer extending to the isolation area and the second part of the first carrier collection layer extending to the isolation area form a stacked structure;

[0011] Second conductive layer, set on the second carrier collection layer;

[0012] First insulating layer, set in the isolation area and connect the first carrier collection layer and the second carrier collection layer;

[0013] Second insulating layer, embedded in the stacked structure formed in the isolation area and located between the main surface of the first part and the main surface of the second part.

[0014] an isolation groove arranged in the isolation region and at least blocking electrical connection between the first conductive layer and the second conductive layer.

[0015] Optionally, the first carrier collection layer comprises a first intrinsic silicon-containing thin film layer and a first doped silicon-containing thin film layer arranged from inside to outside along the thickness direction of the silicon substrate.

[0016] Alternatively,

[0017] The first carrier collection layer comprises a tunneling oxide layer and a first doped polysilicon layer arranged from inside to outside along the thickness direction of the silicon substrate.

[0018] Optionally, the first insulating layer extends from the side surface of the first carrier collection layer to the second carrier collection layer, or the first insulating layer extends from the side surface of the second carrier collection layer to the first carrier collection layer.

[0019] Optionally, for the structure that the first insulating layer extends from the side surface of the first carrier collection layer to the second carrier collection layer and the first carrier collection layer comprises the first intrinsic silicon-containing thin film layer,

[0020] The first insulating layer is an intrinsic silicon-containing thin film layer, wherein the first insulating layer and the first doped silicon-containing thin film layer are an integral structure.

[0021] Preferably, for the structure that the first part of the first carrier collection layer extending to the isolation region is located at the inner side of the laminated structure, the first intrinsic silicon-containing thin film layer completely covers the isolation region.

[0022] Preferably, for the structure that the first part of the first carrier collection layer extending to the isolation region is located at the inner side of the laminated structure, the first doped silicon-containing thin film layer extends to the isolation region with a width of 1 μm to 100 μm.

[0023] Alternatively,

[0024] For the structure that the first insulating layer extends from the side surface of the first carrier collection layer to the second carrier collection layer and the first carrier collection layer comprises the tunneling oxide layer,

[0025] The first insulating layer is a polysilicon layer, wherein the polysilicon layer and the first doped polysilicon layer are an integral structure.

[0026] Preferably, for the structure that the first part of the first carrier collection layer extending to the isolation region is located at the inner side of the laminated structure, the tunneling oxide layer completely covers the isolation region.

[0027] Preferably, the first doped polysilicon layer extends to a width of 1-100 μm of the isolation region.

[0028] Optionally, the second carrier collection layer comprises a second intrinsic silicon-containing thin film layer and a second doped layer arranged from inside to outside along the thickness direction of the silicon substrate.

[0029] Preferably,

[0030] for the structure in which the first insulating layer extends from the side of the second carrier collection layer to the first carrier collection layer,

[0031] the first insulating layer is an intrinsic silicon-containing thin film layer, and the first insulating layer and the second doped layer are in an integral structure.

[0032] Optionally, for the structure in which a second part of the second carrier collection layer extending to the isolation region is located outside the laminated structure,

[0033] the isolation groove cuts off the second part of the second carrier collection layer extending to the isolation region.

[0034] Alternatively,

[0035] for the structure in which a first part of the first carrier collection layer extending to the isolation region is located outside the laminated structure, the isolation groove cuts off the first part of the first carrier collection layer extending to the isolation region.

[0036] Optionally, the first functional region, the isolation region and the second functional region are arranged alternately.

[0037] and / or,

[0038] The back contact heterojunction solar cell further comprises a passivation layer and an anti-reflection layer laminated on the second main surface of the silicon substrate.

[0039] and / or,

[0040] The back contact heterojunction solar cell further comprises a metal electrode separately arranged in the first functional region and the second functional region and electrically connected with the first conductive layer and the second conductive layer respectively.

[0041] Optionally, the first functional region and the second functional region are arranged staggeredly in the thickness direction of the silicon substrate.

[0042] Optionally, for the structure in which the silicon substrate is an N-type silicon substrate and the first carrier collection layer comprises the tunneling oxide layer,

[0043] the first carrier collection layer is an electron collection layer, and the second carrier collection layer is a hole collection layer.

[0044] Optionally, the second insulating layer has a thickness of 0.001-0.100 μm.

[0045] and / or,

[0046] The isolation region has a width of 1-150 μm.

[0047] The technical scheme of the first aspect of the utility model has the following advantages or beneficial effects:

[0048] The isolation region of the back contact heterojunction solar cell provided in the embodiment of the utility model is connected with the first carrier collection layer and the second carrier collection layer through the design of the first insulating layer and the second insulating layer embedded in the laminated structure formed by the isolation region and located between the main surface of the first part and the main surface of the second part, and the combination of the first insulating layer, the second insulating layer and the isolation groove, which can completely isolate the electrical contact between the first carrier collection layer and the second carrier collection layer, effectively ensure the electrical insulation of the isolation region, solve the problem of electric leakage of the back contact heterojunction solar cell due to poor electrical insulation of the isolation region, and effectively improve the conversion efficiency of the back contact heterojunction solar cell. BRIEF DESCRIPTION OF DRAWINGS

[0049] Figure 1 is a partial cross-sectional structure schematic view of a first structure of the back contact heterojunction solar cell according to the embodiment of the utility model;

[0050] Figure 2 is a partial cross-sectional structure schematic view of a second structure of the back contact heterojunction solar cell according to the embodiment of the utility model;

[0051] Figure 3 is a partial cross-sectional structure schematic view of a third structure of the back contact heterojunction solar cell according to the embodiment of the utility model.

[0052] The reference signs are as follows:

[0053] 10-silicon substrate; 11-first functional region; 12-isolation region; 13-second functional region; 20-first carrier collection layer; 21-tunneling oxide layer; 22-first doped polysilicon layer; 23-first intrinsic silicon-containing thin film layer; 24-first doped silicon-containing thin film layer; 30-first conductive layer; 40-second carrier collection layer; 41-second intrinsic silicon-containing thin film layer; 42-second doped layer; 50-second conductive layer; 61-first insulating layer; 62-second insulating layer; 63-isolation groove; 70-passivation layer; 80-antireflection layer; 90-metal electrode. DETAILED DESCRIPTION

[0054] In this embodiment of the invention, a structure, from the inside out, generally refers to the direction away from the structure, taking the structure as a reference. For example, in the thickness direction of the silicon substrate 10, from the inside out refers to the direction away from a main surface (such as the first main surface) of the silicon substrate 10, taking it as a reference. Correspondingly, the inner side of a structure refers to the portion of the structure close to the silicon substrate 10, and the outer side of a structure refers to the portion of the structure away from the silicon substrate 10.

[0055] In this embodiment of the invention, the first main surface and the second main surface of the silicon substrate 10 refer to two opposing main surfaces on the silicon substrate 10, one of which is the first main surface and the other is the second main surface. Furthermore, the main surface of a structure in this invention refers to a surface on the structure that extends in the same direction as the first or second main surface of the silicon substrate 10, or a surface on the structure that is parallel to the first or second main surface of the silicon substrate 10.

[0056] It is worth noting that the terms "first," "second," etc., mentioned in the embodiments of this utility model are used to distinguish different functional layers, functional parts, or functional regions, and are not intended to sort or number the functional layers, functional parts, or functional regions. For example, the first carrier collection layer 20 and the second carrier collection layer 40 are used to distinguish film layers that collect different carriers; the first doped polysilicon layer 22 and the second doped layer 42 are used to distinguish doped layers formed by different doping elements or doped layers with different doping types; the first functional region and the second functional region are used to distinguish p-type doped regions and n-type doped regions (e.g., if the first functional region is a p-type doped region, the second functional region is correspondingly an n-type doped region; if the first functional region is an n-type doped region, the first functional region is correspondingly a p-type doped region); and the first part and the second part are used to distinguish the part of the first carrier collection layer 20 that extends into the isolation region and the part of the second carrier collection layer that extends into the isolation region. Further, the part of the first carrier collection layer 20 that extends into the isolation region is called the first part, and the part of the second carrier collection layer that extends into the isolation region is called the second part.

[0057] The layered arrangement of multiple structures involved in this embodiment of the invention generally refers to one structure being laid on top of or below another structure. Correspondingly, a layered structure refers to a structure formed by at least two structures being layered.

[0058] It is worth noting that the fact that one structure in this embodiment is located on another structure does not specifically mean that the structure is located above another structure during the use of the back contact heterojunction solar cell. Rather, it means that the structure is formed on top of another structure when the main surface (such as the first main surface) of the back contact heterojunction solar cell where the two structures are located is facing upwards.

[0059] This invention improves the structure of back-contact heterojunction solar cells to solve the leakage problem in the isolation region between the n-type and p-type functional regions, thereby enhancing the performance and yield of back-contact heterojunction solar cells.

[0060] in, Figures 1 to 3 The following are partial cross-sectional schematic diagrams of three structures of the back-contact heterojunction solar cell provided in the embodiments of this utility model.

[0061] like Figures 1 to 3 As shown, the back-contact heterojunction solar cell provided in this embodiment of the present invention may include:

[0062] A silicon substrate 10, wherein a first functional region 11, an isolation region 12 and a second functional region 13 are arranged on the first main surface of the silicon substrate 10;

[0063] The first carrier collection layer 20 is disposed on the first functional region 11 and extends to the isolation region 12;

[0064] The first conductive layer 30 is disposed on the first carrier collection layer 20;

[0065] The second carrier collection layer 40 is disposed on the second functional region 13 and extends to the isolation region 12. The first carrier collection layer 20 and the second carrier collection layer 40 have opposite conductivity types. The second part of the second carrier collection layer 40 extending to the isolation region 12 and the first part of the first carrier collection layer 20 extending to the isolation region 12 form a stacked structure.

[0066] The second conductive layer 50 is disposed on the second carrier collection layer 40;

[0067] The first insulating layer 61 is disposed within the isolation region 12 and is connected to the first carrier collection layer 20 and the second carrier collection layer 40.

[0068] The second insulating layer 62 is embedded in the stacked structure formed within the isolation region 12 and is located between the main surface of the first part and the main surface of the second part.

[0069] An isolation groove 63 is disposed within the isolation zone 12 and at least blocks the electrical connection between the first conductive layer 30 and the second conductive layer 50.

[0070] The back-contact heterojunction solar cell provided in the above embodiments has an isolation region designed with a first insulating layer 61 connecting the first carrier collection layer 20 and the second carrier collection layer, and a second insulating layer 62 embedded in the stacked structure formed in the isolation region and located between the main surface of the first part and the main surface of the second part. The combination of the first insulating layer 61, the second insulating layer 62 and the isolation groove 63 can completely isolate the electrical contact between the first carrier collection layer 20 and the second carrier collection layer 40, effectively ensuring the electrical insulation of the isolation region, solving the leakage problem of the back-contact heterojunction solar cell due to poor electrical insulation of the isolation region, and effectively improving the conversion efficiency of the back-contact heterojunction solar cell.

[0071] Generally, the silicon substrate 10 used in this invention can be an N-type silicon substrate or a P-type silicon substrate. Preferably, the silicon substrate 10 is an N-type silicon substrate.

[0072] In addition, the main surface of the silicon substrate 10 can be either a textured surface or a planar surface.

[0073] Wherein, the first functional region 11 can be an N-type functional region, the first carrier collection layer 20 is an electron collection layer, and correspondingly, the second functional region 13 is a P-type functional region, and the second carrier collection layer 40 is a hole collection layer; the first functional region 11 can be a P-type functional region, the first carrier collection layer 20 is a hole collection layer; correspondingly, the second functional region 13 is an N-type functional region, and the second carrier collection layer 40 is an electron collection layer.

[0074] Among them, it can be like Figure 1 and Figure 2 As shown, only a first functional region 11, an isolation region 12, and a second functional region 13 are disposed on the first main surface of the silicon substrate 10.

[0075] Furthermore, the first functional region 11, the isolation region 12, and the second functional region 13 are arranged alternately on the first main surface of the silicon substrate 10. Specifically, this alternating arrangement means that the first functional region 11 and the second functional region 13 are arranged alternately, with the isolation region 12 located between adjacent first functional regions 11 and second functional regions 13. That is: first functional region 11 - isolation region 12 - second functional region 13 - isolation region 12 - first functional region 11 - second functional region 13 - ...

[0076] Furthermore, such as Figure 1 and Figure 2 As shown, the first functional region 11 and the second functional region 13 are staggered in the thickness direction of the silicon substrate 10, which can further prevent the first carrier collection layer 20 from contacting the second carrier collection layer 40 and prevent leakage of the back contact heterojunction solar cell.

[0077] The isolation zone 12 can have multiple structures. Specifically, the isolation zone 12 can be as follows: Figure 1 and Figure 3 As shown, a first portion of the first carrier collection layer 20 extending into the isolation region 12 is close to the silicon substrate 10, and a second portion of the second carrier collection layer 40 extending into the isolation region 12 is stacked on the outside of the first carrier collection layer 20. A second insulating layer 62 is provided between the main surface of the outer side of the first portion of the first carrier collection layer 20 extending into the isolation region 12 and the main surface of the inner side of the second portion of the second carrier collection layer 40 extending into the isolation region 12.

[0078] In addition, quarantine zone 12 can also be used as follows: Figure 2 As shown, the second portion of the second carrier collection layer 40 extending into the isolation region 12 is close to the silicon substrate 10. The first portion of the first carrier collection layer 20 extending into the isolation region 12 is stacked on the outside of the first carrier collection layer 20. A second insulating layer 62 is disposed between the main surface of the outer side of the second portion of the second carrier collection layer 40 extending into the isolation region 12 and the main surface of the inner side of the first portion of the first carrier collection layer 20 extending into the isolation region 12. The carriers collected by the first carrier collection layer 20 can be electrons, and correspondingly, the carriers collected by the second carrier collection layer 40 can be holes; or, the carriers collected by the first carrier collection layer 20 can be holes, and correspondingly, the carriers collected by the second carrier collection layer 40 can be electrons.

[0079] The side surface of the first carrier collection layer 20 generally refers to the surface perpendicular to the main surface of the first carrier collection layer 20 or the main surface of the silicon substrate 10. Similarly, the side surface of the second carrier collection layer 40 generally refers to the surface perpendicular to the main surface of the second carrier collection layer 40 or the main surface of the silicon substrate 10. It is worth noting that, as... Figure 1 and Figure 2 As shown, the side of the first carrier collection layer 20 or the side of the second carrier collection layer 40 connected to the first insulating layer 61 are opposite each other.

[0080] Furthermore, the relative positional relationship between the first insulating layer 61, the first carrier collection layer 20, and the second carrier collection layer 40 can be as follows: Figure 1 and Figure 3 As shown, the first insulating layer 61 extends from the side of the first carrier collection layer 20 to the second carrier collection layer 40. Alternatively, as... Figure 2 As shown, the first insulating layer 61 extends from the side of the second carrier collection layer 40 to the first carrier collection layer 20.

[0081] The thickness of the second insulating layer 62 can be 0.001μm to 0.1μm. For example, the thickness of the second insulating layer 62 can be 0.001μm, 0.002μm, 0.004μm, 0.0055μm, 0.008μm, 0.01μm, 0.011μm, 0.013μm, 0.014μm, 0.015μm, 0.02μm, 0.025μm, 0.028nm, 0.030μm, 0.035μm, 0.036μm, 0.040μm, 0.045μm, 0.047μm, 0.049μm, 0.050μm, 0.060μm, 0.065μm, 0.07μm, 0.08μm, 0.09μm, 0.1μm, etc. It is generally a single-layer or stacked film formed by chemical vapor deposition, plasma vapor deposition, physical vapor deposition, etc. Each layer of the single-layer or stacked film can include any one or more of silicon oxide, silicon nitride, and silicon oxynitride.

[0082] Furthermore, the width of the isolation region 12 is generally not less than 1 μm, and the width of the isolation region 12 is generally not greater than 150 μm. The width of the isolation region 12 generally refers to... Figure 1 The width of region C1 corresponding to the isolation groove 63 shown is the sum of the widths of the two regions C2 located on both sides of region C1. The width direction of the isolation area 12 is consistent with the direction in which the first functional area 11, the isolation area 12 and the second functional area 13 are arranged alternately. For example, the width of the isolation zone 12 can be 1μm, 5μm, 8μm, 10μm, 15μm, 20μm, 30μm, 40μm, 42μm, 45μm, 48μm, 50μm, 52μm, 55μm, 57μm, 59μm, 60μm, 70μm, 77μm, 80μm, 85μm, 90μm, 95μm, 100μm, 105μm, 110μm, 115μm, 118μm, 120μm, 125μm, 130μm, 135μm, 140μm, 145μm, or 150μm, etc.

[0083] Furthermore, the isolation trench 63 in the isolation region 12 achieves the purpose of blocking the electrical connection between the first functional region 11 and the second functional region 13. The isolation trench 63 can block only the first conductive layer 30 and the second conductive layer 50 without damaging other parts of other stacked structures in the isolation region 12 (such as the part of the first carrier collection layer 20 extending into the isolation region 12, the part of the second carrier collection layer 40 extending into the isolation region 12, the first insulating layer 61 and the second insulating layer 62); it can avoid damage to the first carrier collection layer 20 and the second carrier collection layer 40.

[0084] The first carrier collection layer 20 and the second carrier collection layer 40 will be described in detail below.

[0085] The first carrier collection layer 20 described above can have two structures.

[0086] Specifically, such as Figure 1 As shown, the first structure of the first carrier collection layer 20 may include a tunneling oxide layer 21 and a first doped polysilicon layer 22 disposed from the inside to the outside along the thickness direction of the silicon substrate 10. Regarding this first structure of the first carrier collection layer 20, since the formation process of the tunneling oxide layer 21 and the first doped polysilicon layer 22 involves a high-temperature treatment stage, the first structure of the first carrier collection layer 20 is generally prepared before the second carrier collection layer 40 during the fabrication process. Therefore, the relative relationship between the first structure of the first carrier collection layer 20 and the second carrier collection layer 40 is generally as follows: Figure 1 The relative relationships shown.

[0087] For the first structure of the first carrier collection layer 20, within the isolation region 12, the first portion of the first carrier collection layer 20 extending into the isolation region 12 is located inside the second insulating layer 62 (i.e., the first portion of the first carrier collection layer 20 extending into the isolation region 12 is located between the second insulating layer 62 and the silicon substrate 10), and the second portion of the second carrier collection layer 40 extending into the isolation region 12 is located outside the second insulating layer 62.

[0088] Furthermore, such as Figure 1 As shown, in the structure where the first insulating layer 61 extends from the side of the first carrier collection layer 20 to the second carrier collection layer 40 and cooperates with the first carrier collection layer 20 in a first structural configuration, the first insulating layer 61 is a polycrystalline silicon layer, and the first insulating layer 61 and the first doped polycrystalline silicon layer 22 are integrally formed. Specifically, the process of forming the first doped polycrystalline silicon layer 22 mainly consists of two steps: first, forming a silicon-containing thin film layer on the tunneling oxide layer 21; second, doping a portion of the silicon-containing thin film layer and performing high-temperature annealing treatment, wherein the doped portion forms the first doped polycrystalline silicon layer 22, while the undoped portion forms the first insulating layer 61. In addition, for the structure in which the first insulating layer 61 extends from the side of the first carrier collection layer 20 to the second carrier collection layer 40 and cooperates with the first structure of the first carrier collection layer 20, the first part of the first carrier collection layer 20 extending to the isolation region 12 is a combination structure of the part of the tunnel oxide layer 21 extending to the isolation region 12 and the part of the first doped polysilicon layer 22 extending to the isolation region 12.

[0089] The tunneling oxide layer 21 is generally a silicon oxide layer formed by thermal oxidation, chemical oxidation, chemical vapor deposition, plasma vapor deposition, physical vapor deposition, etc., and its thickness is generally 0.0005 μm to 0.003 μm. For example, the thickness of the tunneling oxide layer 21 can be 0.0005 μm, 0.0008 μm, 0.001 μm, 0.0013 μm, 0.0015 μm, 0.0018 μm, 0.002 μm, 0.0022 μm, 0.0025 μm, 0.0028 μm, 0.003 μm, etc.

[0090] The aforementioned first doped polysilicon layer 22 is generally a doped polysilicon layer with a thickness of 0.03 μm to 0.3 μm. For example, the thickness of the first doped layer 22 can be 0.030 μm, 0.036 μm, 0.04 μm, 0.055 μm, 0.075 μm, 0.085 μm, 0.095 μm, 0.11 μm, 0.13 μm, 0.15 μm, 0.18 μm, 0.2 μm, 0.21 μm, 0.23 μm, 0.24 μm, 0.26 μm, 0.28 μm, 0.3 μm, etc.

[0091] The tunneling oxide layer 21 completely covers the isolation region 12, meaning that the tunneling oxide layer 21 can exist in the entire area of ​​the isolation region 12. During the preparation process, the tunneling oxide layer 21 can be formed on the entire first main surface of the silicon substrate 10. Then, the portion of the tunneling oxide layer 21 on the second region 13 is removed, leaving the portion on the isolation region 12. This can prevent the first carrier collection layer 20 from being damaged, improve the process window, and thus improve the yield of the back contact heterojunction solar cell.

[0092] For a silicon substrate 10 that is an N-type silicon substrate and a first carrier collection layer 20 that includes a tunneling oxide layer 21, the first carrier collection layer 20 is generally an electron collection layer and the second carrier collection layer 40 is a hole collection layer.

[0093] In addition, such as Figure 2 and Figure 3 As shown, the second structure of the first carrier collection layer 20 may include a first intrinsic silicon-containing thin film layer 23 and a first doped silicon-containing thin film layer 24 disposed from the inside to the outside along the thickness direction of the silicon substrate 10. This second structure of the first carrier collection layer 20 is generally formed under low-temperature conditions; therefore, the second structure of the first carrier collection layer 20 can be prepared before or after the second carrier collection layer 40.

[0094] Specifically, regarding the second structure of the first carrier collection layer 20, within the isolation region 12, the first portion of the first carrier collection layer 20 extending into the isolation region 12 and the second portion of the second carrier collection layer 40 extending into the isolation region 12 can have two relative positional relationships. The first relative positional relationship can be as follows: Figure 2 As shown, the first portion of the first carrier collection layer 20 extending to the isolation region 12 is located outside the second insulating layer 62, and the second portion of the second carrier collection layer 40 extending to the isolation region 12 is located inside the second insulating layer 62. The second relative positional relationship can be described as follows: Figure 3 As shown, the second portion of the second carrier collection layer 40 extending to the isolation region 12 is located outside the second insulating layer 62, and the first portion of the first carrier collection layer 20 extending to the isolation region 12 is located inside the second insulating layer 62.

[0095] More specifically, regarding the second structure of the first carrier collection layer 20 and the structure in which the first insulating layer 61 extends from the side of the second carrier collection layer 40 to the first carrier collection layer 20 to cooperate, within the isolation region 12, the first portion of the first carrier collection layer 20 extending into the isolation region 12 and the second portion of the second carrier collection layer 40 extending into the isolation region 12 are... Figure 2 The first relative positional relationship is shown. The formation process of the first insulating layer 61 in this structure will be described in detail later and will not be repeated here.

[0096] Furthermore, such as Figure 2 As shown, for the first relative positional relationship, the isolation trench 63 further cuts off the first carrier collection layer 20 extending into the isolation region 12 to further improve the isolation effect of the isolation region 12.

[0097] Furthermore, regarding the second structure of the first carrier collection layer 20 that mates with the first insulating layer 61 extending from the side of the first carrier collection layer 20 to the second carrier collection layer 40, within the isolation region 12, the first portion of the first carrier collection layer 20 extending into the isolation region 12 and the second portion of the second carrier collection layer 40 extending into the isolation region 12 are... Figure 3 The second type of relative positional relationship is shown. (Regarding...) Figure 3In the second relative positional relationship shown, the first insulating layer 61 is an intrinsic silicon-containing thin film layer, which is integrally structured with the first doped silicon-containing thin film layer 24. The formation process of the first insulating layer 61 mainly involves: after preparing the first intrinsic silicon-containing thin film layer 23 for the second structure of the first carrier collection layer 20, a new intrinsic silicon-containing thin film layer is stacked on top of the first intrinsic silicon-containing thin film layer 23, and a portion of this new intrinsic silicon-containing thin film layer is doped to form the first doped silicon-containing thin film layer 24. The doped portion of this new intrinsic silicon-containing thin film layer is the first doped silicon-containing thin film layer 24, and the undoped portion is the first insulating layer 61. Furthermore, regarding the second structure of the first carrier collection layer 20 and the structure in which the first insulating layer 61 extends from the side of the first carrier collection layer 20 to the second carrier collection layer 40, the first portion of the first carrier collection layer 20 extending to the isolation region 12 is a combination of the portion of the first intrinsic silicon-containing thin film layer 23 extending to the isolation region 12 and the portion of the first doped silicon-containing thin film layer 24 extending to the isolation region 12.

[0098] In addition, for the second structure of the first carrier collection layer 20 and the structure in which the first insulating layer 61 extends from the side of the first carrier collection layer 20 to the second carrier collection layer 40, the first part of the first carrier collection layer 20 extending to the isolation region 12 is located inside the stacked structure, and the first intrinsic silicon-containing thin film layer 23 completely covers the isolation region 12.

[0099] Furthermore, targeting Figure 3 In the structure shown, the isolation trench 63 further cuts off the second carrier collection layer 40 extending into the isolation region 12 to further improve the isolation effect of the isolation region 12.

[0100] Regardless of the above Figure 2 The relative positional relationship shown is still Figure 3 The relative positional relationships shown are for Figure 2 and Figure 3 The second structure of the first carrier collection layer 20 shown typically includes a first intrinsic silicon-containing thin film layer 23 with a thickness of 0.0005 μm to 0.01 μm. For example, the thickness of the first intrinsic silicon-containing thin film layer 23 can be 0.0005 μm, 0.001 μm, 0.003 μm, 0.005 μm, 0.007 μm, 0.008 μm, 0.009 μm, 0.01 μm, etc. Correspondingly, the first doped silicon-containing thin film layer 24 is a single layer or stacked film layer formed from one or more of doped amorphous silicon, doped microcrystalline silicon, and doped nanocrystalline silicon. The thickness of this first doped silicon-containing thin film layer 24 can be 0.0005 μm to 0.003 μm. For example, the thickness of the first doped silicon thin film layer 24 can be 0.0005μm, 0.001μm, 0.015μm, 0.02μm, etc.

[0101] Furthermore, such as Figures 1 to 3 As shown, the second carrier collection layer 40 may include a second intrinsic silicon-containing thin film layer 41 and a second doped layer 42 disposed from the inside to the outside along the thickness direction of the silicon substrate 10.

[0102] Specifically, as described above, for the structure in which the second carrier collection layer 40, including the second intrinsic silicon-containing thin film layer 41 and the second doped layer 42, cooperates with the first structure of the first carrier collection layer 20 (the first carrier collection layer 20 including the tunneling oxide layer 21 and the first doped polysilicon layer 22), the relative positional relationship between the second portion of the second carrier collection layer 40 extending to the isolation region 12 and the first portion of the first carrier collection layer 20 extending to the isolation region 12 is only... Figure 1 In one embodiment, the first portion of the first carrier collection layer 20 extending into the isolation region 12 is located inside the second insulating layer 62, and the second portion of the second carrier collection layer 40 extending into the isolation region 12 is located outside the second insulating layer 62. For a structure in which the second carrier collection layer 40, including the second intrinsic silicon-containing thin film layer 41 and the second doped layer 42, cooperates with the first structure of the first carrier collection layer 20 described above, the second portion of the second carrier collection layer 40 extending into the isolation region 12 is a combination of the portion of the second intrinsic silicon-containing thin film layer 41 extending into the isolation region 12 and the portion of the second doped layer 42 extending into the isolation region 12.

[0103] Furthermore, as described above, for the structure in which the second carrier collection layer 40, including the second intrinsic silicon-containing thin film layer 41 and the second doped layer 42, cooperates with the second structure of the first carrier collection layer 20 (the first carrier collection layer 20 including the first intrinsic silicon-containing thin film layer 23 and the first doped silicon-containing thin film layer 24), the relative positional relationship between the second portion of the second carrier collection layer 40 extending into the isolation region 12 and the first portion of the first carrier collection layer 20 extending into the isolation region 12 can be as follows: Figure 2 and Figure 3 The two types shown.

[0104] against Figure 2 As shown in the relative positional relationship, the first insulating layer 61 extends from the side of the second carrier collection layer 40 to the first carrier collection layer 20.

[0105] More specifically, targeting Figure 2The relative positions shown indicate that the first insulating layer 61 is an intrinsic silicon-containing thin film layer, wherein the first insulating layer 61 and the second doped layer 42 are integrally formed. The formation process of the first insulating layer 61 is as follows: first, a second intrinsic silicon-containing thin film layer 41 is formed in the second carrier collection layer 40; then, a new intrinsic silicon-containing thin film layer is stacked on the second intrinsic silicon-containing thin film layer 41; then, the new intrinsic silicon-containing thin film layer is partially doped, wherein the doped portion is the second doped layer 42, and the undoped portion is the first insulating layer 61. Figure 2 In the relative positional relationship shown, the second part of the second carrier collection layer 40 extending into the isolation region 12 is a combination structure of the part of the second intrinsic silicon-containing thin film layer 41 extending into the isolation region 12 and the part of the second doped layer 42 extending into the isolation region 12.

[0106] In addition, regarding Figure 2 As shown in the relative positional relationship, the second intrinsic silicon-containing thin film layer 41 included in the second carrier collection layer 40 completely covers the isolation region 12, that is, the second intrinsic silicon-containing thin film layer 41 can exist in the entire region of the isolation region 12. During the preparation process, the second intrinsic silicon-containing thin film layer 41 can be formed on the entire first main surface of the silicon substrate 10. Then, the portion of the second intrinsic silicon-containing thin film layer 41 on the first region 11 is removed, leaving the portion on the isolation region 12. This can avoid damage to the second intrinsic silicon-containing thin film layer 41, improve the process window, and thus improve the yield of the back contact heterojunction solar cell.

[0107] In addition, such as Figure 3 As shown in the relative positions, the first portion of the first carrier collection layer 20 extending into the isolation region 12 is located inside the stacked structure, the first intrinsic silicon-containing thin film layer 23 completely covers the isolation region 12, and the second portion of the second carrier collection layer 40 extending into the isolation region 12 is located outside the stacked structure. The structure where the second portion of the second carrier collection layer 40 extending into the isolation region 12 is located outside the stacked structure has already been explained above and will not be repeated here.

[0108] As can be seen from the above, the first insulating layer 61 is formed simultaneously with the first carrier collection layer 20 or the second carrier collection layer 40.

[0109] In cases where the first insulating layer 61 and the first carrier collection layer 20 are formed simultaneously, the first insulating layer 61 will also be different for different structures of the first carrier collection layer 20.

[0110] Specifically, for the first structure of the first carrier collection layer 20 described above, the first insulating layer 61 is generally a polycrystalline silicon layer, wherein the polycrystalline silicon layer and the first doped polycrystalline silicon layer 22 are integrally formed. The first insulating layer 61 is formed as follows: during the preparation of the first doped polycrystalline silicon layer 22, the first polycrystalline silicon layer is first formed, and then, during the doping of the first polycrystalline silicon layer with doping elements, doping is performed in regions other than the first insulating layer 61. This doping process can be implemented using existing doping methods, which will not be elaborated here. The undoped regions constitute the first insulating layer 61.

[0111] Among them, for the first structure of the first carrier collection layer 20 mentioned above, such as Figure 1 As shown, the width D of the first doped polysilicon layer 22 extending into the isolation region 12 is generally 1 μm to 100 μm. For example, the width D of the first doped polysilicon layer 22 extending into the isolation region 12 can be 1 μm, 5 μm, 10 μm, 20 μm, 40 μm, 50 μm, 70 μm, 80 μm, 90 μm, or 100 μm, etc. Preferably, the width D of the first doped polysilicon layer 22 extending into the isolation region 12 is generally smaller than the width of the isolation region 12. Alternatively, the width D of the first doped polysilicon layer 22 extending into the isolation region 12 can also be the same as the width of the isolation region 12. For this structure, the first insulating layer 61 can be omitted, that is, the first insulating layer 61 is completely replaced by the first portion of the first doped polysilicon layer 22 extending into the isolation region 12.

[0112] With the above structure, the first insulating layer 61 can completely isolate the first doped polycrystalline silicon layer 22 from contact with the second carrier collection layer 40 in the extension direction of the first doped polycrystalline silicon layer 22, thereby solving the leakage problem caused by the contact between the first doped polycrystalline silicon layer 22 and the second carrier collection layer 40, without increasing the manufacturing process, effectively controlling the cost while solving the leakage problem and improving the photoelectric conversion efficiency of the back contact heterojunction solar cell.

[0113] Furthermore, regarding the second structure of the first carrier collection layer 20 (i.e., the structure in which the first carrier collection layer 20 includes the first intrinsic silicon-containing thin film layer 23), where the first carrier collection layer 20 is prepared first and the second carrier collection layer 40 is prepared later (i.e., the first portion of the first carrier collection layer 20 extending to the isolation region 12 is located inside the stacked structure, and the second portion of the second carrier collection layer 40 extending to the isolation region 12 is located outside the stacked structure), the first insulating layer 61 is generally an intrinsic silicon-containing thin film layer, wherein the first insulating layer 61 and the first doped silicon-containing thin film layer 24 are an integral structure.

[0114] Furthermore, regarding the structure where the first carrier collection layer 20 includes a first intrinsic silicon-containing thin film layer 23, and the first carrier collection layer 20 is fabricated first, followed by the second carrier collection layer 40 (i.e., ... Figure 3 As shown, the first portion of the first carrier collection layer 20 extending to the isolation region 12 is located inside the stacked structure, and the second portion of the second carrier collection layer 40 extending to the isolation region 12 is located outside the stacked structure. The first insulating layer 61 is formed as follows: during the preparation of the first doped silicon-containing thin film layer 24, a first intrinsic silicon-containing thin film layer 23 is first formed. Then, during the doping of the surface of the first intrinsic silicon-containing thin film layer 23, doping is performed in regions other than the first insulating layer 61. This doping process can be implemented using existing doping methods, which will not be elaborated here. The undoped region is the first insulating layer 61. The first insulating layer 61 is generally a single-layer or multi-layer film formed from one or more of amorphous silicon, microcrystalline silicon, and nanocrystalline silicon.

[0115] Specifically, the first portion of the first carrier collection layer 20 extending into the isolation region 12 is located inside the stacked structure, and the width of the first doped silicon-containing thin film layer 24 extending into the isolation region 12 is 1 μm to 100 μm. For example, the width of the first doped silicon-containing thin film layer 24 extending into the isolation region 12 can be 1 μm, 5 μm, 10 μm, 20 μm, 40 μm, 50 μm, 70 μm, 80 μm, 90 μm, or 100 μm, etc. It is worth noting that the width of the first doped silicon-containing thin film layer 24 extending into the isolation region 12 is generally smaller than the width of the isolation region 12.

[0116] Furthermore, regarding the second structure of the first carrier collection layer 20 (i.e., the structure in which the first carrier collection layer 20 includes the first intrinsic silicon-containing thin film layer 23), in the case where the second carrier collection layer 40 is prepared first and the first carrier collection layer 20 is prepared later (i.e., as...) Figure 2 The second portion of the second carrier collection layer 40 extending into the isolation region 12 is located inside the stacked structure, while the first portion of the first carrier collection layer 20 extending into the isolation region 12 is located outside the stacked structure. Figure 2 As shown, the first insulating layer 61 is generally also an intrinsic silicon-containing thin film layer, wherein the first insulating layer 61 and the second doped layer 42 in the second carrier collection layer 40 are an integral structure.

[0117] In the case where the first carrier collection layer 20 includes a first intrinsic silicon-containing thin film layer 23, and the second carrier collection layer 40 is fabricated first, followed by the first carrier collection layer 20 (i.e., ... Figure 2The second portion of the second carrier collection layer 40 extending into the isolation region 12 is located inside the stacked structure, and the first portion of the first carrier collection layer 20 extending into the isolation region 12 is located outside the stacked structure. The first insulating layer 61 is formed as follows: during the preparation of the second doped layer 42 in the second carrier collection layer 40, a second intrinsic silicon-containing thin film layer 41 is first formed. Then, during the doping of the surface of the second intrinsic silicon-containing thin film layer 41, doping is performed in regions other than the first insulating layer 61. This doping process can be achieved using existing doping methods, which will not be elaborated here. The undoped region is the first insulating layer 61. The first insulating layer 61 is generally a single-layer or multi-layer film formed from one or more of amorphous silicon, microcrystalline silicon, and nanocrystalline silicon.

[0118] Furthermore, such as Figures 1 to 3 As shown, the second carrier collection layer 40 may include a second intrinsic silicon-containing thin film layer 41 and a second doped layer 42 disposed from the inside to the outside along the thickness direction of the silicon substrate 10.

[0119] Furthermore, the first intrinsic silicon-containing thin film layer 23 of the first carrier collection layer 20 and the second intrinsic silicon-containing thin film layer 41 of the second carrier collection layer 40 are generally formed by the same single-layer or multi-layer film using the same technical means. This technical means can be implemented using existing techniques and will not be elaborated upon here. It is worth noting that the formation of the first intrinsic silicon-containing thin film layer 23 and the formation of the second intrinsic silicon-containing thin film layer 41 do not restrict each other. Each of the single-layer or multi-layer films forming the first intrinsic silicon-containing thin film layer 23 and the second intrinsic silicon-containing thin film layer 41 includes one or more of microcrystalline silicon, nanocrystalline silicon, amorphous silicon, silicon oxide, and silicon carbide. Among these, microcrystalline silicon, nanocrystalline silicon, and amorphous silicon are all silicon with different structures or crystal forms.

[0120] The second doped layer 42 is generally a single-layer silicon-containing thin film or a stacked silicon-containing thin film doped with a doping element. Each silicon-containing thin film in the single-layer or stacked silicon-containing thin film can be formed by chemical vapor deposition, plasma vapor deposition, physical vapor deposition, or other methods. The thickness of the second doped layer 42 can be greater than 0 μm and less than or equal to 0.015 μm. For example, the thickness of the second doped layer 42 can be 0.0002μm, 0.0004μm, 0.0006μm, 0.001μm, 0.0012μm, 0.0016μm, 0.002μm, 0.004μm, 0.005μm, 0.007μm, 0.008μm, 0.009μm, 0.010μm, 0.011μm, 0.012μm, 0.013μm, 0.014μm, 0.015μm, etc.

[0121] The second intrinsic silicon-containing thin film layer 41 and the tunneling oxide layer 21 of the first carrier collection layer 20 (or the first intrinsic silicon-containing thin film layer 23 of the first carrier collection layer 20) are offset in the thickness direction of the silicon substrate 10 to avoid contact between the second intrinsic silicon-containing thin film layer 41 and the tunneling oxide layer 21 (or the first intrinsic silicon-containing thin film layer 23).

[0122] Furthermore, for the structure where the first portion of the first carrier collection layer 20 extending to the isolation region 12 is located outside the stacked structure, the isolation trench 63 cuts off the first portion extending into the isolation region 12. For the structure where the second portion of the second carrier collection layer 40 extending to the isolation region 12 is located outside the stacked structure, the isolation trench 63 further cuts off the second portion extending into the isolation region 12. This further improves the insulation of the isolation region 12. Specifically, the isolation trench 63 cuts off the first doped polysilicon layer 22 or the first doped silicon-containing thin film layer 24 of the first carrier collection layer 20 or the second doped layer 42 of the second carrier collection layer 40.

[0123] Furthermore, such as Figures 1 to 3 As shown, the back-contact heterojunction solar cell may further include a passivation layer 70 and an antireflection layer 80 stacked on the second main surface of the silicon substrate 10. The passivation layer 70 and the antireflection layer 80 can effectively improve the photoelectric conversion efficiency of the back-contact heterojunction solar cell. The antireflection layer 80 can be at least one of aluminum oxide, silicon oxide, gallium oxide, silicon nitride, aluminum nitride, silicon oxynitride, aluminum oxynitride, magnesium fluoride, lithium fluoride, ITO, and zinc oxide. The thickness of the antireflection layer 80 can be 0.040 μm to 0.200 μm. For example, the thickness of the antireflection layer 80 can be 0.040 μm, 0.050 μm, 0.080 μm, 0.100 μm, 0.120 μm, 0.150 μm, 0.170 μm, 0.180 μm, 0.200 μm, etc.

[0124] Furthermore, such as Figures 1 to 3 As shown, the back-contact heterojunction solar cell further includes: metal electrodes 90 disposed in the first functional region 11 and the second functional region 13, and electrically connected to the first conductive layer 30 and the second conductive layer 50, respectively. Specifically, the metal electrode 90 disposed in the first functional region 11 is electrically connected to the first conductive layer 30; the metal electrode 90 disposed in the second functional region 13 is electrically connected to the second conductive layer 50.

[0125] The first conductive layer 30 disposed on the first carrier collection layer 20 and the second conductive layer 50 disposed on the second carrier collection layer 40 can be formed simultaneously. The first conductive layer 30 and the second conductive layer 50, formed simultaneously in the first functional region 11 and the second functional region 13, are generally formed by doping metal elements with a single-layer or multi-layer thin film of metal oxide and / or nitride. The metal oxide is one or more combinations of indium oxide, tin oxide, zinc oxide, cadmium oxide, and titanium nitride; the metal nitride is titanium nitride; and the doping elements in the first conductive layer 30 and the second conductive layer 50 are one or more of indium, tin, calcium, aluminum, cadmium, zinc, cerium, and fluorine.

[0126] Each functional layer in the first functional region 11 and each functional layer in the second functional region 13 formed by this invention can be formed on the entire first main surface of the silicon substrate 10, without the need for special treatment of the isolation region 12, such as covering, so as to effectively reduce the processing steps of the back contact heterojunction solar cell and make the entire back contact heterojunction solar cell convenient for industrial production.

[0127] Regardless Figure 1 ,still Figure 2 or Figure 3 The back-contact heterojunction solar cell shown has an isolation region 12 that is essentially the intersection of the first functional region 11 and the second functional region 13. Figure 1 Taking the structure shown as an example, the intersection area can be divided into a first intersection area C1 corresponding to the isolation groove 63 and a second intersection area C2 located on both sides of the first intersection area C1 and adjacent to the first functional area 11 and the second functional area 13, respectively. Figure 1 An example is provided showing that the first cross region C1 corresponding to the isolation trench 63 includes a tunneling oxide layer 21, a first insulating layer 61, and a second insulating layer 62 stacked from the inside out. Additionally, the second cross region C2 includes a tunneling oxide layer 21, a first insulating layer 61, a second insulating layer 62, a second intrinsic silicon-containing thin film layer 41, a second doped layer 42, and conductive layers (a first conductive layer 30 adjacent to the first functional region 11 and a second conductive layer 50 adjacent to the second functional region 13) stacked from the inside out.

[0128] The above steps are provided only to help understand the method, structure, and core idea of ​​this utility model. For those skilled in the art, various improvements and modifications can be made to this utility model without departing from its principles, and these improvements and modifications also fall within the scope of protection of the claims of this utility model.

Claims

1. A back-contact heterojunction solar cell, characterized in that, include: A silicon substrate (10), wherein a first functional region (11), an isolation region (12) and a second functional region (13) are arranged on the first main surface of the silicon substrate (10); A first carrier collection layer (20) is disposed on the first functional region (11) and extends to the isolation region (12); A first conductive layer (30) is disposed on the first carrier collection layer (20); A second carrier collection layer (40) is disposed on the second functional region (13) and extends to the isolation region (12), wherein the first carrier collection layer (20) and the second carrier collection layer (40) have opposite conductivity types, and the second portion of the second carrier collection layer (40) extending to the isolation region (12) and the first portion of the first carrier collection layer (20) extending to the isolation region (12) form a stacked structure; A second conductive layer (50) is disposed on the second carrier collection layer (40); A first insulating layer (61) is disposed within the isolation region (12) and connects the first carrier collection layer (20) and the second carrier collection layer (40); The second insulating layer (62) is embedded in the stacked structure formed within the isolation region (12) and is located between the main surface of the first part and the main surface of the second part; An isolation groove (63) is disposed within the isolation area (12) and at least blocks the electrical connection between the first conductive layer (30) and the second conductive layer (50).

2. The back-contact heterojunction solar cell according to claim 1, characterized in that, The first carrier collection layer (20) includes a first intrinsic silicon-containing thin film layer (23) and a first doped silicon-containing thin film layer (24) disposed from the inside to the outside along the thickness direction of the silicon substrate (10).

3. The back-contact heterojunction solar cell according to claim 1, characterized in that, The first carrier collection layer (20) includes a tunneling oxide layer (21) and a first doped polycrystalline silicon layer (22) disposed from the inside to the outside along the thickness direction of the silicon substrate (10).

4. The back-contact heterojunction solar cell according to any one of claims 1 to 3, characterized in that, The first insulating layer (61) extends from the side of the first carrier collection layer (20) to the second carrier collection layer (40), or the first insulating layer (61) extends from the side of the second carrier collection layer (40) to the first carrier collection layer (20).

5. The back-contact heterojunction solar cell according to claim 4, characterized in that, For a structure in which the first insulating layer (61) extends from the side of the first carrier collection layer (20) to the second carrier collection layer (40) and the first carrier collection layer (20) includes a first intrinsic silicon-containing thin film layer (23), The first insulating layer (61) is an intrinsic silicon-containing thin film layer, wherein the first insulating layer (61) and the first doped silicon-containing thin film layer (24) stacked on the outside of the first intrinsic silicon-containing thin film layer (23) included in the first carrier collection layer (20) are an integral structure.

6. The back-contact heterojunction solar cell according to claim 5, characterized in that, The first portion of the first carrier collection layer (20) containing the first intrinsic silicon thin film layer (23) and the first doped silicon thin film layer (24) extending to the isolation region (12) is located inside the stacked structure, and the first intrinsic silicon thin film layer (23) completely covers the isolation region (12).

7. The back-contact heterojunction solar cell according to claim 5, characterized in that, The first portion of the first carrier collection layer (20) containing the first intrinsic silicon thin film layer (23) and the first doped silicon thin film layer (24) extending to the isolation region (12) is located inside the stacked structure, and the width of the first doped silicon thin film layer (24) extending to the isolation region (12) is 1 μm to 100 μm.

8. The back-contact heterojunction solar cell according to claim 4, characterized in that, For a structure in which the first insulating layer (61) extends from the side of the first carrier collection layer (20) to the second carrier collection layer (40) and the first carrier collection layer (20) includes a tunneling oxide layer (21), The first insulating layer (61) is a polycrystalline silicon layer, wherein the polycrystalline silicon layer and the first doped polycrystalline silicon layer (22) stacked on the outside of the tunneling oxide layer (21) are an integral structure.

9. The back-contact heterojunction solar cell according to claim 8, characterized in that, The first portion of the first carrier collection layer (20), which includes a tunneling oxide layer (21) and a first doped polysilicon layer (22), extending into the isolation region (12) is located inside the stacked structure, and the tunneling oxide layer (21) completely covers the isolation region (12).

10. The back-contact heterojunction solar cell according to claim 9, characterized in that, The width of the first doped polysilicon layer (22) extending into the isolation region (12) is 1 μm to 100 μm.

11. The back-contact heterojunction solar cell according to claim 1, characterized in that, The second carrier collection layer (40) includes a second intrinsic silicon-containing thin film layer (41) and a second doped layer (42) disposed from the inside to the outside along the thickness direction of the silicon substrate (10).

12. The back-contact heterojunction solar cell according to claim 11, characterized in that, Regarding the structure in which the first insulating layer (61) extends from the side of the second carrier collection layer (40) to the first carrier collection layer (20), The first insulating layer (61) is an intrinsic silicon-containing thin film layer, wherein the first insulating layer (61) and the second doped layer (42) are an integral structure.

13. The back-contact heterojunction solar cell according to claim 1, characterized in that, For the structure in which the second portion of the second carrier collection layer (40) extending to the isolation region (12) is located outside the stacked structure, The isolation groove (63) cuts off a second portion of the second carrier collection layer (40) extending into the isolation region (12); or, For a structure in which the first portion of the first carrier collection layer (20) extending to the isolation region (12) is located outside the stacked structure, the isolation groove (63) cuts off the first portion of the first carrier collection layer (20) extending into the isolation region (12).

14. The back-contact heterojunction solar cell according to any one of claims 1 to 3, 11, and 12, characterized in that, The first functional area (11), the isolation area (12), and the second functional area (13) are arranged alternately; And / or, The back-contact heterojunction solar cell further includes: a passivation layer (70) and an anti-reflection layer (80) stacked on the second main surface of the silicon substrate (10); And / or, The back-contact heterojunction solar cell further includes: a metal electrode (90) disposed in the first functional region (11) and the second functional region (13) and electrically connected to the first conductive layer (30) and the second conductive layer (50) respectively.

15. The back-contact heterojunction solar cell according to any one of claims 1 to 3 and 11, characterized in that, The first functional area (11) and the second functional area (13) are offset in the thickness direction of the silicon substrate (10).

16. The back-contact heterojunction solar cell according to claim 3, characterized in that, For the silicon substrate (10) being an N-type silicon substrate, and the first carrier collection layer (20) including the tunneling oxide layer (21), The first carrier collection layer (20) is an electron collection layer, and the second carrier collection layer (40) is a hole collection layer.

17. The back-contact heterojunction solar cell according to any one of claims 1 to 3, 11, and 12, characterized in that, The thickness of the second insulating layer (62) is 0.001 μm to 0.100 μm; And / or, The width of the isolation zone (12) is 1μm to 150μm.

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