Display device

Abstract

The utility model relates to a display device. A display device according to an embodiment may include: a substrate including a display area and a non-display area; a thin film transistor on the substrate; a planarization layer disposed on the thin film transistor; the through hole layer is configured on the planarization layer, provided with a groove in the display area and provided with an alignment mark in the non-display area; the sub-pixel comprises a first electrode, an organic light-emitting layer and a second electrode which are configured corresponding to the groove; and a pixel defining layer defining a sub-pixel on the through hole layer, the first electrode being electrically connected to the thin film transistor and including an inclined electrode extending along an inclined surface of the through hole layer.

Description

Technical Field

[0001] This utility model relates to a display device. Background Technology

[0002] With the development of multimedia, the importance of display devices is increasing. Correspondingly, various types of display devices, such as Liquid Crystal Display (LCD) and Organic Light Emitting Display (OLED), are being used.

[0003] In display devices, images are displayed using organic light-emitting elements that generate light through the recombination of electrons and holes. Display devices offer advantages such as fast response times, high brightness and viewing angles, and low power consumption. Utility Model Content

[0004] The problem to be solved by this invention is to provide a display device for preventing screen stains and the like from being caused by the tilted portion of the first electrode being covered by the pixel defining layer.

[0005] The problems to be solved by this utility model are not limited to those mentioned above. Those skilled in the art can clearly understand other problems not mentioned from the following description.

[0006] A display device according to an embodiment of the present invention for solving the aforementioned problem may include: a substrate including a display area and a non-display area; a thin-film transistor on the substrate; a planarization layer disposed on the thin-film transistor; a via layer disposed on the planarization layer, having a groove in the display area and an alignment mark in the non-display area; a sub-pixel including a first electrode, an organic light-emitting layer, and a second electrode disposed corresponding to the groove; and a pixel defining layer defining the sub-pixel on the via layer, wherein the first electrode is electrically connected to the thin-film transistor and includes an inclined electrode disposed along an inclined surface of the via layer.

[0007] In one embodiment, the first electrode may further include: a lower electrode extending from the lower end of the inclined electrode and disposed within the groove; and an upper electrode extending from the upper end of the inclined electrode and disposed on the via layer.

[0008] The upper electrode may include one or more of a masking portion that overlaps with the pixel defining layer and an exposed portion that does not overlap with the pixel defining layer.

[0009] In one embodiment, the exposed portion may have a length of 1 μm to 2 μm.

[0010] In one embodiment, the organic light-emitting layer may be configured to overlap with the lower electrode, the tilted electrode, and the upper electrode.

[0011] In one embodiment, the pixel defining layer may expose at least a portion of the second flat portion.

[0012] In one embodiment, the pixel defining layer may be in direct contact with the top surface of the via layer.

[0013] In one embodiment, the alignment mark may be composed of the same material as the via layer.

[0014] In one embodiment, the alignment mark may be formed by a grooved pattern that recesses a portion of the upper part of the via layer.

[0015] In one embodiment, the alignment mark may comprise ink that fills the grooved pattern, the ink having a different color than the upper surface of the through-hole layer.

[0016] In one embodiment, the display device further includes a thin-film encapsulation layer disposed on the sub-pixels and the pixel delimiting layer.

[0017] Alternatively, a method for manufacturing a display device according to another embodiment may include: a step of forming a planarization layer on a substrate having thin-film transistors; a step of forming an organic layer on the planarization layer; a step of patterning the organic layer to form a via layer having grooves and alignment marks; a step of forming a first electrode electrically connected to the thin-film transistors and including a tilted electrode disposed along a tilted surface of the grooves; and a step of forming a pixel defining layer on the via layer that exposes at least a portion of the first electrode using the alignment marks.

[0018] In one embodiment, the step of forming the first electrode may further include forming: a lower electrode extending from the lower end of the inclined electrode and disposed within the groove; and an upper electrode extending from the upper end of the inclined electrode and disposed on the via layer.

[0019] In one embodiment, the method of manufacturing the display device may further include the steps of forming an organic light-emitting layer on a first electrode exposed through the pixel defining layer and forming a second electrode on the organic light-emitting layer.

[0020] In one embodiment, the pixel defining layer may expose the lower electrode and the tilted electrode of the first electrode and overlap with at least a portion of the upper electrode.

[0021] In one embodiment, the second flat portion may include: a masking portion that overlaps with the pixel defining layer; and an exposed portion that does not overlap with the pixel defining layer.

[0022] In one embodiment, the exposed portion may have a distance of 1 μm to 2 μm.

[0023] In one embodiment, the pixel defining layer may be formed to be in direct contact with the top surface of the via layer.

[0024] In one embodiment, the alignment mark may be composed of the same material as the via layer.

[0025] In one embodiment, the alignment mark may be formed by a recessed pattern on the upper portion of the via layer.

[0026] In one embodiment, the alignment mark may comprise ink that fills the grooved pattern, the ink having a different color than the upper surface of the through-hole layer.

[0027] In one embodiment, the step may further include forming a thin film encapsulation layer on the second electrode.

[0028] Specific details of other embodiments are included in the detailed description and accompanying drawings.

[0029] According to embodiments of this invention, misalignment of the pixel boundary layer can be minimized. Furthermore, even in the event of pixel boundary layer misalignment, the tilted electrode of the first electrode can be prevented from overlapping with the pixel boundary layer.

[0030] The effects of this utility model are not limited to the examples above, and more diverse effects are included in this specification. Attached Figure Description

[0031] Figure 1 This is a perspective view of a display device according to one embodiment.

[0032] Figure 2 This is a plan view of a display device according to one embodiment.

[0033] Figure 3 It is shown Figure 2 A cross-sectional view of an example of I-I'.

[0034] Figure 4 This is a cross-sectional view illustrating an example of the construction of any sub-pixel included in a display device according to an embodiment of the present invention.

[0035] Figure 5a and Figure 5b It is shown Figure 4 A cross-sectional view of an example of an enlarged view of region A.

[0036] Figure 6 and Figure 7This is a cross-sectional view of the light-emitting element and the pixel boundary layer used to illustrate the alignment of the pixel boundary layer.

[0037] Figure 8 This is a schematic cross-sectional view of the construction of the alignment mark AK region.

[0038] Figure 9 This is for illustrating an embodiment of the present invention. Figure 8 The plan view of the alignment markers.

[0039] Figure 10 It is used for explanation Figure 9 A diagram illustrating the alignment markers.

[0040] Figure 11 This is a plan view illustrating the alignment marks according to another embodiment of the present invention.

[0041] Figure 12a and Figure 12b It is used for explanation Figure 11 A diagram illustrating the alignment markers.

[0042] Figures 13 to 17 It is a process flow diagram used to manufacture display devices.

[0043] (Explanation of reference numerals in the attached diagram)

[0044] 171: First electrode

[0045] 171-1: Lower electrode

[0046] 171-2: Tilted Electrode

[0047] 171-3: Upper Electrode

[0048] 172: Organic light-emitting layer

[0049] 173: Second electrode

[0050] 180: Through-hole layer

[0051] PDL: Pixel Delimiter Layer Detailed Implementation

[0052] If referring to the attached appendix Figure 1 The advantages and features of this invention, as well as the methods of implementing them, will become clear from the detailed embodiments described below. However, this invention is not limited to the embodiments disclosed below and will be implemented in various forms that differ from each other. These embodiments are provided only to make the disclosure of this invention complete and to fully inform those skilled in the art of the invention of the scope of the invention. This invention is defined only by the scope of the claims.

[0053] When referring to elements or layers as "on" or "above" another element or layer, it includes not only cases where the element or layer is directly on top of the other element or layer, but also cases where there is another layer or element in between. Conversely, when referring to an element as "directly on" or "directly on," it indicates cases where there is no other element or layer in between.

[0054] Spatially relative terms such as "below," "below," "lower," "above," "on," "on," and "upper" can be used, as illustrated in the accompanying drawings, to readily describe the relationship between one element or component and another. Spatially relative terms should be understood to include not only the directions shown in the drawings but also terms indicating the different orientations of elements during use or operation. For example, when elements shown in the drawings are flipped, an element described as "below" another element can be placed "above" yet another element. Similarly, an element described as being "to the left" of another element relative to the drawing can be located "to the right" of another element at a given time point. Therefore, the illustrative term "below" can encompass both the below and above directions. Elements can also be oriented in another direction; in this case, spatially relative terms can be interpreted according to the orientation.

[0055] Although terms like "first," "second," etc., are used to describe various constituent elements, these constituent elements are not inherently limited by these terms. These terms are used merely to distinguish one constituent element from others. Therefore, the "first constituent element" mentioned below can also be a "second constituent element" within the technical concept of this utility model. Unless there is a clear difference in definition within the context, singular expressions also include plural expressions. Furthermore, terms such as "comprising" or "having" are used to specify the presence of features, numbers, steps, operations, constituent elements, components, or combinations thereof described in the specification, and do not presuppose the presence or additional possibilities of one or more other features, numbers, steps, operations, constituent elements, components, or combinations thereof.

[0056] Throughout the instruction manual, the same reference numerals are used for the same or similar parts.

[0057] The embodiments of the present invention will now be described with reference to the accompanying drawings.

[0058] Figure 1 This is a perspective view of a display device according to one embodiment. Figure 2 This is a plan view of a display device according to one embodiment.

[0059] Reference Figure 1 and Figure 2 The display device 10, as a device for displaying dynamic or static images, is used not only in portable electronic devices such as mobile phones, smartphones, tablet PCs, smartwatches, watch phones, mobile communication terminals, electronic manuals, e-books, PMPs (portable multimedia players), navigators, and UMPCs (Ultra Mobile PCs), but also in the display screens of various products such as televisions, laptops, monitors, billboards, and Internet of Things (IoT) devices. The display device 10 can be any of the following: organic light-emitting display device, liquid crystal display device, plasma display device, electric field emitting display device, electrophoretic display device, electrowetting display device, quantum dot light-emitting display device, and micro LED display device. The following description focuses on the display device 10 being an organic light-emitting display device, but the present invention is not limited thereto.

[0060] According to one embodiment, the display device 10 includes a display panel 100, a display driving circuit 200, and a circuit board 300.

[0061] The display panel 100 may include a main area MA and a protruding area PA that protrudes from one side of the main area MA.

[0062] The main region MA can be formed as a rectangular plane having a short side in a first direction (X-axis direction) and a long side in a second direction (Y-axis direction) intersecting the first direction (X-axis direction). The corner where the short side in the first direction (X-axis direction) and the long side in the second direction (Y-axis direction) intersect can be rounded or formed by a right angle to have a predetermined curvature. The planar form of the display device 10 is not limited to a quadrilateral and can be formed by other polygons, circles, or ellipses. The main region MA can be formed flat, but is not limited to this, and may include curved surfaces formed at the left and right ends. In this case, the curved surfaces can have a certain curvature or a varying curvature.

[0063] The main region MA can include the display region DA that forms pixels to display the image and the surrounding area of ​​the display region DA, i.e., the non-display region NDA.

[0064] The display area DA is not only composed of pixels, but can also be configured to connect scan lines, data lines, and power lines to those pixels. When the main area MA includes a curved section, the display area DA can be configured on the curved section. In this case, the image of the display panel 100 can also be seen on the curved section.

[0065] The non-display area NDA can be defined as the area extending from the outer edge of the display area DA to the edge of the display panel 100. A scan drive unit for applying scan signals to scan lines and a link line connecting the data line and the display drive circuit 200 can be configured in the non-display area NDA.

[0066] In the non-display area NDA of the display panel 100, alignment marks AK, required during the pixel delimitation layer process, can be configured. Figure 2 The diagram shows four alignment markers AK, but it is not limited to these. The shape, size, or number of alignment markers AK can be modified.

[0067] The protruding region PA can protrude from one side of the main region MA. For example, the protruding region PA can be like... Figure 2 It protrudes from the lower side of the main region MA. The length of the protruding region PA in the first direction (X-axis direction) can be smaller than the length of the main region MA in the first direction (X-axis direction).

[0068] The protruding region PA may include a curved region BA and a pad region PDA. In this case, the pad region PDA may be configured on one side of the curved region BA, and the main region MA may be configured on the other side of the curved region BA. For example, the pad region PDA may be configured below the curved region BA, and the main region MA may be configured above the curved region BA.

[0069] The display panel 100 can be flexibly configured to bend, fold, or roll. Therefore, the display panel 100 can be bent from the bending region BA in the thickness direction (Z-axis direction). In this case, before the display panel 100 is bent, the pad area PDA of the display panel 100 faces upwards, but after the display panel 100 is bent, the pad area PDA of the display panel 100 faces downwards. Thus, the pad area PDA is positioned below the main region MA, and therefore can overlap with the main region MA.

[0070] In the pad area of ​​the display panel 100, the PDA can be configured with the display driver circuit 200 and the pads electrically connected to the circuit board 300.

[0071] The display driver circuit 200 outputs signals and voltages for driving the display panel 100. For example, the display driver circuit 200 may supply data voltage to the data lines. Alternatively, the display driver circuit 200 may supply power voltage to the power lines and scan control signals to the scan drive unit. The display driver circuit 200 is formed by an integrated circuit (IC) and may be mounted on the display panel 100 in the pad area of ​​the PDA via COG (chip on glass), COP (chip on plastic), or ultrasonic bonding, but is not limited thereto. For example, the display driver circuit 200 may be mounted on a circuit board 300.

[0072] The pads may include display pads electrically connected to the display driver circuit 200 and touch pads electrically connected to the contact wires.

[0073] Circuit board 300 can be attached to pads using an anisotropic conductive film. Thus, the leads of circuit board 300 can be electrically connected to the pads. Circuit board 300 can be a flexible printed circuit board, a printed circuit board, or a flexible film such as a chip-on-film.

[0074] The touch driving circuit can be connected to the touch electrodes of the touch sensor layer of the display panel 100. The touch driving circuit applies a driving signal to the touch electrodes of the touch sensor layer and measures the capacitance value of the touch electrodes. The driving signal can be a signal with multiple driving pulses. The touch driving circuit can not only determine whether a touch input has occurred based on the capacitance value, but also calculate the touch coordinates of the input touch.

[0075] The touch driving circuit can be configured on the circuit board 300. The touch driving circuit can be formed by an integrated circuit (IC) and mounted on the circuit board 300.

[0076] Figure 3 It is shown Figure 2 A cross-sectional view of an example of I-I'.

[0077] Reference Figure 3 The display panel 100 may include a substrate SUB, a thin film transistor layer (TFTL) disposed on the substrate SUB, a light-emitting element layer (EML) and a thin film encapsulation layer (TFEL).

[0078] The substrate SUB can be composed of insulating materials such as glass, quartz, and polymer resins. Examples of polymer materials include polyethersulfone (PES), polyacrylate (PA), polyarylate (PAR), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyallylate, polyimide (PI), polycarbonate (PC), cellulose triacetate (CAT), cellulose acetate propionate (CAP), or combinations thereof. Alternatively, the substrate SUB can also include metallic materials.

[0079] The substrate SUB can be a rigid substrate or a flexible substrate that can be bent, folded, or rolled. When the substrate SUB is a flexible substrate, it can be formed of polyamide (PI), but is not limited to this.

[0080] A thin-film transistor layer (TFTL) can be disposed on a substrate (SUB). The TFTL can form not only the thin-film transistors for each pixel, but also scan lines, data lines, power lines, scan control lines, and routing lines connecting pads and data lines. Each thin-film transistor may include a gate electrode, a semiconductor layer, a source electrode, and a drain electrode.

[0081] The thin-film transistor layer (TFTL) can be configured in the display area (DA) and the non-display area (NDA). Specifically, the thin-film transistors, scan lines, data lines, and power lines of each pixel of the TFTL can be configured in the display area (DA). The scan control lines and link lines of the TFTL can be configured in the non-display area (NDA).

[0082] A light-emitting element layer (EML) can be configured on a thin-film transistor layer (TFTL). The EML may include pixels comprising a first electrode, a light-emitting layer, and a second electrode, and a pixel-defining layer defining the pixels. The light-emitting layer may be an organic light-emitting layer comprising organic materials. In this case, the light-emitting layer may include a hole transporting layer, an organic light-emitting layer, and an electron transporting layer. When a predetermined voltage is applied to the first electrode and a cathode voltage is applied to the second electrode via the thin-film transistors of the TFTL, holes and electrons move through the hole transporting layer and electron transporting layer, respectively, to the organic light-emitting layer and couple with each other within the organic light-emitting layer to emit light. The pixels of the EML can be configured in the display area (DA).

[0083] A thin-film encapsulation layer (TFEL) can be disposed on the light-emitting element layer (EML). The TFEL serves to prevent oxygen or moisture from penetrating into the EML. Therefore, the TFEL may include at least one inorganic film. The inorganic film may be a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer, but is not limited to these. Additionally, the TFEL protects the EML from foreign matter such as dust. Therefore, the TFEL may include at least one organic film. The organic film may be acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin, but is not limited to these.

[0084] The thin-film encapsulation layer TFEL can be entirely configured in the display area DA and the non-display area NDA. Specifically, the thin-film encapsulation layer TFEL can be configured as an emissive element layer EML covering the display area DA and the non-display area NDA, and a thin-film transistor layer TFTL covering the non-display area NDA.

[0085] A cover window can be further configured on the thin-film encapsulation layer TFEL, and a touch sensing layer can be further configured between the thin-film encapsulation layer TFEL and the cover window. In this case, the cover window is attached to the underlying layer by a transparent adhesive component such as an OCA (optically clear adhesive) film.

[0086] Figure 4 This is a cross-sectional view illustrating an example of the construction of any sub-pixel included in a display device according to an embodiment of the present invention. Figure 5a and Figure 5b It is shown Figure 4 A cross-sectional view of an example of an enlarged view of region A.

[0087] A pixel can include multiple light-emitting elements (LELs) and can be defined as the smallest unit of light emission that can display white light by combining the light emitted by multiple LELs.

[0088] A pixel can include multiple sub-pixels. Multiple sub-pixels can each display light of a different wavelength.

[0089] Reference Figure 4 and Figure 5a A thin-film transistor layer (TFTL) is formed on the substrate SUB of the display device 10. The TFTL includes thin-film transistors (TFTs), a gate insulating layer 130, an interlayer insulating layer 140, a first protective layer 150, a planarization layer 160, and a via layer 180.

[0090] A buffer layer BF1 may also be formed on one side of the substrate SUB. The buffer layer BF1 is formed on one side of the substrate SUB to protect the organic light-emitting layer 172 of the thin-film transistor (TFT) and the light-emitting element layer (EML) from moisture that can penetrate through the easily permeable substrate SUB. The buffer layer BF1 may be composed of multiple inorganic films stacked alternately. For example, the buffer layer BF1 may be formed by stacking one or more inorganic films, such as silicon nitride, silicon oxynitride, silicon oxide, titanium oxide, and aluminum oxide, in an alternating manner. The buffer layer BF1 may be omitted.

[0091] Thin-film transistors (TFTs) can be formed on the buffer layer BF1. A TFT includes an active layer ACT, a gate electrode G, a source electrode S, and a drain electrode D. Figure 4 The example shown is a case where a thin-film transistor (TFT) is formed with the gate electrode G located above the active layer ACT, which is a top gate configuration. However, it should be noted that this is not the only possibility. That is, a thin-film transistor (TFT) can be formed with the gate electrode G located below the active layer ACT, which is a bottom gate configuration, or with the gate electrodes G located both above and below the active layer ACT, which is a double gate configuration.

[0092] An active layer ACT can be formed on the buffer layer BF1. The active layer ACT can include polycrystalline silicon, monocrystalline silicon, low-temperature polycrystalline silicon, amorphous silicon, or oxide semiconductors. For example, oxide semiconductors can include binary compounds (ABs) containing indium, zinc, gallium, tin, titanium, aluminum, hafnium (Hf), zirconium (Zr), magnesium (Mg), etc. x ), ternary compounds (AB) x C y ), quaternary compounds (AB)x C y D z For example, the active layer ACT may include ITZO (including oxides of indium, tin, and titanium) or IGZO (including oxides of indium, gallium, and tin). A light-shielding layer for blocking external light incident on the active layer ACT may be formed between the buffer layer BF1 and the active layer ACT.

[0093] A gate insulating layer 130 may be formed on the active layer ACT. The gate insulating layer 130 may be formed of an inorganic film, such as a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

[0094] A gate electrode G and a gate line can be formed on the gate insulating layer 130. The gate electrode G and the gate line can be formed from a single layer or multiple layers of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or alloys thereof.

[0095] An interlayer insulating layer 140 may be formed on the gate electrode G and the gate line. The interlayer insulating layer 140 may be formed of an inorganic film, for example, a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

[0096] A source electrode S and a drain electrode D can be formed on the interlayer insulating layer 140. Each of the source electrode S and the drain electrode D can be connected to the active layer ACT through a contact hole penetrating the gate insulating layer 130 and the interlayer insulating layer 140. The source electrode S and the drain electrode D can be formed from a single layer or multiple layers of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) or their alloys.

[0097] A first protective layer 150 for insulating thin-film transistors (TFTs) can be formed on the source electrode S and the drain electrode D. The first protective layer 150 can be formed of an inorganic film, such as a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

[0098] A planarization layer 160 for flattening the steps caused by the thin-film transistor TFT can be formed on the first protective layer 150.

[0099] A first contact hole CH1 can be formed in the planarization layer 160. The first contact hole CH1 can be formed to expose the drain electrode D of the thin-film transistor TFT. A second contact hole CH2 can be formed in the via layer 180. The second contact hole CH2 can be formed to expose the first contact hole CH1. Therefore, the first electrode 171 can be connected to the drain electrode D of the thin-film transistor TFT through the second contact hole CH2 and the first contact hole CH1.

[0100] The planarization layer 160 can be formed from organic films such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, and polyimide resin.

[0101] A second protective layer 165 may be formed on the planarization layer 160. The second protective layer 165 may be formed of an inorganic film, such as a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer. The second protective layer 165 may be omitted. A via layer 180 may be disposed on the second protective layer 165. The via layer 180 may be formed of an organic material, such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin.

[0102] The via layer 180 may include a sloped surface SSL1 defining a recess OP1. Additionally, the sloped surface SSL1 of the via layer 180 may have a gentle slope relative to the top surface of the substrate SUB. The first included angle θ1 formed by the sloped surface SSL1 of the via layer 180 and the extension line below the recess OP1 may be an acute angle. For example, the first included angle θ1 may be approximately 10 degrees to 40 degrees. A first electrode 171 may be disposed on the sloped surface SSL1 of the via layer 180. Figure 5a As shown, the groove OP1, when disposed on the bottom layer of the via layer 180, such as the second protective layer 165, or when the second protective layer 165 is omitted, can be a through-hole exposing the planarization layer 160. However, it is not limited to this. The groove OP1 is as follows: Figure 5b That could be a groove with a shape that is recessed downwards from the top of the through-hole layer 180.

[0103] In addition, Figure 5a and Figure 5b The via layer 180 is illustrated as a single layer, but is not limited thereto, and can be formed by stacking two or more layers. For example, the via layer 180 includes a first via layer and a second via layer, wherein the first via layer can be formed on the second via layer.

[0104] A light-emitting element layer (EML) can be disposed on the thin-film transistor layer (TFTL). The EML may include light-emitting elements (LEL) and pixel delimiting layers (PDL).

[0105] Each of the light-emitting elements (LELs) may include a first electrode 171, an organic light-emitting layer 172, and a second electrode 173.

[0106] The first electrode 171 can be disposed in the groove OP1 of the via layer 180 and extend along the inclined surface SSL1 of the via layer 180.

[0107] The first electrode 171 may include an inclined electrode 171-2 disposed along the inclined surface SSL1 of the via layer 180. In addition, the first electrode 171 may also include a lower electrode 171-1 extending from the lower end of the inclined electrode 171-2 and disposed in the groove OP1, and an upper electrode 171-3 extending from the upper end of the inclined electrode 171-2 and disposed on the via layer 180.

[0108] At least a portion of the upper electrode 171-3 may be covered by the pixel definition layer (PDL). The upper electrode 171-3 may include a masking portion 171-31 covered by the PDL and an exposed portion 171-32 not covered by the PDL. The masking portion 171-31 overlaps with the PDL, and the exposed portion 171-32 does not overlap with the PDL.

[0109] The exposed portions 171-32 can be considered as edge regions considering the distribution of the pixel delimiting layer (PDL). The exposed portions 171-32 can have a length of approximately 1 μm to 2 μm.

[0110] Ensure the edge area, so that even if the pixel boundary layer (PDL) is not aligned, the PDL can still not cover the tilted electrode 171-2.

[0111] As one embodiment, the first electrode 171 may be an anode electrode. When the first electrode 171 is an anode electrode, it may include a reflective material. As one embodiment, the reflective material may include one or more reflective films selected from the group consisting of silver (Ag), magnesium (Mg), chromium (Cr), gold (Au), platinum (Pt), nickel (Ni), copper (Cu), tungsten (W), and aluminum (Al), and transparent or translucent electrodes formed on the reflective films.

[0112] Here, the transparent or semi-transparent electrode may be composed of one or more of the group consisting of ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), ZnO (Zinc Oxide), In2O3 (Indium Oxide), IGO (Indium Gallium Oxide) and AZO (Aluminum Zinc Oxide).

[0113] The pixel defining layer (PDL) can be formed to demarcate the first electrode 171. The pixel defining layer (PDL) can be formed to cover the edge of the first electrode 171. The pixel defining layer (PDL) can be formed from an organic film such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin.

[0114] The pixel delimiting layer (PDL) may include an inclined surface (SSL2) that defines the second opening (OP2).

[0115] The width of the second opening OP2 defined by the pixel defining layer PDL can be wider than the width of the groove OP1 defined by the via layer 180. Here, the width of the groove OP1 is the shortest distance between the inclined surfaces SSL1 of the via layer 180, and the width of the second opening OP2 can be defined by the shortest distance between the inclined surfaces SSL2 of the pixel defining layer PDL.

[0116] The sloping surface SSL2 of the pixel boundary layer PDL can have a gentle slope relative to the via layer 180.

[0117] Each sub-pixel shows a region in which a first electrode 171, an organic light-emitting layer 172, and a second electrode 173 are sequentially stacked, and holes from the first electrode 171 and electrons from the second electrode 173 couple with each other in the organic light-emitting layer 172 to emit light. Each sub-pixel may include a light-emitting element (LEL).

[0118] An organic light-emitting layer 172 is formed on the first electrode 171.

[0119] The organic light-emitting layer 172 may include organic materials to emit a predetermined color. For example, the organic light-emitting layer 172 may include a hole transporting layer, an organic material layer, and an electron transporting layer. For example, the organic light-emitting layer 172 of the first sub-pixel may emit light of a first color, the organic light-emitting layer 172 of the second sub-pixel may emit light of a second color, and the organic light-emitting layer 172 of the third sub-pixel may emit light of a third color. The first color may be red, the second color may be green, and the third color may be blue, but this is not a limitation.

[0120] Alternatively, the organic light-emitting layer 172 of each sub-pixel can emit white light. For example, the first sub-pixel may overlap with a color filter layer of a first color, the second sub-pixel may overlap with a color filter layer of a second color, and the third sub-pixel may overlap with a color filter layer of a third color.

[0121] The organic light-emitting layer 172 can be overlapped with the lower electrode 171-1, the tilted electrode 171-2, and the upper electrode 171-3 of the first electrode 171. The organic light-emitting layer 172 may include a first flat portion 172-1, a tilted portion 172-2, and a second flat portion 172-3. The first flat portion 172-1 is disposed on the lower electrode 171-1 of the first electrode 171, the tilted portion 172-2 is disposed on the tilted electrode 171-2 of the first electrode 171, and the second flat portion 172-3 is disposed on the upper electrode 171-3 of the first electrode 171. Therefore, the first flat portion 172-1 may overlap with the groove OP1 of the via layer 180, the tilted portion 172-2 may overlap with the tilted surface SSL1 of the via layer 180, and the second flat portion 172-3 may overlap with the top of the via layer 180. In one embodiment, the first flat portion 172-1 and the second flat portion 172-3 are referred to as flat, but they can be formed to have curvature in the manufacturing process. In this case, the first flat portion 172-1 and the second flat portion 172-3 can also be formed to be relatively flat compared to the inclined portion 172-2.

[0122] Of the light generated in the organic light-emitting layer 172, light traveling towards the side of the first electrode 171 can be reflected by the tilted electrode 171-2 of the first electrode 171 and travel towards the top of the organic light-emitting layer 172, instead of emitting light towards the top of the organic light-emitting layer 172. That is, the tilted electrode 171-2 of the first electrode 171 can guide the side light upwards so that the light is not lost from the side of the organic light-emitting layer 172, thus improving light extraction efficiency and providing high luminous efficiency. Furthermore, the tilted electrode 171-2 of the second electrode 171 affects the improvement of the white-out phenomenon (WAD) that changes the hue to blue through the white-out phenomenon from the side. Thus, the tilted electrode 171-2 of the first electrode 171 has a direct impact on reflectivity and WAD improvement.

[0123] In one embodiment, the organic light-emitting layer 172 can emit one of red, green, and blue light. The wavelength of the red light can be approximately 620 nm to 750 nm, and the wavelength of the green light can be approximately 495 nm to 570 nm. Additionally, the wavelength of the blue light can be approximately 450 nm to 495 nm.

[0124] In another embodiment, the organic light-emitting layer 172 can emit white light. In the case where the organic light-emitting layer 172 emits white light, it can, as one embodiment, have a stacked configuration of a red light-emitting layer, a green light-emitting layer, and a blue light-emitting layer. Additionally, it may include separate color filters for displaying red, green, and blue.

[0125] Although not shown in the figure, the organic light-emitting layer 172 may also be a multilayer structure including a hole transporting layer, an organic light emitting layer, and an electron transporting layer.

[0126] The second electrode 173 is formed on the organic light-emitting layer 172 and the pixel-defining layer PDL. The second electrode 173 can be formed to cover both the organic light-emitting layer 172 and the pixel-defining layer PDL. The second electrode 173 can be formed in a common layer of all light-emitting elements (LELs). As an embodiment, the second electrode 173 can be a cathode electrode. As an embodiment, the second electrode 173 can include materials selected from the group consisting of Li, Ca, LiF, Al, Ag, and Mg, or materials having a multilayer structure such as LiF / Ca or LiF / Al. Alternatively, the second electrode 173 can be composed of a metal thin film with a low work function. As an embodiment, the second electrode 173 can be a transparent or semi-transparent electrode selected from the group consisting of ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), ZnO (Zinc Oxide), In2O3 (Indium Oxide), IGO (Indium Gallium Oxide), and AZO (Aluminum Zinc Oxide).

[0127] In the upper light-emitting structure, the second electrode 173 can be formed of a transparent conductive oxide (TCO) such as ITO (Indium Tin Oxide) and IZO (Indium Zinc Oxide), or a semi-transmissive conductive material such as magnesium (Mg), silver (Ag), or an alloy of magnesium (Mg) and silver (Ag). When the second electrode 173 is formed of a semi-transmissive metallic material, the light extraction efficiency can be improved through a microcavity. A capping layer can be formed on the second electrode 173.

[0128] An encapsulation layer TFEL can be disposed on the second electrode 173. The encapsulation layer TFEL, to prevent oxygen or moisture from penetrating into the organic light-emitting layer 172 and the second electrode 173, may include at least one inorganic film. Additionally, to protect the light-emitting element layer EML from foreign matter such as dust, the encapsulation layer TFEL may include at least one organic film. For example, the encapsulation layer TFEL may include a first inorganic film TFEL1 disposed on the second electrode 173, an organic film TFEL2 disposed on the first inorganic film TFEL1, and a second inorganic film TFEL3 disposed on the organic film TFEL2. The first inorganic film TFEL1 and the second inorganic film TFEL3 may be formed from a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer, but are not limited thereto. The organic film may be formed from acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, etc., but is not limited thereto.

[0129] A second buffer layer can be formed on the thin-film encapsulation layer TFEL. The second buffer layer can be composed of multiple inorganic films stacked alternately. For example, the second buffer layer can be formed by stacking more than one of the following inorganic films: silicon nitride layer, silicon oxynitride layer, silicon oxide layer, titanium oxide layer, and aluminum oxide layer. The second buffer layer can be omitted.

[0130] Each pixel region DA of the display panel 100 may include a light-emitting region and a non-light-emitting region. Specifically, the light-emitting region may be an area in each pixel region DA where an organic light-emitting layer 172 for emitting actual light is disposed, and the non-light-emitting region may be a light-shielding region adjacent to the light-emitting region and disposed of with a light-shielding material such as a black matrix. In one embodiment, the light-emitting region may be wider than the second opening OP2 defined by the pixel defining layer PDL.

[0131] Multiple microlenses can be configured on the thin-film encapsulation layer TFEL. Each of the multiple microlenses can be configured to overlap with the light-emitting area of ​​the corresponding pixel area DA.

[0132] Figure 6 and Figure 7 This is a cross-sectional view of the light-emitting element and the pixel boundary layer used to illustrate the alignment of the pixel boundary layer.

[0133] It can be, as referenced. Figure 6 The pixel delimiting layer (PDL) is pushed to one side in the first direction, or as referenced. Figure 7 The pixel delimiting layer (PDL) is pushed to the other side of the first direction.

[0134] In reference Figure 6 and Figure 7 Even when the pixel boundary layer (PDL) is misaligned, at least a portion of the exposed portion 171-32 can be covered. Thus, even with the PDL misalignment, the tilted electrode 171-2 can still be exposed through the PDL. Therefore, the PDL overlaps with the tilted electrode 171-2, preventing potential screen smudges and other contaminants.

[0135] The following is a detailed explanation of the alignment mark.

[0136] Figure 8 This is a schematic cross-sectional view of the construction of the alignment mark AK region.

[0137] exist Figure 8 The alignment mark AK of the display device 10 shown according to an embodiment of the present invention is aligned with the alignment mark AK of the display device 10 according to an embodiment of the present invention. Figure 2 The structure corresponding to the alignment mark AK of the display device 10 shown is illustrated. The alignment mark AK may be composed of the same organic material as the through-hole layer 180.

[0138] Reference Figure 8 In the non-display area NDA of the display device 10, a substrate SUB, a gate insulating layer 130, an interlayer insulating layer 140, a first protective layer 150, a planarization layer 160, and a via layer 180 can be sequentially stacked. The substrate SUB, gate insulating layer 130, interlayer insulating layer 140, first protective layer 150, planarization layer 160, and second protective layer 165 have been referenced. Figure 4 and Figure 5a Explanations have been provided, so repeated explanations will be omitted.

[0139] Alignment marks formed of metal may also be included on the buffer layer BF1, the interlayer insulation layer 140, and the planarization layer 160.

[0140] The via layer 180 may include alignment marks AK formed by a recessed pattern on the upper portion of the via layer 180.

[0141] Alignment marks AK can be formed by patterning the via layer 180. Alignment marks AK comprise ink filling a recessed pattern; the ink can have a different color than the upper part of the via layer 180. The ink can be omitted.

[0142] The pixel delimiting layer (PDL) can be formed with the alignment mark AK of the via layer 180 as a reference.

[0143] Figure 9 This is for illustrating an embodiment of the present invention. Figure 8 The alignment mark plan view, Figure 10 It is used for explanation Figure 9 A diagram illustrating the alignment markers. Figure 11 This is a plan view illustrating the alignment marks according to another embodiment of the present invention. Figure 12a and Figure 12b It is used for explanation Figure 11 A diagram illustrating the alignment markers.

[0144] like Figure 9 As shown, the pattern for aligning the AK mark can be a cross (+) shape. For example... Figure 10 As shown, the cross-shaped alignment mark AK pattern can form a concave texture.

[0145] In addition to Figure 9 Besides the illustrated alignment mark pattern, the alignment mark AK pattern can also have various planar shapes. For example, the alignment mark AK can have planar shapes such as straight lines, squares, triangles, hexagons, circles, etc.

[0146] like Figure 10 , Figure 11 , Figure 12a and Figure 12b As shown, the alignment mark AK pattern can be composed of multiple sub-patterns AK-S, and the shapes of each sub-pattern AK-S can be the same or different. The alignment mark AK is shown as including 4... The AK-S features a letter-shaped sub-pattern, but is not limited to this.

[0147] Alignment marker AK can be as follows Figure 12a That kind of concave pattern can also be formed as... Figure 12b That is formed by relief patterns.

[0148] The manufacturing method of the display device described above shall be referred to Figures 13 to 17 Please provide an explanation.

[0149] Figures 13 to 17 This is a process flow diagram for manufacturing a display device. The following process sequence is illustrative and does not limit the scope of this invention. (See reference...) Figure 4 and Figure 8 Please provide an explanation.

[0150] It is possible, in Figure 14 The displayed area corresponds to the reference. Figure 4 , Figure 5a and Figure 5b The display area is described, and the non-display area corresponds to the reference area. Figure 8 The non-display area is described. (See reference.) Figure 13 A substrate SUB for forming a thin-film transistor (TFT) can be prepared. A first protective layer 150 and a planarization layer 160 may also be disposed on the substrate SUB for forming the TFT.

[0151] An organic layer is formed on the planarization layer 160, and a groove OP1 and an alignment mark AK are patterned to form a via layer 180. To form the via layer 180, an organic layer is first laminated onto the planarization layer 160 using various methods. The groove OP1 and the alignment mark AK are then patterned using a photolithography process with a first mask and an etching process to form the via layer 180. The groove OP1 can be patterned to protrude downwards towards the underside of the via layer 180. Thus, the alignment mark AK can be formed by the groove OP1 formed on the via layer 180. The buffer material may include organic materials such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, and polyimide resin.

[0152] Next, refer to Figure 14 A first electrode 171 can be formed on the via layer 180. For example, a conductive material layer can be deposited on the via layer 180. The conductive material layer may, for example, comprise one or more of the group consisting of ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), ZnO (Zinc Oxide), In2O3 (Indium Oxide), IGO (Indium Gallium Oxide), and AZO (Aluminum Zinc Oxide). The conductive material layer can be patterned into the first electrode 171 using a photolithography process and an etching process using a second mask.

[0153] Next, refer to Figure 15 A pixel defining layer (PDL) is formed on the via layer 180 and the first electrode 171 using alignment marks AK. The PDL can be formed by spin coating or other methods using an organic insulating material selected from one or more of the group consisting of acrylic resin, epoxy resin, phenolic resin, polyamide resin, and polyimide resin. The PDL can be patterned using photolithography and etching processes with a third mask to expose at least a portion of the upper surface of the first electrode 171. The formation location of the PDL can be confirmed by identifying the alignment marks AK in the non-display area NDA during its formation.

[0154] Reference Figure 16An organic light-emitting layer 172 can be formed on the first electrode 171. Alignment marks AK can be used to align the organic light-emitting layer 172. An organic material evaporation apparatus identifies the alignment marks to obtain the position of the pixel electrode and deposits organic material on the pixel electrode to form the organic light-emitting layer 172. In addition to an organic light-emitting layer (EML), the organic light-emitting layer 172 can also be formed by stacking single or composite layers of any one or more functional layers such as a hole transport layer (HTL), a hole injection layer (HIL), an electron transport layer (ETL), and an electron injection layer (EIL). The organic light-emitting layer 172 can be prepared from low-molecular-weight or high-molecular-weight organic materials.

[0155] Next, refer to Figure 17 A second electrode 173 is formed on the organic light-emitting layer 172, and an encapsulation layer TFEL can then be formed on the second electrode 173.

[0156] The second electrode 173 can be formed on the display area DA of the display panel 100. The second electrode 173 can also be formed in front of the display area DA.

[0157] The encapsulation layer TFEL can be attached to the display panel 100. Using sealing components, the encapsulation layer TFEL can be bonded to the substrate.

[0158] The above description focuses on embodiments of the present invention, but these are merely illustrative and do not limit the scope of the invention. Those skilled in the art will recognize that various modifications and applications not illustrated above can be made without departing from the essential characteristics of the embodiments of the present invention. For example, the constituent elements specifically shown in the embodiments of the present invention can be modified and implemented. Furthermore, the distinctions regarding such modifications and applications are to be interpreted as including within the scope of the present invention as defined in the appended claims.

Claims

1. A display device, characterized in that, include: The substrate includes a display area and a non-display area; Thin-film transistors are disposed on the substrate; A planarization layer is disposed on the thin-film transistor; A via layer is disposed in the planarization layer and has a groove in the display area and an alignment mark in the non-display area; A sub-pixel includes a first electrode, an organic light-emitting layer, and a second electrode configured corresponding to the groove. as well as A pixel defining layer defines the sub-pixel on the via layer. The first electrode is electrically connected to the thin-film transistor and includes a tilted electrode disposed along the tilted surface of the via layer.

2. The display device according to claim 1, characterized in that, The first electrode further includes: a lower electrode extending from the lower end of the inclined electrode and disposed within the groove; and an upper electrode extending from the upper end of the inclined electrode and disposed on the via layer.

3. The display device according to claim 2, characterized in that, The upper electrode includes: a masking portion that overlaps with the pixel defining layer; and an exposed portion that does not overlap with the pixel defining layer.

4. The display device according to claim 3, characterized in that, The exposed portion has a length of 1 μm to 2 μm.

5. The display device according to claim 2, characterized in that, The organic light-emitting layer is configured to overlap with the lower electrode, the tilted electrode, and the upper electrode.

6. The display device according to claim 1, characterized in that, The pixel defining layer is in direct contact with the top of the via layer.

7. The display device according to claim 1, characterized in that, The alignment marks are composed of the same material as the through-hole layer.

8. The display device according to claim 1, characterized in that, The alignment mark is formed by a recessed pattern on the upper portion of the through-hole layer.

9. The display device according to claim 8, characterized in that, The alignment marks include ink that fills the grooved pattern. The ink has a different color than the surface of the through-hole layer.

10. The display device according to claim 1, characterized in that, The display device further includes: A thin-film encapsulation layer is disposed on the sub-pixel and the pixel delimiting layer.

Images