Distributed insulation system packaging module
By using a distributed insulation system packaging module and a multi-layer PCB board and insulating substrate design, the problems of large drive circuit, high switching loss and ceramic plate cracking in the existing technology are solved, and efficient chip packaging and low-cost heat dissipation connection are achieved.
Patent Information
- Application Number
- CN202520272156.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-02-20
- Publication Date
- 2025-12-12
- Estimated Expiration
- 2035-02-20
AI Technical Summary
In existing chip packaging technologies, the drive circuit has large parasitics and high switching losses. The ceramic plate is large in size and cost and is prone to cracking. The chip area is large, and the chip and passive devices are assembled on a large board, which increases the overall area and cost.
A distributed insulation system packaging module is adopted, which combines a multi-layer PCB board with an insulating substrate, and sets up a placement area and a wiring layer to achieve distributed packaging of power chips and peripheral devices. Through the wiring layer connection of the multi-layer PCB board and the conductive connection of the insulating substrate, the use of ceramic plates is reduced, and efficient heat dissipation and electrical connection of the chip are achieved.
This reduces the overall module area and cost, decreases the use of ceramic plates, avoids stress cracking, improves chip efficiency, and reduces switching losses.
Smart Images
Figure CN223665458U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to a distributed insulation system packaging module, belonging to the technical field of chip packaging module. Background Technology
[0002] Chip packaging technology is a process that encapsulates memory chips to prevent them from contacting the outside world and thus protecting them from damage. Common forms of insulating packaging modules include... Figure 1 and Figure 2 As shown, where, Figure 1 It has a housing and top pin structure, with only power chips (IGBT / SBD / MOS, etc.) inside. The pins are soldered onto the ceramic substrate, and the pins come out from the top. A plastic shell is used as the outer shell for protection, and the inside is filled with silicone grease. Figure 2 It is an IPM structure, which generally has two boards. One is a ceramic substrate for soldering the main chip, and the other is a PCB for soldering the driver and passive components.
[0003] However, both of the above designs still have shortcomings, among which Figure 1 The structure shown integrates only power devices, while the drive and passive devices are external. The drive circuit has large parasitics and high switching losses. Furthermore, all devices are assembled on a large ceramic plate. The ceramic plate is large and prone to cracking under stress. In addition, the large ceramic substrate is expensive. Figure 2 The structure shown has long circuits between chips, resulting in large parasitic losses and high switching losses. Furthermore, the chips and passive devices are laid out in a flat structure, leading to a large product area. All heat-generating devices are assembled on a large ceramic plate, which is large in size and prone to cracking under stress. In addition, large-sized ceramic substrates are more expensive. Utility Model Content
[0004] The technical problem to be solved by this utility model is to provide a distributed insulation system packaging module that overcomes the shortcomings of the prior art. It uses various insulating substrates in conjunction with multiple wiring layers to realize the application and packaging of power chips and improve chip working efficiency.
[0005] To solve the aforementioned technical problems, this utility model adopts the following technical solution: This utility model designs a distributed insulation system packaging module for system packaging of various power chips and their respective peripheral devices. It includes at least one insulating substrate and a multilayer PCB board with at least two embedded wiring layers. Each insulating substrate has the same structure, and each includes an insulating and thermally conductive layer and two copper layers respectively disposed on the upper and lower surfaces of the insulating and thermally conductive layer. The space between any two adjacent wiring layers is defined as a placement area. The wiring layers above the placement area are defined as the upper wiring area, and adjacent wiring layers in the upper wiring area are electrically connected. The wiring layers below the placement area are defined as the lower wiring area. In the lower wiring area, adjacent wiring layers are electrically connected; each insulating substrate is disposed in the placement area, and the bottom copper layer of each insulating substrate is connected to the top wiring layer in the lower wiring area; the top wiring layer in the upper wiring area is located on the upper surface of the multilayer PCB board, and each peripheral working device is electrically connected to the wiring layer on the upper surface of the multilayer PCB board via pads; the bottom wiring layer in the lower wiring area is located on the lower surface of the multilayer PCB board; each power chip is located in the area between the top copper layer of each insulating substrate and the upper wiring area in the placement area, and each contact on the surface of each power chip is electrically connected to each other and to each peripheral working device via the upper wiring area; each power chip dissipates heat to the outside via the insulating substrate and the lower wiring area in sequence.
[0006] As a preferred technical solution of this utility model: if the power chip is a single-sided contact structure, the surface where the contacts of the single-sided contact structure power chip are located faces the upper wiring area, each contact on the single-sided contact structure power chip is electrically connected to the bottom wiring layer in the upper wiring area, and the other surface of the single-sided contact structure power chip is connected to the upper surface of the top copper layer of the insulating substrate it faces.
[0007] If the power chip has a double-sided contact structure, the upper surface of the copper layer on the top of the insulating substrate facing the double-sided contact power chip is electrically connected to the bottom trace layer in the upper trace area. Each contact on one surface of the double-sided contact power chip is electrically connected to the bottom trace layer in the upper trace area. Each contact on one surface of the double-sided contact power chip is electrically connected to each other and to each peripheral working device through the upper trace area. The other surface of the double-sided contact power chip is connected to the upper surface of the copper layer on the top of the insulating substrate facing it. At the same time, each contact on the other surface of the double-sided contact power chip is electrically connected to the upper surface of the copper layer on the top of the insulating substrate facing it. Each contact on the other surface of the double-sided contact power chip is electrically connected to each other and to each peripheral working device through the copper layer on the top of the insulating substrate and the upper trace area.
[0008] As a preferred technical solution of this utility model: for a power chip with a double-sided contact structure, the upper surface of the copper layer on the top of the insulating substrate facing the power chip with a double-sided contact structure is electrically connected to the bottom trace layer in the upper trace area through a via structure.
[0009] As a preferred technical solution of this utility model: for a power chip with a double-sided contact structure, it further includes a first copper pillar corresponding to the double-sided contact structure power chip. The height of the first copper pillar is the same as the thickness of the double-sided contact structure power chip. One end of the first copper pillar is disposed on the upper surface of the top copper layer of the insulating substrate to which the corresponding double-sided contact structure power chip is connected. The other end of the first copper pillar is electrically connected to the bottom wiring layer in the upper wiring area, thereby realizing the electrical connection between the upper surface of the top copper layer of the insulating substrate facing the double-sided contact structure power chip and the bottom wiring layer in the upper wiring area.
[0010] As a preferred technical solution of this utility model, the surface of the power chip is connected to the upper surface of the copper layer on the top of the insulating substrate it faces by a high thermal and electrical conductivity welding material.
[0011] As a preferred technical solution of this utility model: the high thermal and electrical conductivity welding material is any one of solder, silver paste, and sintered silver.
[0012] As a preferred technical solution of this utility model, it further includes at least one second copper pillar, with both ends of each second copper pillar connected to the bottom routing layer in the upper routing area and the top routing layer in the lower routing area, respectively, to realize the electrical connection between the upper routing area and the lower routing area.
[0013] As a preferred technical solution of this utility model: the insulating and thermally conductive layer is a ceramic or organic insulating and thermally conductive material.
[0014] As a preferred technical solution of this utility model, it also includes a heat sink, and the bottom wiring layer in the lower wiring area is a whole copper plate layer, which is connected to the heat sink for heat dissipation.
[0015] As a preferred technical solution of this utility model: the peripheral working device includes a drive control chip and various passive components.
[0016] The distributed insulation system encapsulation module of this utility model, compared with the prior art, has the following technical advantages:
[0017] This invention designs a distributed insulation system packaging module. Based on a multilayer PCB board with at least two built-in trace layers, a placement area is set between two adjacent trace layers, and multiple insulating substrates are set to mount various power chips. The contacts on the surface of each power chip are electrically connected to each other and to various peripheral working devices through the trace area in the upper part of the multilayer PCB board. At the same time, each power chip dissipates heat to the outside through the insulating substrate and the trace area in the lower part of the multilayer PCB board. In the design scheme, the driver / control chip and the power chip are 3D stacked, resulting in a small loop area, low parasitics, and low loss. This makes the overall module area small and the cost low. It also reduces the area of ceramic plate used, significantly reducing costs and avoiding the problem of stress cracking of large-area ceramic plates. Attached Figure Description
[0018] Figure 1 This is a schematic diagram of the existing Housing & Top Pin structure;
[0019] Figure 2 This is a schematic diagram of the existing IPM structure;
[0020] Figure 3 This is a schematic diagram of an embodiment of the distributed insulation system packaging module designed according to this utility model;
[0021] Figure 4 This is a schematic diagram of Embodiment 2 of the design of the distributed insulation system packaging module of this utility model.
[0022] Among them, 1. Power chip, 2. Peripheral working device, 3. Insulating substrate, 3-1. Insulating and thermally conductive layer, 3-2. Copper layer, 4. Tracing layer, 5. Multilayer PCB board, 6. Solder pad, 7. Via structure, 8. First copper pillar, 9. High thermal and electrical conductivity soldering material, 10. Second copper pillar. Detailed Implementation
[0023] The specific embodiments of this utility model will be further described in detail below with reference to the accompanying drawings.
[0024] This utility model designs a distributed insulation system packaging module for system packaging of various power chips 1 and peripheral working devices 2 that are connected to them, such as various drive control chips and various passive components. In practical applications, such as... Figure 3 and Figure 4As shown, the specific design includes at least one insulating substrate 3 and a multilayer PCB board 5 with at least two built-in trace layers 4; wherein, each insulating substrate 3 has the same structure, and each insulating substrate 3 includes an insulating thermally conductive layer 3-1 and two copper layers 3-2 respectively disposed on the upper and lower surfaces of the insulating thermally conductive layer 3-1. In practical applications, the insulating thermally conductive layer 3-1 may be made of ceramic or organic insulating thermally conductive materials, and the size of each insulating substrate 3 is not specifically limited, and the sizes of each substrate may be the same or different.
[0025] like Figure 3 and Figure 4 As shown, the space between any two adjacent trace layers 4 in the multilayer PCB board 5 is defined as the placement area. The trace layers 4 above the placement area are defined as the upper trace area, and adjacent trace layers 4 in the upper trace area are electrically connected. The trace layers 4 below the placement area are defined as the lower trace area, and adjacent trace layers 4 in the lower trace area are electrically connected. Each insulating substrate 3 is disposed in the placement area, and the bottom copper layer 3-2 of each insulating substrate 3 is connected to the top trace layer 4 in the lower trace area. The top trace layer 4 in the upper trace area is located on the upper surface of the multilayer PCB board 5, and each peripheral working device 2... The trace layers 4 on the upper surface of the multilayer PCB board 5 are electrically connected via pads 6. The bottom trace layer 4 in the lower trace area is located on the lower surface of the multilayer PCB board 5. Each power chip 1 is located in the area between the top copper layer 3-2 of each insulating substrate 3 and the upper trace area in the placement area. Each contact on the surface of each power chip 1 is electrically connected to each other and to each peripheral working device 2 via the upper trace area. Each power chip 1 dissipates heat to the outside via the insulating substrate 3 and the lower trace area. In practical applications, the power chip 1 here can be a chip with large heat generation such as MOS, IGBT, SiC, GaN HEMT.
[0026] Regarding the actual application of the power chip 1 in the above design, it is divided into a single-sided contact structure power chip 1 and a double-sided contact structure power chip 1. If the power chip 1 is a single-sided contact structure, the surface where the contacts of the single-sided contact structure power chip 1 are located faces the upper wiring area. Each contact on the single-sided contact structure power chip 1 is electrically connected to the bottom wiring layer 4 in the upper wiring area. The other surface of the single-sided contact structure power chip 1 is connected to the upper surface of the top copper layer 3-2 of the insulating substrate 3 it faces through a high thermal conductivity and electrical conductivity welding material 9.
[0027] If power chip 1 has a double-sided contact structure, such as Figure 3 and Figure 4 As shown, the upper surface of the copper layer 3-2 on the top of the insulating substrate 3, which faces the double-sided contact structure power chip 1, is electrically connected to the bottom trace layer 4 in the upper trace area. In practical applications, such as... Figure 3As shown, the upper surface of the double-sided contact structure power chip 1 facing the top copper layer 3-2 of the insulating substrate 3 is electrically connected to the bottom trace layer 4 in the upper trace area through a via structure 7, or as shown in the diagram. Figure 4 As shown, a first copper pillar 8 corresponding to the double-sided contact structure power chip 1 is also designed. The height of the first copper pillar 8 is the same as the thickness of the double-sided contact structure power chip 1. One end of the first copper pillar 8 is disposed on the upper surface of the top copper layer 3-2 of the insulating substrate 3 to which the double-sided contact structure power chip 1 is connected. The other end of the first copper pillar 8 is electrically connected to the bottom wiring layer 4 in the upper wiring area, thereby realizing the electrical connection between the upper surface of the top copper layer 3-2 of the insulating substrate 3 facing the double-sided contact structure power chip 1 and the bottom wiring layer 4 in the upper wiring area.
[0028] Continuing the application design of the double-sided contact structure power chip 1, each contact on one surface of the double-sided contact structure power chip 1 is electrically connected to the bottom trace layer 4 in the upper trace area. The contacts on one surface of the double-sided contact structure power chip 1 are electrically connected to each other and to each peripheral working device 2 through the upper trace area. The other surface of the double-sided contact structure power chip 1 is connected to the upper surface of the top copper layer 3-2 of the insulating substrate 3 it faces through a high thermal conductivity and electrical conductivity soldering material 9. At the same time, each contact on the other surface of the double-sided contact structure power chip 1 is electrically connected to the upper surface of the top copper layer 3-2 of the insulating substrate 3 it faces. The contacts on the other surface of the double-sided contact structure power chip 1 are electrically connected to each other and to each peripheral working device 2 through the connected top copper layer 3-2 of the insulating substrate 3 and the upper trace area.
[0029] The high thermal and electrical conductivity welding material 9 involved in the above design can be selected from any one of solder, silver paste, or sintered silver in practical applications.
[0030] Based on the above scheme design, such as Figure 3 and Figure 4 As shown, the design further includes at least one second copper pillar 10, with both ends of each second copper pillar 10 connected to the bottom routing layer 4 in the upper routing area and the top routing layer 4 in the lower routing area, respectively, to realize the electrical connection between the upper routing area and the lower routing area.
[0031] When applying the above to practice, a heat sink is further designed and added. Based on the design, the bottom trace layer 4 in the lower trace area is a whole copper plate layer. The heat sink is connected to the whole copper plate layer by soldering or applying thermal adhesive / silicone grease to dissipate heat and improve the heat dissipation effect.
[0032] The distributed insulation system packaging module designed in the above technical solution is based on a multilayer PCB board 5 with at least two built-in trace layers 4. A placement area is set between two adjacent trace layers 4, and multiple insulating substrates 3 are set to mount each power chip 1. The contacts on the surface of each power chip 1 are electrically connected to each other and to each peripheral working device 2 through the upper trace area of the multilayer PCB board 5. At the same time, each power chip 1 dissipates heat to the outside through the insulating substrate 3 and the lower trace area of the multilayer PCB board 5. In the design, the driver / control chip and the power chip are 3D stacked, resulting in a small loop area, small parasitics, and low loss. This makes the overall module area small and the cost low. It also reduces the area of ceramic plate used, which greatly reduces the cost and avoids the problem of stress cracking of large-area ceramic plates.
[0033] The embodiments of the present invention have been described in detail above with reference to the accompanying drawings. However, the present invention is not limited to the above embodiments. Within the scope of knowledge possessed by those skilled in the art, various changes can be made without departing from the spirit of the present invention.
Claims
1. A distributed insulation system packaging module for implementing system packaging for each power chip (1) and each peripheral working device (2) connected to it, characterized in that: The invention comprises at least one insulating substrate (3) and at least two embedded wiring layers (4) of a multilayer PCB board (5); wherein each insulating substrate (3) has the same structure, and each insulating substrate (3) includes an insulating and heat-conducting layer (3-1) and two copper layers (3-2) respectively disposed on the upper and lower surfaces of the insulating and heat-conducting layer (3-1). The space between any two adjacent wiring layers (4) is defined as the storage area, and each wiring layer (4) above the storage area is defined as the upper wiring area. Each adjacent wiring layer (4) in the upper wiring area is electrically connected to the other. Each wiring layer (4) below the storage area is defined as the lower wiring area. Each adjacent wiring layer (4) in the lower wiring area is electrically connected to the other. Each insulating substrate (3) is disposed in the storage area, and the bottom copper layer of each insulating substrate (3) is... (3-2) are connected to the top trace layer (4) in the lower trace area respectively; the top trace layer (4) in the upper trace area is located on the upper surface of the multilayer PCB board (5), and each peripheral working device (2) is electrically connected to the trace layer (4) on the upper surface of the multilayer PCB board (5) via the pad (6) respectively. The bottom trace layer (4) in the lower trace area is located on the lower surface of the multilayer PCB board (5); each power chip (1) is located in the area between the top copper layer (3-2) of each insulating substrate (3) in the placement area and the upper trace area respectively. Each contact on the surface of each power chip (1) is electrically connected to each other via the upper trace area and connected to each peripheral working device (2). Each power chip (1) is heat dissipated to the outside via the insulating substrate (3) and the lower trace area respectively.
2. The distributed insulation system encapsulation module according to claim 1, characterized in that: If the power chip (1) is a single-sided contact structure, the surface where the contacts of the single-sided contact structure power chip (1) are located faces the upper wiring area. Each contact on the single-sided contact structure power chip (1) is electrically connected to the bottom wiring layer (4) in the upper wiring area. The other surface of the single-sided contact structure power chip (1) is connected to the upper surface of the top copper layer (3-2) of the insulating substrate (3) it faces. If the power chip (1) is a double-sided contact structure, the upper surface of the copper layer (3-2) on the top of the insulating substrate (3) facing the double-sided contact structure power chip (1) is electrically connected to the bottom wiring layer (4) in the upper wiring area. Each contact on one surface of the double-sided contact structure power chip (1) is electrically connected to the bottom wiring layer (4) in the upper wiring area. Each contact on one surface of the double-sided contact structure power chip (1) is electrically connected to each other through the upper wiring area and is connected to each peripheral working device (2). The other surface of the double-sided contact structure power chip (1) is connected to the upper surface of the top copper layer (3-2) of the insulating substrate (3) it faces. At the same time, each contact on the other surface of the double-sided contact structure power chip (1) is electrically connected to the upper surface of the top copper layer (3-2) of the insulating substrate (3) it faces. Each contact on the other surface of the double-sided contact structure power chip (1) is electrically connected to each other through the top copper layer (3-2) of the connected insulating substrate (3) and the upper wiring area, and is connected to each peripheral working device (2).
3. The distributed insulation system encapsulation module according to claim 2, characterized in that: For the power chip (1) with double-sided contact structure, the upper surface of the top copper layer (3-2) of the insulating substrate (3) facing the double-sided contact structure power chip (1) is electrically connected to the bottom trace layer (4) in the upper trace area through a via structure (7).
4. The distributed insulation system encapsulation module according to claim 2, characterized in that: For the power chip (1) with double-sided contact structure, it also includes a first copper pillar (8) corresponding to the power chip (1) with double-sided contact structure. The height of the first copper pillar (8) is the same as the thickness of the power chip (1) with double-sided contact structure. One end of the first copper pillar (8) is disposed on the upper surface of the top copper layer (3-2) of the insulating substrate (3) to which the power chip (1) with double-sided contact structure is connected. The other end of the first copper pillar (8) is electrically connected to the bottom wiring layer (4) in the upper wiring area, so as to realize the electrical connection between the upper surface of the top copper layer (3-2) of the insulating substrate (3) facing the power chip (1) with double-sided contact structure and the bottom wiring layer (4) in the upper wiring area.
5. The distributed insulation system encapsulation module according to claim 2, characterized in that: The surface of the power chip (1) is connected to the top surface of the copper layer (3-2) on the insulating substrate (3) it faces by means of a high thermal conductivity and electrical conductivity welding material (9).
6. The distributed insulation system encapsulation module according to claim 5, characterized in that: The high thermal and electrical conductivity welding material (9) is any one of solder, silver paste, or sintered silver.
7. The distributed insulation system encapsulation module according to claim 1, characterized in that: It also includes at least one second copper pillar (10), with the two ends of each second copper pillar (10) connected to the bottom routing layer (4) in the upper routing area and the top routing layer (4) in the lower routing area, respectively, to realize the electrical connection between the upper routing area and the lower routing area.
8. The distributed insulation system encapsulation module according to claim 1, characterized in that: The insulating and thermally conductive layer (3-1) is made of ceramic or organic insulating and thermally conductive material.
9. The distributed insulation system encapsulation module according to claim 1, characterized in that: It also includes a heat sink. The bottom wiring layer (4) in the lower wiring area is a whole copper plate layer, and the whole copper plate layer is connected to the heat sink for heat dissipation.
10. A distributed insulation system encapsulation module according to any one of claims 1 to 9, characterized in that: Peripheral working devices (2) include drive control chips and various passive components.