Display device
By setting a barrier in the non-display area of the thin-film transistor layer of the AMOLED screen to prevent silicone sealant from overflowing, the problem of reduced ink surface energy caused by silicone sealant precipitation is solved, thereby improving the screen's impact resistance and long-term display effect.
Patent Information
- Application Number
- CN202422971833.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-03
- Publication Date
- 2025-12-12
- Estimated Expiration
- 2034-12-03
AI Technical Summary
In existing technologies, the precipitation of small molecules of silicone adhesive during the drop process of AMOLED screens leads to a decrease in the surface energy of the ink, affecting the long-term performance of the screen.
A barrier, including a top wall and side walls, is set in the non-display area of the thin-film transistor layer and wrapped with silicone sealant to prevent it from overflowing and contaminating the ink layer.
It effectively prevents small molecules of silicone sealant from precipitating onto the ink surface, maintains the surface energy value of the ink, and improves the long-term performance of the AMOLED screen.
Smart Images
Figure CN223666723U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of electronic equipment technology, and specifically to a display device. Background Technology
[0002] Active-matrix organic light-emitting diode (AMOLED) screens are commonly used in mobile phones, televisions, wearable devices, and more. Due to their thin structure, AMOLED screens are susceptible to external impacts or drops. To improve impact resistance during drops and ensure that the single-layer terminal area does not break, a silicone sealant is applied to the single-layer glass area to absorb external forces and reduce damage to the screen from drops.
[0003] Problems with existing technologies, such as Figure 1 As shown, after the silicone sealant comes into contact with the ink on the glass-covered surface, over time, small silicon molecules from the silicone sealant are easily precipitated and adsorbed onto the ink surface, causing a decrease in the ink surface energy (dyne value). Typically, the initial dyne value of the ink is >36A, but it decreases to <32A over time due to the influence of overflowing silicon molecules, thus affecting the long-term performance of the AMOLED screen. Utility Model Content
[0004] The purpose of this utility model is to provide a display device that solves the above-mentioned technical problems;
[0005] The technical problem solved by this utility model can be achieved by the following technical solution:
[0006] A display device, comprising,
[0007] A thin-film transistor layer, wherein a silicone adhesive is provided on the non-display area of the thin-film transistor layer;
[0008] An encapsulation layer is disposed on the display area of the thin-film transistor layer;
[0009] A polarizing layer is disposed on the encapsulation layer;
[0010] A glass layer is bonded to the polarizing layer with optical adhesive. An ink layer is provided below the glass layer and on the side of the optical adhesive. A barrier is provided on the ink layer at a position corresponding to the non-display area of the thin film transistor layer. The barrier includes a top wall connected to the lower surface of the ink layer and a side wall extending downward from the edge of the top wall. The projection of the silicone adhesive toward the ink layer falls within the range of the top wall between the side walls.
[0011] Preferably, the top of the silicone sealant is in contact with the lower surface of the top wall, and the side of the silicone sealant is a certain distance away from the side wall.
[0012] Preferably, the ink layer has a dyne test area extending from the edge of the non-display area corresponding to the thin film transistor layer to the edge of the ink layer away from the optical adhesive.
[0013] Preferably, the horizontal height of the bottom surface of the side wall near the dyne value test area is lower than the horizontal height of the bottom surface of the side wall away from the dyne value test area.
[0014] Preferably, the horizontal height of the bottom surface of the sidewall is lower than the horizontal height of the bottom surface of the polarizing layer.
[0015] Preferably, the glass layer extends from the display area of the thin-film transistor layer toward the non-display area, and the projection of the edge of the glass layer away from the optical adhesive toward the thin-film transistor layer is located outside the edge of the non-display area of the thin-film transistor layer.
[0016] Preferably, the edge of the glass layer away from the optical adhesive is flush with the edge of the ink layer away from the optical adhesive.
[0017] Preferably, the ink layer and the optical adhesive are spaced a certain distance apart, and the bottom surface of the optical adhesive is at a lower level than the bottom surface of the ink layer.
[0018] Preferably, the outer surface of the retaining wall has an anti-adhesion layer.
[0019] Preferably, the thin-film transistor layer is a low-temperature polycrystalline silicon layer.
[0020] The beneficial effects of this utility model are as follows: By adopting the above technical solution, this utility model can effectively prevent the small silicon molecules of silicone sealant from precipitating and adsorbing onto the surface of the ink layer, thus preventing the reduction of the dyne value of the ink surface. Attached Figure Description
[0021] Figure 1 This is a schematic diagram of the structure of a display device in the prior art;
[0022] Figure 2 This is a schematic diagram of the display device structure in an embodiment of the present utility model.
[0023] In the attached diagram: 1. Thin-film transistor layer; 2. Encapsulation layer; 3. Polarizing layer; 4. Optical adhesive; 5. Glass layer; 6. Silicone adhesive; 7. Ink layer; 8. Barrier wall; 81. Top wall; 82. Side wall; 9. Dyne value test area. Detailed Implementation
[0024] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present utility model.
[0025] It should be noted that, unless otherwise specified, the embodiments and features described in these embodiments can be combined with each other.
[0026] The present invention will be further described below with reference to the accompanying drawings and specific embodiments, but this is not intended to limit the present invention.
[0027] A display device, such as Figure 2 As shown, including,
[0028] Thin film transistor layer 1, with silicone adhesive 6 provided on the non-display area of thin film transistor layer 1;
[0029] Encapsulation layer 2 is disposed on the display area of thin-film transistor layer 1;
[0030] Polarizing layer 3 is disposed on encapsulation layer 2;
[0031] Glass layer 5 is bonded to polarizing layer 3 by optical adhesive 4. Below glass layer 5, on the side of optical adhesive 4, there is ink layer 7. Ink layer 7 is provided at the position of non-display area of thin film transistor layer 1 corresponding to ink layer 7. The barrier 8 includes a top wall 81 connected to the lower surface of ink layer 7 and a side wall 82 extending downward from the edge of top wall 81. The projection of silicone adhesive 6 toward ink layer 7 falls within the range of top wall 81 between side walls 82.
[0032] Specifically, this invention adds a barrier wall 8 to the ink surface corresponding to the position of the silicone sealant 6 to prevent silicone from being precipitated by the ink. The barrier wall 8 consists of a top wall 81 and a side wall 82. The top wall 81 is located on the surface below the ink layer 7, and the side wall 82 extends downward to cover the side of the silicone sealant 6. The projected area of the silicone sealant 6 falls within the range of the lower surface of the top wall 81, effectively preventing the silicone sealant 6 from accidentally overflowing or spreading to the ink layer 7 and avoiding contamination of the ink layer 7.
[0033] In a preferred embodiment, the top of the silicone sealant 6 is in contact with the lower surface of the top wall 81, and the side of the silicone sealant 6 is a certain distance away from the side wall 82.
[0034] Specifically, the fact that the side of the silicone sealant 6 is a certain distance away from the sidewall 82 means that the side of the silicone sealant 6 does not directly contact the sidewall 82, which can encapsulate the silicon molecules in the baffle 8 in three dimensions, reducing the probability of them escaping out of the baffle 8.
[0035] In a preferred embodiment, a dyne test area 9 is provided on the lower surface of the ink layer 7, extending from the edge of the non-display area corresponding to the thin film transistor layer 1 to the edge of the ink layer 7 away from the optical adhesive 4.
[0036] Specifically, the dyne value test area 9 is used to test the wettability (surface energy) of the surface material. The test method is to use a No. 36 dyne pen to draw a line on the dyne value test area 9. If the dyne ink in the dyne value test area 9 does not shrink within 5 seconds, it indicates that the dyne value of the area is ≥36A, indicating that the surface adhesion of the ink layer 7 meets the required requirements.
[0037] In a preferred embodiment, the horizontal height of the bottom surface of the sidewall 82 near the dyne test area 9 is lower than the horizontal height of the bottom surface of the sidewall 82 away from the dyne test area 9.
[0038] Specifically, the horizontal height of the bottom surface of the sidewall 82 near the dyne value test area 9 is lower than the horizontal height of the bottom surface of the sidewall 82 far from the dyne value test area 9, which can improve the constraint force on the silicone sealant 6 on the side near the dyne value test area 9 and further prevent silicon molecules from overflowing onto the surface of the ink layer 7.
[0039] In a preferred embodiment, the horizontal height of the bottom surface of the sidewall 82 is lower than the horizontal height of the bottom surface of the polarizing layer 3.
[0040] Specifically, this invention extends the sidewall 82 downwards as much as possible to wrap around the side of the silicone sealant 6 and prevent silicone molecules from overflowing.
[0041] In a preferred embodiment, the glass layer 5 extends from the display area of the thin-film transistor layer 1 toward the non-display area, and the projection of the edge of the glass layer 5 away from the optical adhesive 4 toward the thin-film transistor layer 1 is located outside the edge of the non-display area of the thin-film transistor layer 1.
[0042] In a preferred embodiment, the edge of the glass layer 5 away from the optical adhesive 4 is flush with the edge of the ink layer 7 away from the optical adhesive 4.
[0043] In a preferred embodiment, the ink layer 7 and the optical adhesive 4 are spaced a certain distance apart, and the bottom surface of the optical adhesive 4 is at a lower level than the bottom surface of the ink layer 7.
[0044] Specifically, the ink layer 7 and the optical adhesive 4 are spaced a certain distance apart, and the bottom surface of the optical adhesive 4 is lower than the bottom surface of the ink layer 7. This can prevent the ink layer 7 from overflowing or migrating onto the optical adhesive 4 layer, thereby preventing the optical adhesive 4 from contacting the ink and causing the surface ink to contaminate the optical adhesive 4 and affect the display effect.
[0045] In a preferred embodiment, the outer surface of the retaining wall 8 has an anti-adhesion layer.
[0046] Specifically, the outer surface of the retaining wall 8 is also provided with an anti-adhesion layer formed by a low surface energy material, and the ink layer 7 also uses a low surface energy material, which can effectively reduce the adhesion between the ink layer 7 and the retaining wall 8.
[0047] In a preferred embodiment, the thin-film transistor layer 1 is a low-temperature polycrystalline silicon layer.
[0048] Specifically, the thin-film transistor layer 1 is made of low-temperature polycrystalline silicon (LTPS), which has a higher electron mobility and can improve the display effect.
[0049] The above description is only a preferred embodiment of the present utility model and does not limit the implementation method and protection scope of the present utility model. Those skilled in the art should realize that all solutions obtained by equivalent substitutions and obvious changes made based on the description and illustrations of the present utility model should be included within the protection scope of the present utility model.
Claims
1. A display device, characterized in that, include, Thin film transistor layer (1), wherein silicone adhesive (6) is provided on the non-display area of the thin film transistor layer (1); An encapsulation layer (2) is disposed on the display area of the thin-film transistor layer (1); A polarizing layer (3) is disposed on the encapsulation layer (2); A glass layer (5) is bonded to the polarizing layer (3) by optical adhesive (4). An ink layer (7) is provided below the glass layer (5) on the side of the optical adhesive (4). A barrier (8) is provided on the ink layer (7) at the position corresponding to the non-display area of the thin film transistor layer (1). The barrier (8) includes a top wall (81) connected to the lower surface of the ink layer (7) and a side wall (82) extending downward from the edge of the top wall (81). The projection of the silicone adhesive (6) toward the ink layer (7) falls within the range of the top wall (81) between the side walls (82).
2. The display device according to claim 1, characterized in that, The top of the silicone sealant (6) is in contact with the lower surface of the top wall (81), and the side of the silicone sealant (6) is a certain distance away from the side wall (82).
3. The display device according to claim 1, characterized in that, The ink layer (7) has a dyne test area (9) on its lower surface, starting from the edge of the non-display area corresponding to the thin film transistor layer (1) and ending at the edge of the ink layer (7) on the side away from the optical adhesive (4).
4. The display device according to claim 3, characterized in that, The horizontal height of the bottom surface of the side wall (82) near the dyne test area (9) is lower than the horizontal height of the bottom surface of the side wall (82) away from the dyne test area (9).
5. The display device according to claim 1, characterized in that, The horizontal height of the bottom surface of the sidewall (82) is lower than the horizontal height of the bottom surface of the polarizing layer (3).
6. The display device according to claim 1, characterized in that, The glass layer (5) extends from the display area of the thin film transistor layer (1) toward the non-display area, and the projection of the edge of the glass layer (5) away from the optical adhesive (4) toward the thin film transistor layer (1) is located outside the edge of the non-display area of the thin film transistor layer (1).
7. The display device according to claim 1, characterized in that, The edge of the glass layer (5) away from the optical adhesive (4) is flush with the edge of the ink layer (7) away from the optical adhesive (4).
8. The display device according to claim 1, characterized in that, The ink layer (7) and the optical adhesive (4) are spaced a certain distance apart, and the bottom surface of the optical adhesive (4) is lower than the bottom surface of the ink layer (7).
9. The display device according to claim 1, characterized in that, The outer surface of the retaining wall (8) has an anti-adhesion layer.
10. The display device according to claim 1, characterized in that, The thin-film transistor layer (1) is a low-temperature polycrystalline silicon layer.