Semiconductor device

Abstract

The utility model relates to a semiconductor device. The first semiconductor device and the second semiconductor device are bonded together using a bonding contact pad buried in a bonding dielectric layer of the first semiconductor device and using at least one bonding via buried in a bonding dielectric layer of the second semiconductor device. The bonding contact pad extends a first dimension in a first direction perpendicular to a main surface of the first semiconductor device and a second dimension in a second direction parallel to a plane of the first semiconductor wafer. The second dimension is at least twice the first dimension. The joint guide hole extends in the first direction by a third dimension and extends in the second direction by a fourth dimension. The third dimension is at least twice the first dimension. Bonding contact pads and bonding vias may be at least partially buried in respective bonding dielectric layers of respective topmost dielectric layers of respective stacked interconnect layers.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to semiconductor devices, and more particularly to semiconductor packages with ultra-fine pitch bonding. BACKGROUND

[0002] The semiconductor industry has experienced rapid growth due to advances in technology. In most cases, the increase in integration density is due to iterative reduction in the minimum feature size, which allows more components to be integrated into a given area. As the demand for electronic devices increases, there is a growing need for smaller and more creative semiconductor die packaging techniques. An example of such a packaging system is the Package-on-Package (PoP) technology. In a Package-on-Package (PoP) device, a top semiconductor package is stacked on top of a bottom semiconductor package to provide high integration and component density. PoP technology generally enables the production of semiconductor devices with enhanced functionality and small footprint on a printed circuit board (PCB).

[0003] Stacked semiconductor devices have become an effective technique for further reducing the physical size of semiconductor devices. In a stacked semiconductor device, active circuits such as logic circuits and memory circuits are fabricated on different semiconductor wafers. Two or more semiconductor wafers can be bonded together by suitable bonding techniques to further reduce the form factor of the semiconductor device. SUMMARY

[0004] In some embodiments, a semiconductor device is provided. The semiconductor device includes a first semiconductor chip, a first interconnect structure, and a second semiconductor chip. The first semiconductor chip has a plurality of first active components formed on the first semiconductor chip. The first interconnect structure is on the plurality of first active components, and the first interconnect structure includes a conductive via and a bond contact pad. The bond contact pad is at least partially embedded in a first bond dielectric layer. The bond contact pad has a first length in a direction parallel to a major plane of the first semiconductor chip and a second length in a direction perpendicular to the major plane of the first semiconductor chip, where the first length exceeds the second length. The second semiconductor chip has a second interconnect structure formed on the second semiconductor chip, the second interconnect structure including a plurality of stacks of a plurality of second metal lines embedded in a respective plurality of second dielectric layers, and the second semiconductor chip includes a bond via that is at least partially embedded in a second bond dielectric layer. The bond via has a third length in a direction perpendicular to the major plane of the first semiconductor chip and a fourth length in a direction parallel to the major plane of the first semiconductor chip, where the third length exceeds the fourth length. A major surface of the bond contact pad is bonded to a major surface of the bond via. A major surface of the first bond dielectric layer is bonded to a major surface of the second bond dielectric layer.

[0005] Preferably, a ratio of the third length to the fourth length exceeds 2:1.

[0006] Preferably, a ratio of the third length to the first length is at least 2:1.

[0007] Preferably, a ratio of the third length to the first length is at least 20:1.

[0008] Preferably, a ratio of the second length to the fourth length is at least 1:1.

[0009] Preferably, a topmost surface of the bond contact pad is substantially coplanar to a topmost surface of the first bond dielectric layer.

[0010] Preferably, a surface area of the bond via is less than a surface area of the contact pad.

[0011] Preferably, a surface area of the bond via is greater than or equal to 25% of a surface area of the contact pad.

[0012] Preferably, the bond via has a tapered profile, and a first cross-sectional dimension of the bond via at a location where the tapering begins is less than a second cross-sectional dimension of the bond via at a location of a topmost surface.

[0013] Preferably, the semiconductor device further includes an underlying via that is embedded within the first bond dielectric layer. BRIEF DESCRIPTION OF DRAWINGS

[0014] The embodiments of the present application will be described hereinafter with reference to the drawings, wherein the figures of the drawings show the embodiments of the present application. It should be noted that the various elements in the drawings are not drawn to scale and are merely meant to illustrate the embodiments of the present application. In fact, the dimensions of the various elements can be arbitrarily increased or decreased, for the sake of clarity, in order to clearly show the components of the embodiments of the present application.

[0015] FIG. 1A and FIG. 1B is a cross-sectional view of a first semiconductor device at an intermediate stage of fabrication, according to some embodiments.

[0016] FIG. 2 is a cross-sectional view of a second semiconductor device at an intermediate stage of fabrication, according to some embodiments.

[0017] FIG. 3 is a cross-sectional view of the first semiconductor device and the second semiconductor device bonded together, according to some embodiments.

[0018] FIG. 4A to FIG. 4C is a cross-sectional view of a bonding pad and a bonding via, according to different embodiments.

[0019] FIG. 5A and FIG. 5B , FIG. 6A and FIG. 6B , and FIG. 7A to FIG. 7D are top views of a combination of a bonding pad and a bonding via, according to different embodiments.

[0020] FIG. 8A to FIG. 8C is a cross-sectional view of the first semiconductor device and the second semiconductor device bonded together, according to different embodiments.

[0021] FIG. 9A to FIG. 9F is a cross-sectional view of a bonding pad and a bonding via, according to yet another embodiment.

[0022] FIG. 10A and FIG. 10B schematically illustrates dimensions of an exemplary bonding pad and an exemplary bonding via.

[0023] FIG. 11 is a flow chart of a fabrication process, according to an embodiment.

[0024] FIG. 12 illustrates a packaged device including results of additional back-end processing.

[0025] In the drawings, reference numbers are generally used to refer to same or similar elements unless otherwise described in connection with the figure in which the elements are found.

[0026] 100, 200: semiconductor device

[0027] 101, 201: substrate

[0028] 103, 203: active device

[0029] 105, 205: interconnect structure

[0030] 107, 207: metal line

[0031] 109, 209: via

[0032] 110: contact pad

[0033] 110T, 111T, 211T: topmost dielectric layer

[0034] 111, 211: dielectric layer

[0035] 115, 116: bonding dielectric layer

[0036] 117: via hole

[0037] 121: backside pad

[0038] 123: external connector

[0039] 210: bonding via

[0040] 210', 210": point

[0041] 300: bonding interface

[0042] L: horizontal dimension

[0043] T: vertical dimension DETAILED DESCRIPTION

[0044] The following disclosure provides different embodiments or examples for implementing various components of the provided subject matter. Specific examples of components and their configurations are described below to facilitate a thorough understanding of the present disclosure. Of course, these are merely examples and are in no way intended to limit the scope of this disclosure. For example, if a first component is described as being formed on a second component, this can include embodiments where the first and second components are in direct contact, as well as embodiments where additional components are formed between the first and second components such that they are not in direct contact. Furthermore, the present disclosure can repeat use of reference numerals and / or letters in various examples. This repetition of reference numerals and / or letters is for the purpose of simplicity and clarity and does not necessarily indicate a common

[0045] Furthermore, relative terms such as "beneath" "below" "lower" "above" "upper" and like terms can be used herein for ease of description to describe one element or component's relationship to another element(s) or component(s) as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the figures. The devices can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0046] FIG. 1A A side view of an exemplary first semiconductor device 100 is depicted, where the exemplary first semiconductor device 100 includes a substrate 101. For clarity, only a small portion of the substrate 101 is shown. In some embodiments, the first semiconductor device 100 can be a die or a package component. The substrate 101 can be a bulk silicon substrate, although other semiconductor materials including Group III, Group IV, and Group V elements can also be used. Active devices 103 such as transistors can be formed in and / or on the substrate 101.

[0047] An interconnect structure 105 is formed over the substrate 101. In some embodiments, the interconnect structure 105 can include at least one dielectric layer 111 such as dielectric layers 111 formed from silicon oxides, silicon oxy-nitrides, silicon carbides, low-k dielectric materials having a low dielectric constant (low-k, k) value of less than about 4.0, and the like. For example, the low-k dielectric materials can have a k value of less than about 4.0. In some embodiments, the dielectric layers of the interconnect structure 105 can be made of, for example, silicon oxide, SiCOH, and the like. The interconnect structure 105 includes a plurality of metal lines 107 for interconnecting various active devices 103, and further includes vias 109 formed in respective ones of the plurality of dielectric layers 111 for interconnecting the plurality of metal lines located in different layers of the interconnect structure 105. In this document, the term "line" will be used to refer to a conductive structure present within a layer of the interconnect structure 105 and generally extending in either the X-direction or the Y-direction, i.e., parallel to a major surface of the substrate 101, in accordance with common usage in the art, and the term "via" or "conductive via" will be used to refer to a conductive structure extending between different levels of lines within the interconnect structure and electrically interconnecting them. The "via" generally extends in the Z-direction, or perpendicular to the major surface of the substrate 101. Although the metal lines 107 and the vias 109 are shown as being formed in the same layers of the interconnect structure 105, in some embodiments, the metal lines 107 and the vias 109 can be formed in different layers of the interconnect structure 105. FIG. 1A-FIG. 1BOnly three levels of lines are shown in the exemplary interconnect structure 105, but one of ordinary skill in the art will recognize that many such levels, perhaps eight or more, can be used in practical applications. The metal lines 107 and vias 109 can be formed of copper or copper alloy, but can be formed of other metals. The metal lines and vias can be formed by etching openings in a dielectric layer, filling the openings with a conductive material, and performing planarization, such as chemical mechanical polishing (CMP), to level the top surfaces of the metal lines and vias with the top surface of the dielectric layer. In general, the metal lines 107 and underlying vias 109 use a dual damascene process, which is: first patterning the relevant dielectric layer 111 to have openings corresponding to the metal lines 107; then patterning the relevant dielectric layer 111 a second time to have openings corresponding to the vias 109; and then filling the openings with, for example, copper (a so-called trench-first dual damascene process). Alternatively, the dual damascene process is: first patterning the relevant dielectric layer 111 to have openings corresponding to the vias 109; then patterning the relevant dielectric layer 111 a second time to have openings corresponding to the metal lines 107; and then filling the two openings with, for example, copper (a so-called via-first dual damascene process).

[0048] As further shown, FIG. 1A The topmost layer includes metal lines 107 in the topmost layer, and further includes contact pads 110 also formed in or at least partially formed in the topmost dielectric layer 111. As shown, the topmost vias 109 formed in the topmost dielectric layer 111 electrically connect the topmost metal lines 107 to the corresponding contact pads 110. As described above, the topmost metal lines 107 and topmost vias 109 can be formed using a trench-first dual damascene process or a via-first dual damascene process.

[0049] While not limited, the contact pad 110 may be formed from the same or similar material as the metal wire 107, such as copper or copper alloys (or other metals, for example, but not exhaustively, including molybdenum, manganese, titanium, tungsten, aluminum, cobalt, and their alloys). In some embodiments, while deposition processes such as electroplating, electroless plating, and the like are also contemplated within the scope of this disclosure, damascene processes may also be used to form the contact pad. Regardless of the process used to form the contact pad 110, in most embodiments it is desirable for the contact pad 110 to have a corresponding top surface substantially flush with the top surface of the topmost dielectric layer as the topmost surface, which will serve as the bonding surface during the wafer-to-wafer bonding process further described in subsequent descriptive paragraphs. However, in some embodiments, some or all of the respective top surfaces of the contact pads 110 may be slightly lower than the top surface of the topmost dielectric layer, provided that the distance between the respective top surface of the contact pads 110 and the top surface of the topmost dielectric layer is small enough that the gap can be filled by thermal expansion of the respective contact pads 110, mechanical deformation of the topmost dielectric layer, or a combination of both.

[0050] FIG. 1B The illustration shows the situation in the FIG. 1A After the semiconductor device 100 undergoes an optional wafer thinning process, the thickness of the substrate 101 in the process is significantly reduced. In some anticipated embodiments, the thickness of the substrate 101 is reduced from about 750 μm to about 30 μm, or perhaps 50 μm, or perhaps 100 μm, depending on the application to which the semiconductor device 100 will be used. As known in the art, such thinning can be achieved by a backside grinding process, a backside etch process, or a similar process. As described below, the semiconductor device 100 is bonded to another semiconductor device in a subsequent process. In some embodiments, thinning is performed after, rather than before, bonding the semiconductor device to the other semiconductor device, and in yet another embodiment, no thinning is performed on the semiconductor device 100. FIG. 1A The device shown is FIG. 1B The only difference between the illustrated devices is the optional back-side thinning step, so FIG. 1A and FIG. 1B It is usually referred to as Figure 1 in the following explanatory paragraphs, unless the context otherwise requires.

[0051] FIG. 2 A side view of an exemplary second semiconductor device 200 is shown, which also includes a substrate 201. For clarity, only a small portion of the substrate 201 is shown. In some embodiments, the second semiconductor device 200 can also be a die or a package assembly. The substrate 101 can be a substrate similar to the substrate 101 (FIG. 1), or a completely different type of substrate. While not necessarily a limiting condition, as a guideline, the thermal expansion characteristics of the substrate 201 and the semiconductor device 200 are generally better matched or at least compatible with the thermal expansion characteristics of the substrate 101 and / or the semiconductor device 100. Active devices 203, such as transistors, can be formed in and / or on the substrate 201. However, in other embodiments, when the semiconductor device 200 is a passive structure such as an interposer or similar (i.e., having only electrical interconnections and / or passive devices such as capacitors, inductors, resistors, and the like), then no such active devices 203 are provided on the semiconductor device 200.

[0052] As with the semiconductor device 100, the semiconductor device 200 also includes an interconnect structure 205, which in the illustrated embodiment has three layers of metal lines 207 buried within respective dielectric layers 211. The metal lines 207 are interconnected to various active devices 203 that can be present or other passive devices (not shown) that can be present. The metal lines 207 can be made of similar materials as the metal lines 107 of FIG. 1, although different materials for the metal lines 207 formed using different processes than the metal lines 107 are within the contemplation of the present embodiments. Similarly, the materials of the dielectric layers 211 can be similar to the materials of the dielectric layers 111, although this is not a limitation or requirement of the present disclosure. FIG. 2 Also disclosed are vias 209 that are electrically interconnected to different layers of the metal lines 207. As noted above, the distinction between the metal lines 207 and the vias 209 is that the metal lines generally extend in the XY plane and are electrically interconnected to different components within a layer, while the vias extend in the Z direction in the XY plane and are electrically interconnected to components within different layers of the interconnect structure 105 (as well as components that are not part of the interconnect structure 205). While only three layers of metal lines 207 are shown in the exemplary interconnect structure 205, one of ordinary skill in the art will recognize that many such layers can be used in practical applications. FIG. 2

[0053] As noted above, the metal lines 207 and the vias 209 are formed using different processes. For example, the metal lines 207 can be formed using a damascene process, while the vias 209 can be formed using a dual damascene process. As another example, the metal lines 207 can be formed using a first metal, while the vias 209 can be formed using a second metal that is different than the first metal. As yet another example, the metal lines 207 can be formed using a first process, while the vias 209 can be formed using a second process that is different than the first process. FIG. 2 ​As further illustrated, the interconnect structure 205 also includes a top layer. The top layer includes metal lines 207 located within it. The top layer has bonding vias 210 embedded therein or at least partially embedded therein. It should be noted that since there are no metal lines above the bonding vias 210, these bonding vias 210 can be formed using a single damascene process, which reduces manufacturing complexity and cost.

[0054] Semiconductor device 100 in Figure 1 and FIG. 2 A significant difference between the semiconductor devices 200 is FIG. 2 The illustrated device does not include contact pad 110. In fact, the inventors of this disclosure have recognized several advantageous effects that can be obtained in the embodiments described herein, wherein the semiconductor device for wafer-to-wafer bonding processes is formed with features such as… FIG. 2 The illustrated engagement guide hole 210 is mated and engaged with a contact pad 110, such as that illustrated in Figure 1. FIG. 3 An example of this is shown in the figure. FIG. 3 A packaging device is illustrated, comprising semiconductor devices 100 and 200 bonded together. Of particular note is that, in the illustrated embodiment, semiconductor device 200 does not have corresponding contact pads aligned and bonded to the contact pads 110 of semiconductor device 100. Instead, as shown, the contact pads 110 of semiconductor device 100 are aligned and directly bonded to the bonding vias 210 of semiconductor device 200. More specifically, as... FIG. 3 As shown, the semiconductor device 100 is inverted such that the top surface of its top dielectric layer 110T faces downward (in the direction shown). Similarly, the top surfaces of each contact pad 110 also face downward (in the direction shown). In this way, the contact pads 110 can be aligned and directly contact the bonding vias 210 of the semiconductor device 200 (in some embodiments, the contact pads 110 or bonding vias 210, or both contact pads 110 and bonding vias 210, are slightly recessed below the top surface of the dielectric layer 111 or dielectric layer 211 on which they are formed; in this case, the corresponding contact pads and bonding vias will be aligned but may not necessarily contact until further processing (e.g., thermal processing) has been performed). Similarly, the top dielectric layers 111T of the semiconductor device 100 and 211T of the semiconductor device 200 are also aligned and contacted, and these dielectric layers are bonded together to form a bonding interface 300 therebetween.

[0055] As noted above, the use of directly bonding via 210 to contact pad 110 simplifies the manufacturing and bonding process (e.g., single damascene versus dual damascene, more flexible overlay windows, and the like), and thus reduces the cost of the resulting structure. Additional advantageous features will be apparent in light of the following description of additional embodiments.

[0056] Reference is now made to FIG. 4A to FIG. 4C , which illustrate, in cross-sectional view, various embodiments in which exemplary via 210 is bonded to exemplary contact pad 110. In FIG. 4A , via 210 is configured as a single via having substantially vertical and parallel sidewalls. FIG. 5A The configuration shown in FIG. 4A is illustrated in top view. As shown, the total surface area of via 210 is less than the surface area of contact pad 110, although this is not a limiting condition. In some embodiments, the surface area of via 210 can be as low as 25% of the surface area of contact pad 110. FIG. 6A Yet another embodiment is illustrated in top view, in which the relationship between the surface area of contact pad 110 and the surface area of via 210 is similar to that shown in FIG. 5A , but in which via 210 has a rectangular shape as seen in top view. Conversely, in the embodiment shown in FIG. 7A , contact pad 110 has a rectangular shape in top view, while via 210 has a circular or round shape in top view. In this embodiment, via 210 again provides a lenient alignment window relative to the surface area of contact pad 110. Although not illustrated, embodiments in which both via 210 and contact pad 110 have a rectangular shape are also within the intended scope of the present disclosure.

[0057] Reference is now made to FIG. 4B , FIG. 5B , FIG. 6B and FIG. 7B , which illustrate various embodiments in which via 210 has a tapered profile, best seen in the cross-sectional view of FIG. 4B . Those having ordinary skill in the art will recognize that various processes can be employed to form a tapered profile as shown in FIG. 4BThe conical profile is shown. As an example, a photo mask layer (before bonding to the semiconductor device 100) such as a photo resist (not shown) can be formed on the topmost dielectric layer 211T; the photo resist layer can be patterned to form openings therein having a conical profile; and the conical profile can be transferred to the underlying dielectric layer using, for example, an appropriate etching process. For such a conical profile, the bonding via 210 has a first cross-sectional dimension at the location of the point 210' where the coning begins, and a second, larger cross-sectional dimension at the location of the point 210" which is the topmost surface of the bonding via 210, which is the location where the bonding via 210 is bonded to the contact pad 110. Relative to, for example FIG. 4A and FIG. 5A the configuration shown in provides a larger surface area for bonding and a lower resistance. When the bonding via 210 is aligned with the contact pad 110, the contact pad with its large surface area provides a more relaxed alignment window relative to the surface area of the bonding via.

[0058] FIG. 5B The configuration of FIG. 4B is shown in a top view. Although the bonding via 210 is not visible in the top view due to the blocking of the contact pad 110, these components are shown here to illustrate their relative dimensions and surface areas, including the contact pad 110 and the bonding via 210 at the locations of the point 210' and the point 210" described above. Similarly, the configuration of a rectangular bonding via 210 with a conical profile is shown in a top view in FIG. 6B , and the conical bonding via 210 with a rectangular contact pad 110 is shown in FIG. 7B .

[0059] Continuing now to FIG. 4C , in this embodiment, multiple bonding vias 210 are bonded to the contact pad 110. FIG. 4C The configuration is shown in a cross-sectional view, and FIG. 7C the same structure is shown in a top view. Although a circular bonding via 210 is shown bonded to a rectangular contact pad 110, one of ordinary skill in the art will recognize that any combination of circular and / or rectangular (or any other shape) bonding vias 210 with any combination of circular and / or rectangular (or any other shape) contact pads 110 is still within the intended scope of the present disclosure. Furthermore, as shown in FIG. 7D , combinations of embodiments of FIG. 4A , FIG. 4B and FIG. 4C such as embodiments in which multiple conical bonding vias 210 are bonded to each (or selected) contact pad 110 are also contemplated.

[0060] In FIG. 8A , FIG. 8B and FIG. 8COther additional embodiments are illustrated. First, from FIG. 8A In this embodiment, semiconductor device 200 includes a bonding dielectric layer 115 in which a bonding via 210 is formed or at least partially formed. In this embodiment, bonding dielectric layer 115 is bonded to the topmost dielectric layer 111T of semiconductor device 100. By way of example, bonding dielectric layer 115 can be a silicon oxide layer, a silicon oxynitride layer, a silicon carbide layer, and the like. Similarly, in this embodiment, a bonding dielectric layer 116 is formed on semiconductor device 100 and is bonded to the topmost dielectric layer 211T of semiconductor device 200 in this illustrative embodiment. In yet another embodiment, a bonding dielectric layer 115 is formed on the topmost surface of semiconductor device 200; a bonding dielectric layer 116 is formed on the topmost surface of semiconductor device 100; and bonding dielectric layer 115 and bonding dielectric layer 116 are brought into contact and bonded together to bond semiconductor device 100 to semiconductor device 200, as shown in FIG. 8B FIG. 8C

[0061] FIG. 9A FIG. 9B FIG. 9C FIG. 4A FIG. 4B FIG. 4C FIG. 9D FIG. 9E FIG. 9F

[0062] As noted above, advantageous effects can be obtained by using a bonding via that is bonded to a bonding contact pad. In terms of technology, these advantageous effects stem from the distinction between a bonding via and a bonding contact pad. By way of example, in the embodiment of FIG. 4A as described above, the exemplary bonding via 210 is an electrically conductive hole, which means that it is oriented primarily in a vertical direction (herein "vertical" describes a direction that is perpendicular to the plane of substrate 201), while the exemplary bonding contact pad 210 is horizontally oriented (i.e., extends primarily in a direction that is parallel to the plane of substrate 201). These distinctions are illustrated by FIG. 10A FIG. 10B FIG. 10B ​​​​​​​​​​​​​An exemplary bonding via 210 (bonding via) is shown, with its vertical dimension T extending in the Z direction and its horizontal dimension L extending in the XY plane. It should be noted that, as an artifact (vertical interconnect component perpendicular to the stack layer or perpendicular to the stack direction) used for bonding via 210, the vertical dimension T of bonding via 210 is significantly larger than its horizontal dimension L. In contrast, as... FIG. 10A The example illustrated shows that the exemplary contact pad 110 has a horizontal dimension L extending in the XY plane, which is significantly larger than its vertical dimension T extending in the Z direction. As an example, the ratio of the horizontal dimension L to the vertical dimension T for contact pad 110 is typically in the range of several hundred, for example, 1000:1. In contrast, the engagement via 210 will have the opposite relationship, with the ratio of the vertical dimension T to the horizontal dimension L typically in the range of around 1000:1, with outer boundaries as low as around 3:1 or 2:1. Due to variations in film thickness and minimum component dimensions, the ratio of the vertical dimension T to the horizontal dimension L for both contact pad 110 and engagement via 210 can vary considerably between different applications. Therefore, the relative relationship between these two ratios is a more reliable guideline. In most cases, engagement via 210 will have a vertical dimension T in the Z direction that is at least twice the vertical dimension T of contact pad 110, and preferably at least twenty times the vertical dimension T of contact pad 110. Similarly, as a useful guideline, the horizontal dimension L of the contact pad 110 should be at least 1.1 times, preferably at least 1.2 times, the horizontal dimension L of the engagement guide hole 210.

[0063] FIG. 11A flow diagram of an embodiment of an exemplary fabrication process is illustrated. The process begins at step 1100 by forming a first integrated circuit on a first substrate. Next, an interconnect structure including a contact pad is formed, as indicated by step 1102. Concurrently, prior to, or subsequent to this, a second integrated circuit can optionally be formed on a second substrate, as indicated by optional step 1108 (in dashed box). An interconnect structure that does not include a bonding contact but does include a bonding via can optionally be formed on the second substrate (step 1110). Optionally, a bonding dielectric layer can be formed over the first interconnect structure of the first semiconductor device, as indicated by optional step 1104 (in dashed box). Alternatively or additionally, a bonding dielectric layer can be formed over the second interconnect structure, as indicated by step 1112 (in dashed box). Optionally, the first substrate can be back-thinned, as indicated by optional step 1106. Alternatively or additionally, the second substrate can optionally be back-thinned, as indicated by step 1114. In step 1116, the contact pad of the first interconnect structure and the bonding via of the second interconnect structure are aligned with each other. Next, the first substrate and the second substrate are bonded together, including bonding the contact pad and the bonding via together. Finally, further back-end processing is performed, such as additional back-thinning, electrical connections to through-substrate vias, formation of electrical connectors, and the like, as indicated by step 1120.

[0064] FIG. 12 Further back-end processing steps 1120 are illustrated in FIG. 1 1 1 1, which shows semiconductor device 100 bonded to semiconductor device 200, and also shows through-substrate via 1 1 7 extending through substrate 101 (one of ordinary skill in the art will recognize that via 1 1 7 is typically formed at least partially concurrently with interconnect structure 105 (see step 1102 of FIG. 1 1 1 1 )). FIG. 11 FIG. 12 A back-side redistribution layer (RDL) 1 1 9 is also illustrated in FIG. 1 1 1 1, which electrically connects through-substrate via 1 1 7 (as well as other electronic components of semiconductor device 100) to aluminum back-side pad 121 and external connector 123. One of ordinary skill in the art will recognize that external connector 123 can be a solder bump, a copper micro-bump or copper pillar, a controlled collapse chip connection, and the like.

[0065] ​In some embodiments, a method of forming a semiconductor package is provided. The method of forming a semiconductor package includes forming a plurality of first active components on a first semiconductor wafer; forming a first interconnect structure over the plurality of first active components using a dual damascene process, and further forming a conductive via and a bond contact pad over the plurality of first active components using the dual damascene process, wherein the first interconnect structure includes a plurality of first tiers of metal lines embedded within a corresponding plurality of dielectric layers, wherein the bond contact pad is at least partially embedded in a first bond dielectric layer, and wherein the conductive via is electrically connected to the bond contact pad and a top metal line of the plurality of first tiers; forming a second interconnect structure on a second semiconductor wafer, and further forming a bond via on the second semiconductor wafer using a single damascene process, wherein the second interconnect structure includes a plurality of second tiers of second metal lines embedded within a corresponding plurality of second dielectric layers, and wherein the bond via is at least partially embedded in a second bond dielectric layer; aligning the bond via with the bond contact pad; contacting the first bond dielectric layer to the second bond dielectric layer; bonding the first bond dielectric layer to the second bond dielectric layer; and bonding the bond via to the bond contact pad.

[0066] In some embodiments, the top metal lines of the plurality of first tiers are buried within the first bonding dielectric layer. In some embodiments, the top metal lines of the plurality of first tiers are buried within an interconnect structure dielectric layer, and wherein the first bonding dielectric layer is deposited on the interconnect structure dielectric layer. In some embodiments, the bonding vias have a first dimension in a direction perpendicular to a major plane of the first semiconductor wafer, the bonding contact pads have a second dimension in the direction perpendicular to the major plane of the first semiconductor wafer, and wherein a ratio of the first dimension to the second dimension is at least 2: 1. In some embodiments, the bonding vias have a first dimension in a direction perpendicular to a major plane of the first semiconductor wafer, the bonding contact pads have a second dimension in the direction perpendicular to the major plane of the first semiconductor wafer, and wherein a ratio of the first dimension to the second dimension is at least 20: 1. In some embodiments, the bonding vias have a first dimension in a direction perpendicular to a major plane of the first semiconductor wafer, the bonding contact pads have a second dimension in the direction perpendicular to the major plane of the first semiconductor wafer, and wherein a ratio of the first dimension to the second dimension is between about 2: 1 and about 20: 1. In some embodiments, the method of forming a semiconductor package further comprises at least one of: backside thinning the first semiconductor wafer; backside thinning the second semiconductor wafer; and backside thinning both the first semiconductor wafer and the second semiconductor wafer. In some embodiments, the method of forming a semiconductor package further comprises forming a plurality of second active components on the second semiconductor wafer. In some embodiments, the bonding contact pads are bonded to the bonding vias while bonding the first bonding dielectric layer to the second bonding dielectric layer.

[0067] In some embodiments, a method of forming a semiconductor package is provided. The method of forming a semiconductor package includes: forming a bonding contact pad and an underlying via on a first semiconductor wafer, wherein the bonding contact pad is buried within a first bonding dielectric layer, wherein the bonding contact pad extends a first dimension in a first direction perpendicular to the first semiconductor wafer and a second dimension in a second direction parallel to a plane of the first semiconductor wafer, wherein the second dimension is at least twice the first dimension; planarizing the first bonding dielectric layer, the bonding contact pad, or both, such that a topmost surface of the bonding contact pad is substantially planar with a topmost surface of the first bonding dielectric layer; forming a second bonding dielectric layer on a second semiconductor wafer, wherein the second bonding dielectric layer has a bonding via buried therein, wherein the bonding via extends a third dimension in the first direction and a fourth dimension in the second direction, and wherein the third dimension is at least twice the first dimension; aligning the bonding contact pad with the bonding via; and bonding the bonding contact pad to the bonding via.

[0068] In some embodiments, the method of forming a semiconductor package further includes bonding the first bonding dielectric layer to the second bonding dielectric layer. In some embodiments, the bonding contact pads and the underlying vias are formed together in a dual damascene process, and the bonding vias are formed in a single damascene process. In some embodiments, a ratio of the third dimension to the first dimension is at least 2: 1. In some embodiments, a ratio of the third dimension to the first dimension is at least 20: 1. In some embodiments, a ratio of the second dimension to the fourth dimension is at least 1: 1. In some embodiments, the underlying vias are also embedded within the first bonding dielectric layer. In some embodiments, the method of forming a semiconductor package further includes tapering the plurality of upper sidewalls of the bonding vias to taper the bonding vias outward from the centerline. In some embodiments, the method of forming a semiconductor package further includes aligning the plurality of bonding vias to the bonding contact pads and bonding the bonding vias to the bonding contact pads.

[0069] In some embodiments, a semiconductor device is provided. The semiconductor device includes a first semiconductor chip, a first interconnect structure, and a second semiconductor chip. The first semiconductor chip has a plurality of first active components formed on the first semiconductor chip. The first interconnect structure is on the plurality of first active components, and the first interconnect structure includes a conductive via and a bonding contact pad. The bonding contact pad is at least partially embedded in a first bonding dielectric layer. The bonding contact pad has a first length in a direction parallel to a major plane of the first semiconductor chip and a second length in a direction perpendicular to the major plane of the first semiconductor chip, where the first length exceeds the second length. The second semiconductor chip has a second interconnect structure formed on the second semiconductor chip, the second interconnect structure including a plurality of stacks of a plurality of second metal lines embedded in a corresponding plurality of second dielectric layers, and the second semiconductor chip includes a bonding via at least partially embedded in a second bonding dielectric layer. The bonding via has a third length in a direction perpendicular to the major plane of the first semiconductor chip and a fourth length in a direction parallel to the major plane of the first semiconductor chip, where the third length exceeds the fourth length. A major surface of the bonding contact pad is bonded to a major surface of the bonding via. A major surface of the first bonding dielectric layer is bonded to a major surface of the second bonding dielectric layer.

[0070] In some embodiments, a ratio of the third length to the fourth length exceeds 2: 1.

[0071] The components of the above-described embodiments are summarized in order to enable a person having ordinary knowledge in the art to which the present application pertains to better understand the viewpoint of the present application. It should be understood by a person having ordinary knowledge in the art to which the present application pertains that they can design or modify other processes and structures based on the embodiments of the present application to achieve the same purpose and / or advantages as the embodiments introduced herein. A person having ordinary knowledge in the art to which the present application pertains should also understand that such processes and structures and their equivalents do not deviate from the spirit and scope of the present application, and they can make various changes, substitutions and replacements without deviating from the spirit and scope of the present application.

Claims

1. A semiconductor device, characterized by comprising: Comprising: a first semiconductor chip having a plurality of first active components formed thereon; a first interconnect structure on the plurality of first active components, the first interconnect structure including a conductive via and a bond contact pad at least partially embedded in a first bond dielectric layer, the bond contact pad having a first length in a direction parallel to a major plane of the first semiconductor chip and a second length in a direction perpendicular to the major plane of the first semiconductor chip, wherein the first length exceeds the second length; a second semiconductor chip having a second interconnect structure formed thereon, the second interconnect structure including a plurality of stacks of a plurality of second metal lines embedded in a corresponding plurality of second dielectric layers, and the second semiconductor chip including a bond via at least partially embedded in a second bond dielectric layer, the bond via having a third length in a direction perpendicular to the major plane of the first semiconductor chip and a fourth length in a direction parallel to the major plane of the first semiconductor chip, wherein the third length exceeds the fourth length; a major surface of the bond contact pad bonded to a major surface of the bond via; and a major surface of the first bond dielectric layer bonded to a major surface of the second bond dielectric layer. The ratio of the third length to the fourth length exceeds 2:

1.

2. The semiconductor device according to claim 1, wherein The ratio of the third length to the first length is at least 2:

1.

3. The semiconductor device according to claim 1, wherein The ratio of the third length to the first length is at least 20:

1.

4. The semiconductor device according to claim 1, wherein The ratio of the second length to the fourth length is at least 1:

1.

5. The semiconductor device according to claim 1, wherein A topmost surface of the bond contact pad is substantially coplanar to a topmost surface of the first bond dielectric layer.

6. The semiconductor device according to claim 1, wherein The bond via has a surface area that is less than a surface area of the contact pad.

7. The semiconductor device according to claim 1, wherein The bond via has a surface area that is greater than or equal to 25% of a surface area of the contact pad.

8. The semiconductor device according to claim 7, wherein The bond via has a tapered profile, and a first cross-sectional dimension of the bond via at a location where the tapering begins is less than a second cross-sectional dimension of the bond via at a location of a topmost surface.

9. The semiconductor device according to claim 1, wherein Further comprising an underlying via embedded within the first bond dielectric layer.

10. The semiconductor device according to any one of Claims 1 to 9, wherein ​

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