Integrated circuit structure

Abstract

The integrated circuit structure includes a shallow trench isolation region, a first gate structure and a second gate structure. The shallow trench isolation region is adjacent to an active region in the semiconductor substrate. The first gate structure is over the active region. The first gate structure includes a high-k gate dielectric layer and a gate metal layer over the high-k gate dielectric layer. The second gate structure is over the shallow trench isolation region. The second gate structure includes a gate metal layer in contact with the shallow trench isolation region in a cross-sectional view taken along a first direction perpendicular to a longitudinal axis of the second gate structure.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to an integrated circuit structure. BACKGROUND

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. A semiconductor device is typically fabricated by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor material layers on a semiconductor substrate, and patterning each material layer using lithography to form circuit components and elements on the material layers.

[0003] The semiconductor industry continues to advance the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continually reducing the size of the individual components that are integrated onto a given area. SUMMARY

[0004] In some embodiments, an integrated circuit structure includes a shallow trench isolation region adjacent to an active region in a semiconductor substrate; a first gate structure over the active region, the first gate structure including a high-k gate dielectric layer and a gate metal layer over the high-k gate dielectric layer; and a second gate structure over the shallow trench isolation region, wherein in a cross-sectional view taken in a first direction perpendicular to a longitudinal axis of the second gate structure, the second gate structure includes a gate metal layer in contact with the shallow trench isolation region.

[0005] In some embodiments, an integrated circuit structure includes a shallow trench isolation region adjacent to an active region in a semiconductor substrate; a first gate structure over the active region, the first gate structure including a high-k gate dielectric layer and a gate metal layer over the high-k gate dielectric layer; and a second gate structure over the shallow trench isolation region, wherein in a cross-sectional view taken in a first direction perpendicular to a longitudinal axis of the second gate structure, the second gate structure includes a work function metal layer in contact with the shallow trench isolation region.

[0006] In some embodiments, an integrated circuit structure includes a shallow trench isolation region adjacent to an active region in a semiconductor substrate; a first gate structure over the active region, the first gate structure including a high-k gate dielectric layer and a gate metal layer over the high-k gate dielectric layer; and a second gate structure over the shallow trench isolation region, wherein in a cross-sectional view taken in a first direction perpendicular to a longitudinal axis of the second gate structure, the second gate structure includes a work function metal layer over the shallow trench isolation region, the work function metal layer being separated from a recess in the shallow trench isolation region. BRIEF DESCRIPTION OF DRAWINGS

[0007] The various features illustrated are not all required, all separate parts, or carried out in any particular order. Rather, various embodiments of the present disclosure can be directed to various feature combinations.

[0008] FIG. 1A 、 FIG. 2A 、 FIG. 3A 、 FIG. 4A 、 FIG. 5A 、 FIG. 6A 、 FIG. 7A 、 FIG. 8A 、 FIG. 9A 、 FIG. 10A 、 FIG. 11A 、 FIG. 12A 、 FIG. 13A and FIG. 14A drawn to a top view of an intermediate stage in the manufacturing process;

[0009] FIG. 1B 、 FIG. 2B 、 FIG. 3B 、 FIG. 4B 、 FIG. 5B 、 FIG. 6B 、 FIG. 7B 、 FIG. 8B 、 FIG. 9B 、 FIG. 10B 、 FIG. 11B 、 FIG. 12B 、 FIG. 13B and FIG. 14B drawn to a cross-sectional view corresponding to line B-B in the "A" drawing;

[0010] FIG. 10C 、 FIG. 13C and FIG. 14C drawn to a cross-sectional view corresponding to line C-C in the "A" drawing;

[0011] FIG. 15A and FIG. 16A drawn to a top view of an intermediate stage in the manufacturing process;

[0012] FIG. 15B and FIG. 16B drawn to a cross-sectional view corresponding to line B-B in the "A" drawing;

[0013] FIG. 17A and FIG. 18A drawn to a top view of an intermediate stage in the manufacturing process;

[0014] FIG. 17B and FIG. 18B drawn to a cross-sectional view corresponding to line B-B in the "A" drawing;

[0015] FIG. 19Aand FIG. 20A top view of an intermediate stage in the manufacturing process;

[0016] FIG. 19B and FIG. 20B cross-sectional view corresponding to line B-B in "A".

[0017]

Symbol Explanation

[0018] 102: substrate

[0019] 102A: first region

[0020] 102B: second region

[0021] 102L: longitudinal edge

[0022] 102S: lateral edge

[0023] 102T: trench

[0024] 104: pad layer

[0025] 106: mask layer

[0026] 108: STI fill material

[0027] 109: location

[0028] 110: recess

[0029] 112: high-k dielectric layer

[0030] 112C: recess

[0031] 114: dummy gate layer

[0032] 116A, 116B: dummy gate structure

[0033] 118A, 118B: gate spacer

[0034] 120A, 120B: high-k gate dielectric layer

[0035] 122A, 122B: source / drain epitaxial structure

[0036] 124: ILD layer

[0037] 130A, 130B: gate structure

[0038] 132, 134: work function metal layer

[0039] 132L: lower portion

[0040] 132U: upper portion

[0041] 136: fill metal layer

[0042] 201, 301, 401: STI region

[0043] 202, 204, 206, 208, 302, 304, 306, 308: Active region

[0044] 212, 214, 216, 312, 314, 316, 412, 414, 416: Designated gate region

[0045] 400: Active region

[0046] 402: First active region

[0047] 404: Second active region

[0048] 1162: First region

[0049] 1164: Second region

[0050] B-B, C-C: Line

[0051] GT1, GT2: Gate trench

[0052] L2: Longitudinal edge

[0053] O1-O8: Opening

[0054] P1-P4: Patterned mask

[0055] S2: Lateral edge

[0056] X3: X-direction dimension

[0057] Y3: Y-direction dimension DETAILED DESCRIPTION

[0058] The following disclosure provides many different embodiments, or examples, for implementing various characteristics of the provided subject matter. Each of the following described embodiments and / or examples and / or results can be implemented alone, or in combination with element(s) and / or example(s) of any other embodiments and / or examples. Of course, those of ordinary skill in the art will recognize that many modifications can be made to the embodiments and examples described in this disclosure, and that such modifications, and / or any substitution of chemical or structural equivalents, are contemplated to fall within the scope of the pertinent embodiments. There can be many alternative configurations other than those explicitly discussed in this disclosure. All such modifications and variations are intended to be included herein within the scope of the disclosure. The order or sequence of any process or method can be different, and the use or type of specific

[0059] Furthermore, spatially relative terms, such as "beneath", "below", "lower", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The devices can be otherwise oriented (rotated 230 degrees or at other orientations) and the spatially relative descriptions used herein interpreted accordingly. As used herein, the terms "left", "right", "about", "approximately", or "substantially" can generally mean within 20%, or within 10%, or within 5% of a given value or range. Numerical values given herein are approximate, and the terms "about", "approximately", or "substantially" are intended to be construed accordingly unless specifically indicated otherwise. However, those skilled in the art will recognize that the values or ranges recited in the description are merely examples and that the values or ranges can decrease as integrated circuits shrink.

[0060] Shallow trench isolation (STI) is a technique used in integrated circuit (IC) fabrication to isolate different active regions of a wafer, which are regions where transistors and other components are formed. The STI process involves etching trenches in a substrate and then filling the trenches with an insulating material, such as silicon dioxide, to electrically isolate the active regions from one another. However, various factors in the fabrication process, such as etching and / or chemical-mechanical polishing (CMP), can cause recesses to form at the boundaries between the STI regions and the active regions, which are small recesses or indentations that occur at the interfaces where the STI regions and the active regions meet. These recesses can adversely affect the performance and / or reliability of the semiconductor device.

[0061] For example, when a high-k dielectric layer is deposited over a substrate and then patterned into local high-k gate dielectric layers, remnants of the high-k dielectric material can inadvertently become trapped within these recesses. This trapping can increase the risk of a leakage path from the active region to the gate structure over the STI region. To address this issue, the present disclosure provides additional lithography and etching steps in various embodiments to remove the high-k dielectric remnants trapped in the recesses, thereby mitigating potential leakage.

[0062] FIGS. 1A-14C Top view and cross-sectional views illustrating intermediate stages in an IC structure fabrication process, in accordance with some example embodiments. FIG. 1A FIG. 2A FIG. 3A FIG. 4A FIG. 5A FIG. 6A ​​​​​, FIG. 7A , FIG. 8A , FIG. 9A , FIG. 10A , FIG. 11A , FIG. 12A , FIG. 13A and FIG. 14A draws a top view of an intermediate stage in the manufacturing process. FIG. 1B , FIG. 2B , FIG. 3B , FIG. 4B , FIG. 5B , FIG. 6B , FIG. 7B , FIG. 8B , FIG. 9B , FIG. 10B , FIG. 11B , FIG. 12B , FIG. 13B and FIG. 14B draws a cross-sectional view corresponding to line B-B in the "A" drawing. FIG. 10C , FIG. 13C and FIG. 14C draws a cross-sectional view corresponding to line C-C in the "A" drawing. It is to be understood that additional embodiments of the method can provide additional operations before, during, and after the processes shown in FIGS. 1A-14C some of the operations described below can be replaced or eliminated. The order of the operations / processes can be interchanged.

[0063] FIG. 1A and FIG. 1B draws an initial structure for fabricating an IC structure. The initial structure includes a substrate 102. The substrate 102 can be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, etc., can be doped (e.g., with p-type or n-type dopants) or undoped. The substrate 102 can be a wafer, such as a silicon wafer. Typically, an SOI substrate is a layer of semiconductor material formed on an insulating layer. The insulating layer can be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulating layer is disposed on a substrate, typically a silicon or glass substrate. Other substrates can also be used, such as a multilayer or graded substrate. In some embodiments, the semiconductor material of the substrate 102 can include silicon; germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium indium arsenide phosphide; or combinations thereof.

[0064] FIG. 1A and FIG. 1BA liner layer 104 is formed over the substrate 102 and a mask layer 106 is formed over the liner layer 104. In some embodiments, the liner layer 104 can be a thin film containing silicon oxide formed using, for example, a thermal oxidation process. The liner layer 104 can act as an adhesion layer between the substrate 102 and the mask layer 106. The liner layer 104 can also act as an etch stop layer for etching the mask layer 106. In some embodiments, the mask layer 106 is formed of silicon nitride, for example, using low-pressure chemical vapor deposition (LPCVD) or plasma enhanced chemical vapor deposition (PECVD). The mask layer 106 is used as a hard mask during subsequent lithography processes.

[0065] The liner layer 104 and the mask layer 106 are patterned by appropriate lithography and etching techniques. For example, a photoresist material is formed over the mask layer 106 by a spin-on process, and then the photoresist material is patterned by an appropriate lithography process to form a patterned photoresist layer over the mask layer 106. For example, the photoresist material is exposed to radiation and developed to remove portions of the photoresist material. In more detail, a photomask (not shown) can be placed over the photoresist material, and then can be exposed to a beam of radiation, which can be ultraviolet (UV) or an excimer laser, such as a krypton fluoride (KrF) excimer laser or an argon fluoride (ArF) excimer laser. The exposure of the photoresist material can be performed, for example, using an immersion lithography tool or an extreme ultraviolet light (EUV) tool to improve resolution and reduce the minimum pitch that can be achieved. A bake or cure operation can be performed to harden the exposed photoresist material, and the exposed or unexposed portions of the photoresist material can be removed using a developer, depending on whether a positive or negative photoresist is used.

[0066] With the patterned photoresist present, the mask layer 106 and the liner layer 104 are patterned using the patterned photoresist as an etch mask, thereby exposing the first regions 102A of the substrate 102 while covering the second regions 102B of the substrate 102. The first regions 102A are referred to as STI regions, over which STI dielectric material will be formed in subsequent processing, and the second regions 102B are referred to as active regions, over which functional transistors will be formed in subsequent processing.

[0067] In FIG. 2A and FIG. 2BIn some embodiments, the STI fill material 108 is formed of an insulating material, such as silicon oxide, nitride, etc., or a combination thereof. The insulating material can be formed by high density plasma chemical vapor deposition (HDP-CVD), flowable CVD (FCVD) (e.g., depositing a CVD-based material in a remote plasma system and post-curing to transform into another material, such as an oxide), etc., or a combination thereof. Other insulating materials formed by any acceptable process can be used. In the depicted embodiment, the insulating material of the STI fill material 108 is silicon oxide formed by a FCVD process. Once the insulating material is formed, an anneal process can be performed. Although the insulating material of the STI fill material 108 is depicted as a single layer, some embodiments can use multiple layers. For example, a liner (not shown) can first be formed along the surface of the substrate 102. Thereafter, a fill material (such as the fill materials described above) can be formed over the liner. In some embodiments, after depositing the STI fill material 108 in the trench 102T, a CMP process is performed on the STI fill material 108 such that the top surface of the STI fill material 108 is substantially flush with the top surface of the mask layer 106.

[0068] In FIG. 3A and FIG. 3B In some embodiments, the STI fill material 108 is formed of an insulating material, such as silicon oxide, nitride, etc., or a combination thereof. The insulating material can be formed by high density plasma chemical vapor deposition (HDP-CVD), flowable CVD (FCVD) (e.g., depositing a CVD-based material in a remote plasma system and post-curing to transform into another material, such as an oxide), etc., or a combination thereof. Other insulating materials formed by any acceptable process can be used. In the depicted embodiment, the insulating material of the STI fill material 108 is silicon oxide formed by a FCVD process. Once the insulating material is formed, an anneal process can be performed. Although the insulating material of the STI fill material 108 is depicted as a single layer, some embodiments can use multiple layers. For example, a liner (not shown) can first be formed along the surface of the substrate 102. Thereafter, a fill material (such as the fill materials described above) can be formed over the liner. In some embodiments, after depositing the STI fill material 108 in the trench 102T, a CMP process is performed on the STI fill material 108 such that the top surface of the STI fill material 108 is substantially flush with the top surface of the mask layer 106.

[0069] In FIG. 4A and FIG. 4BIn some embodiments, one or more etching processes are employed to remove the liner 104 and the mask layer 106, and to etch back the STI fill material 108. Phosphoric acid (H3PO4) and hydrofluoric acid (HF) can be used as etching solutions for the mask layer 106 (e.g., nitride material) and the liner 104 (e.g., oxide material), respectively. These etching processes, particularly the etching process for the liner 104, also remove the STI fill material 108 from the top surface of the substrate 102. As a result of this etch-back process, the top corners of the STI trench 102T experience a significant removal of the STI fill material 108 at various locations 109 near the active region 102B. This results in a recess (also referred to as a recessed region) 110 that is concave from the top surface of the STI fill material 108, and can expose an upper portion of the sidewall 102S of the active region 102B. The reason for this occurrence is that the wet etching process etches faster along the interface between the substrate 102 and the STI fill material 108 than it does in other areas of the STI fill material 108.

[0070] In FIG. 5A and FIG. 5B The high-k dielectric layer 112 is blanket-deposited over the substrate 102, across the STI region 102A and the active region 102B. The high-k dielectric layer 112 contacts and covers the top surface of the STI fill material 108 and the active region 102B of the substrate 102. In some embodiments, the high-k dielectric layer 112 includes a dielectric material having a high dielectric constant, e.g., greater than that of thermal silicon oxide (~3.9). The high-k dielectric layer 112 can include hafnium oxide (HfO2). Alternatively, the high-k dielectric layer 112 can include other high-k dielectric layers such as hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), lanthanum oxide (LaO), zirconium oxide (ZrO), titanium oxide (TiO), tantalum oxide (Ta2O5), yttrium oxide (Y2O3), strontium titanium oxide (SrTiO3, STO), barium titanium oxide (BaTiO3, BTO), barium zirconium oxide (BaZrO), hafnium lanthanum oxide (HfLaO), lanthanum silicon oxide (LaSiO), aluminum silicon oxide (AlSiO), aluminum oxide (Al2O3), silicon nitride (Si3N4), silicon oxynitride (SiON), and combinations thereof. The high-k dielectric layer 112 can be formed by atomic layer deposition (ALD), chemical vapor deposition (CVD), and / or other suitable methods.

[0071] As FIG. 5BAs shown, the high-k dielectric layer 112 has a recess 112C within the recess 110 of the STI fill material 108. In some cases, this recess 112C can be in contact with the sidewall of the active region 102B. Such contact can increase the risk of a leakage path from the active region 102B to the gate structure, which will be subsequently formed on the STI region 102A. This risk is higher compared to the case where the high-k dielectric layer 112 is not in contact with the sidewall of the active region 102B.

[0072] In FIG. 6A and FIG. 6B A patterned mask P1 is formed over the high-k dielectric layer 112. In some embodiments, the patterned mask P1 is a patterned photoresist formed using a suitable lithography process. In an exemplary lithography process, a photoresist material is illuminated (exposed) and developed to remove portions of the photoresist material. In more detail, a photomask or mask (not shown) can be placed over the photoresist material, which can then be exposed to a beam of radiation, which can be ultraviolet (UV) or an excimer laser, such as a krypton fluoride (KrF) excimer laser or an argon fluoride (ArF) excimer laser. The exposure of the photoresist material can be performed, for example, using an immersion lithography tool or an extreme ultraviolet light (EUV) tool to increase resolution and reduce the minimum pitch that can be achieved. A bake or cure operation can be performed to harden the exposed photoresist material. A developer can be used to remove either the exposed or unexposed portions of the photoresist material (depending on whether a positive or negative photoresist is used), leaving a patterned photoresist mask P1 over the high-k dielectric layer 112 with openings O1 exposing regions of the high-k dielectric layer 112, including the recess 112C.

[0073] In FIG. 7A and FIG. 7BIn some embodiments, the high-k dielectric layer 112 is patterned by using the patterned mask P1 as an etch mask in an etching process to create openings O2 extending through the high-k dielectric layer 112 to expose a portion of the STI fill material 108. The etching process removes the recessed portion 112C of the high-k dielectric layer 112 from the recess 110, thereby reducing the risk of a leakage path from the active region 102B to a gate structure that will later be formed over the STI region 102A. Suitable etching techniques, such as wet etching, dry etching, or a combination thereof, can be used to pattern the high-k dielectric layer 112. For example, a dry etching process for patterning the high-k dielectric layer 112, such as hafnium oxide (Hf02), can be performed using a reactive ion etching (RIE) technique. In this process, a plasma of a fluorine-based gas, such as carbon tetrafluoride (CF4), trifluoromethane (CHF3), or sulfur hexafluoride (SF6), can be used as the etchant. These etching conditions can effectively etch the high-k dielectric layer 112 while minimizing damage to the exposed STI fill material 108.

[0074] After the openings O2 are formed in the high-k dielectric layer 112, the patterned mask P1 can be removed, for example, using a plasma ashing process. In some embodiments, the plasma ashing process is performed such that the temperature of the photoresist is raised until the photoresist undergoes thermal decomposition and can be removed. However, any other suitable process, such as a wet stripping, can be used.

[0075] In some embodiments, the openings O2 in the high-k dielectric layer 112 have a quadrilateral profile in a top view, as shown in FIG. 7A For example, the openings O2 have opposing longitudinal sides L2 and opposing transverse sides S2 that are shorter than the longitudinal sides L2. The active region 102B includes opposing longitudinal sides 102L and a transverse side 102S that is shorter than the longitudinal sides 102L and connects the longitudinal sides 102L. As shown in the top view of FIG. 7A The transverse side 102S of the active region 102B is in contact with the transverse sides S2 of the openings O2 in this manner. In this way, the transverse side 102S of the active region 102B is free of the high-k dielectric layer 112, thereby mitigating potential leakage current.

[0076] In FIG. 8A and FIG. 8B A dummy gate layer 114 is formed over the STI region 102A and the active region 102B. In some embodiments, the dummy gate layer 114 can be deposited, such as by CVD, over the STI fill material 108 and the high-k dielectric layer 112 and then planarized, such as by CMP.

[0077] In FIG. 9A and FIG. 9BIn some embodiments, dummy gate layer 114 is patterned using acceptable lithography and etching techniques to form dummy gate structures 116A and 116B. The etching can include acceptable anisotropic etching, such as RIE, NBE, etc. Dummy gate structures 116A and 116B include a first dummy gate structure 116A that overlaps a channel region of active region 102B and a second dummy gate structure 116B that does not overlap active region 102B. First dummy gate structure 116A is located on and in contact with high-k dielectric layer 112, while second dummy gate structure 116B is located on and in contact with STI fill material 108. Dummy gate structures 116A and 116B can have a length direction that is substantially perpendicular to a length direction of active region 102B.

[0078] In some embodiments, dummy gate layer 114 is patterned using an appropriate etching process that does not leave behind poly-silicon residue, or negligible poly-silicon residue, in recess 110 in STI region 102A, mitigating potential leakage current. For example, an etching process to pattern dummy gate layer 114, which can include poly-silicon, can involve a reactive ion etching (RIE) technique using a gas mixture of chlorine (Cl2) and hydrogen bromide (HBr). This combination is very effective for anisotropic etching of poly-silicon, providing high selectivity to underlying oxide material and reducing poly-silicon residue.

[0079] In some embodiments, dummy gate layer 114 is patterned using an appropriate etching process that does not leave behind poly-silicon residue, or negligible poly-silicon residue, in recess 110 in STI region 102A, mitigating potential leakage current. For example, an etching process to pattern dummy gate layer 114, which can include poly-silicon, can involve a reactive ion etching (RIE) technique using a gas mixture of chlorine (Cl2) and hydrogen bromide (HBr). This combination is very effective for anisotropic etching of poly-silicon, providing high selectivity to underlying oxide material and reducing poly-silicon residue. FIG. 10A and FIG. 10BIn this configuration, gate spacers 118A and 118B are formed on the sidewalls of dummy gate structures 116A and 116B, respectively. In some embodiments, a gate spacer 118B is formed near a recess 110 but does not overlap with the recess 110. In some embodiments of the gate spacer formation step, a spacer material layer is deposited on substrate 102. The spacer material layer may be a conformal layer, which is then etched back to form the gate spacers 118A and 118B. For example (but not limited to), the spacer material can be formed by depositing a dielectric layer material over the dummy gate structures 116A and 116B using a suitable deposition process (such as CVD, subatmospheric CVD (SACVD), flowable CVD, ALD, PVD, or other suitable processes). An anisotropic etching process is then performed on the deposited dielectric material to expose portions of the active region 102B not covered by the dummy gate structures 116A and 116B (e.g., in the source / drain regions of the active region 102B). This anisotropic etching process can completely remove portions of the spacer layer directly above the dummy gate structure 116. Portions of the spacer layer sidewalls of the dummy gate structures 116A and 116B can be retained to form gate sidewall spacers, which, for simplicity, are referred to as gate spacers 118A and 118B.

[0080] In some embodiments, by using dummy gate structures 116A, 116B and gate spacers 118A, 118B as etching masks, a high-k dielectric layer 112 is patterned during the etching process, thereby leaving a portion of the high-k dielectric layer 112 directly beneath the dummy gate structures 116A and gate spacers 118A to serve as the high-k gate dielectric layer 120A, such as... FIG. 10B As shown, two independent portions of a high-k dielectric layer 112 are left directly below the dummy gate structure 116B and the gate spacer 118B to serve as a high-k gate dielectric layer 120B separated by the opening O2, as... FIG. 10C As shown. A selective etching process can be used to etch the high-k dielectric layer 112. This selective etching process erodes the high-k material but leaves the dummy gate structures 116A, 116B and gate spacers 118A, 118B virtually untouched. For example, a dry etching process (such as plasma etching using fluorine-based chemicals such as carbon tetrafluoride (CF4) or trifluoromethane (CHF3)) can be used to perform a selective etching process for etching the high-k dielectric material (such as hafnium oxide (HfO2)). These etchants selectively remove hafnium oxide while leaving the polysilicon-based dummy gate structures 116A, 116B and nitride-based gate spacers 118A, 118B substantially intact.

[0081] exist FIG. 10BIn the cross-sectional view, the resulting high-k gate dielectric layer 120A contacts the entire bottom surface of the dummy gate structure 116A. The high-k gate dielectric layer 120A extends laterally beyond the opposite sidewalls of the dummy gate structure 116A and has opposing end faces substantially aligned with the outermost sidewall of the gate spacer 118A. On the other hand, in FIG. 10B In the cross-sectional view, the dummy gate structure 116B is in contact with the STI filler material 108, and there is no high-k material between the dummy gate structure 116B and the STI filler material 108. However, in such... FIG. 10C In another cross-sectional view shown along the longitudinal axis of the dummy gate structure 116B, the bottom surface of the dummy gate structure 116B has a first region 1162 in contact with the STI filling material 108 and a second region 1164 in contact with the high-k dielectric layer 120B.

[0082] exist FIG. 11A and FIG. 11B In this process, after patterning the high-k dielectric layer into high-k gate dielectric layers 120A and 120B, source / drain epitaxial structures 122A and 122B are formed on the source / drain regions of the active region 102B. The dummy gate structure 116A and gate spacer 118A do not cover these source / drain regions. In some embodiments, the formation of the source / drain epitaxial structures 122A and 122B includes recessing the source / drain regions of the active region 102B, and then epitaxially growing semiconductor material in the recessed source / drain regions of the active region 102B. For clarity, the source / drain epitaxial structures 112A and 112B are... FIG. 11B It is shown in the cross-sectional view, but FIG. 11A Not shown in the top view.

[0083] The source / drain regions of the active regions 102B can be recessed using a suitable selective etch process that attacks the active regions 102B but attacks the dummy gate structures 116A, 116B and the gate spacers 118A, 118B very little. For example, the active regions 102B can be recessed by dry chemical etching with a plasma source and etching gas. The plasma source can be inductively coupled plasma (ICP) etching, transformer coupled plasma (TCP) etching, electron cyclotron resonance (ECR) etching, reactive ion etching (RIE), or the like, and the etching gas can be fluorine, chlorine, bromine, combinations thereof, or the like, that etches the active regions 102B faster than the dummy gate structures 116A, 116B and the gate spacers 118A, 118B. In some other embodiments, the active regions can be recessed by wet chemical etching, such as ammonium peroxide mixture (APM), NH4OH, tetramethylammonium hydroxide (TMAH), combinations thereof, or the like, that etches the active regions 102B faster than the dummy gate structures 116A, 116B and the gate spacers 118A, 118B. In some other embodiments, the active regions can be recessed by a combination of dry chemical etching and wet chemical etching.

[0084] Once the recesses are formed in the source / drain regions of the active region 102B, source / drain epitaxial structures 122A and 122B are formed in the source / drain recesses in the active region 102B by one or more epitaxial processes that provide one or more epitaxial materials on the active region 102B. In the epitaxial growth process, the gate spacers 118A confine the one or more epitaxial materials to the source / drain regions in the active region 102B. In some embodiments, the lattice constant of the epitaxial structures 122A, 122B is different from the lattice constant of the semiconductor material within the active region 102B, such that the channel regions within the active region 102B and between the epitaxial structures 122A and 122B are able to be strained or stressed by the epitaxial structures 122A and 122B to improve carrier mobility and enhance device performance. The epitaxial processes include CVD deposition techniques (e.g., PECVD, vapor-phase epitaxy (VPE), and / or ultra-high vacuum CVD (UHV-CVD)), molecular beam epitaxy, and / or other suitable processes. The epitaxial processes can use gaseous and / or liquid precursors that interact with the semiconductor composition of the active region 102B. In some embodiments, the epitaxial structures 122A and 122B can have surfaces that are raised from the top surface of the active region 102B.

[0085] In some embodiments, the source / drain epitaxial structures 122A and 122B can include Ge, Si, GaAs, AlGaAs, SiGe, GaAsP, SiP, or other suitable materials. The source / drain epitaxial structures 122A and 122B can be in-situ doped during the epitaxial process by introducing dopant species including p-type dopants such as boron or BF2, n-type dopants such as phosphorus or arsenic, and / or other suitable dopants, including combinations thereof. If the source / drain epitaxial structures 122A and 122B are not in-situ doped, implantation processes (i.e., implantation processes) are performed to dope the source / drain epitaxial structures 122A and 122B. In some example embodiments, the source / drain epitaxial structures 122A and 122B in n-type transistors include SiP, while the source / drain epitaxial structures 122A and 122B in p-type transistors include GeSnB and / or SiGeSnB. In embodiments with different device types, a mask (such as a photoresist) can be formed over the n-type device regions while exposing the p-type device regions, and p-type epitaxial structures are formed on the exposed active region 102B in the p-type device regions. The mask can then be removed. Subsequently, a mask (such as a photoresist) can be formed over the p-type device regions while exposing the n-type device regions, and n-type epitaxial structures are formed on the exposed active region 102B in the n-type device regions. The mask can then be removed.

[0086] Once the source / drain epitaxial structures 122A and 122B are formed, an annealing process can be performed to activate the p-type or n-type dopants in the source / drain epitaxial structures 122A and 122B. Annealing processes can include, for example, rapid thermal annealing (RTA), laser annealing, and millisecond thermal annealing (MSA).

[0087] In some embodiments, such as FIG. 11B As shown, the source / drain epitaxial structure 122B has sidewalls adjacent to the recess 110 in the STI filling material 108. If high-k dielectric layer residues are present in the recess 110, the risk of a leakage path from the source / drain epitaxial structure 122B to the dummy gate structure 116B may increase. However, by employing... FIGS. 6A-7B The processing steps shown can effectively remove high-k dielectric layer residues in the recess 110, thereby reducing the possibility of leakage.

[0088] exist FIG. 12A and FIG. 12B In this process, an interlayer dielectric (ILD) layer 124 is formed on substrate 102. In some embodiments, a contact etchstop layer (CESL) may be optionally formed prior to the formation of the ILD layer 124. In some instances, the CESL comprises a silicon nitride layer, a silicon oxide layer, a silicon oxynitride layer, and / or other suitable materials having a different etch selectivity than the ILD layer 124. The CESL may be formed by a plasma-enhanced chemical vapor deposition (PECVD) process and / or other suitable deposition or oxidation processes. In some embodiments, the ILD layer 124 comprises an oxide such as tetraethoxysilane (TEOS), undoped silicate glass, or doped silicon oxide, such as borosilicate glass (BPSG), fused silica glass (FSG), silicon phosphide glass (PSG), boron-doped silicon glass (BSG), and / or other suitable dielectric materials having a different etch selectivity than the CESL. The ILD layer 124 may be deposited by a PECVD process or other suitable deposition techniques. In some embodiments, after the formation of the ILD layer 124, the wafer can withstand a high thermal budget process to anneal the ILD layer 124.

[0089] In some examples, after the ILD layer 124 is formed, a planarization process can be performed to remove excess material of the ILD layer 124. For example, the planarization process includes a chemical mechanical planarization (CMP) process that removes portions of the ILD layer 124 (and the CESL, if present) that cover the dummy gate structures 116A and 116B until the dummy gate structures 116A and 116B are exposed.

[0090] In FIGS. 13A-C the exposed dummy gate structures 116A, 116B are removed by one or more etching processes to form gate trenches GT1 between the gate spacers 118A and gate trenches GT2 between the gate spacers 118B. In some embodiments, the dummy gate structures 116A and 116B are removed using a selective etching process (e.g., a selective dry etching, a selective wet etching, or a combination thereof) that etches the material in the dummy gate structures 116A, 116B at a faster rate than other materials (e.g., the gate spacers 118A, 118B and / or the ILD layer 124). As shown in the top view of FIGS. 13A-C in the active region 102B, the high-k gate dielectric layer 120A is exposed at the bottom of the gate trench GT1 and occupies the entire footprint of the gate trench GT1 when viewed in the top view of FIG. 13A in the STI region 102A, the STI fill material 108 and the high-k gate dielectric layer 120B are exposed at the bottom of the gate trench GT2 and the high-k gate dielectric layer 120B occupies a partial area of the gate trench GT2 footprint, resulting from a high-k dielectric patterning process performed in the step shown in FIGS. 6A-7B

[0091] In FIGS. 14A-C ​In this embodiment, alternative gate structures 130A and 130B are formed in gate trenches GT1 and GT2, respectively. Gate structure 130A may be a functional gate of a transistor formed on active region 102B. Gate structure 130B may be a non-functional gate formed on STI region 102A, or a functional gate of another transistor formed on another active region (not shown). Gate structures 130A and 130B may each form a high-k / metal gate (HKMG) stack with underlying high-k gate dielectric layers 120A and 120B, but other combinations are also possible. In some embodiments, gate structure 130A forms a gate associated with the channel region between source / drain epitaxial structures 122A and 122B. In various embodiments, gate structures 130A and 130B each include one or more work function metal layers, including a first work function metal layer 132 located above the high-k gate dielectric layers 120A and 120B, a second work function metal layer 132 located above the first work function metal layer 132, and fill metal 136 formed above the work function metal layers 132 and filling the remaining portions of the gate trenches GT1 and GT2.

[0092] The work function metal layers 132, 134 and / or fill metal layer 136 used within the gate structure 130A may include metal, metal alloy or metal silicide. The formation of the gate structures 130A and 130B may include a plurality of deposition processes to form various gate materials, one or more pad layers and one or more CMP processes to remove excess gate material.

[0093] like FIG. 14B As shown in the cross-sectional view taken along line BB perpendicular to the longitudinal axis of the gate structure 130B, the gate structure 130B includes a work function metal layer 132 in contact with the STI filler material 108 in the STI region 102A. Because in this cross-sectional view, the gate structure 130B does not have a high-k gate dielectric layer, due to... FIGS. 6A-7B This is caused by the high-k dielectric patterning process performed in the steps shown. Therefore, in this cross-sectional view, the bottom surface of the work function metal layer 132 of the gate structure 130A is higher than the bottom surface of the work function metal layer 132 of the gate structure 130B. As... FIG. 14C Another cross-sectional view taken along line CC parallel to the longitudinal axis of gate structure 130B shows that gate structure 130B includes separate high-k gate dielectric layers 120B and work function metal layer 132 has a protrusion that extends through the region between the separate high-k gate dielectric layers 120B to the STI filling material 108 in STI region 102A.

[0094] like FIG. 14CAs shown, the gate structure 130B over the STI region 102A includes a work function metal layer 132 having a non-linear bottom surface. The non-linear bottom surface of the work function metal layer 132 has a lower portion 132L that extends through the gap between the high-k gate dielectric layers 120B to the STI fill material 108. In addition, the non-linear bottom surface of the work function metal layer 132 further includes an upper portion 132U that is in contact with the top surface of the high-k gate dielectric layers 120B. In some embodiments, since the work function metal layers 132 and 134 are formed using a conformal deposition technique, the work function metal layers 134 and the fill metal layer 136 can also exhibit similar non-linear bottom surfaces.

[0095] In some embodiments, the one or more work function metal layers 132, 134 can include a work function metal to provide a suitable work function for the gate structures 130A and 130B. For an n-type FinFET, the one or more work function metal layers 132, 134 can include one or more n-type work function metals (N-metal). The n-type work function metal can illustratively include, but is not limited to, titanium aluminum (TiAl), titanium aluminum nitride (TiAlN), tantalum carbonitride (TaCN), hafnium (Hf), zirconium (Zr), titanium (Ti), tantalum (Ta), aluminum (Al), metal carbides (e.g., hafnium carbide (HfC), zirconium carbide (ZrC), titanium carbide (TiC), aluminum carbide (AlC)), aluminides, and / or other suitable materials. On the other hand, for a p-type FinFET, the one or more work function metal layers 132, 134 can include one or more p-type work function metals (P-metal). The p-type work function metal can illustratively include, but is not limited to, titanium nitride (TiN), tungsten nitride (WN), tungsten (W), ruthenium (Ru), palladium (Pd), platinum (Pt), cobalt (Co), nickel (Ni), conductive metal oxides, and / or other suitable materials. In some embodiments, the fill metal 136 can illustratively include, but is not limited to, tungsten, aluminum, copper, nickel, cobalt, titanium, tantalum, titanium nitride, tantalum nitride, nickel silicide, cobalt silicide, TaC, TaSiN, TaCN, TiAl, TiAlN, or other suitable materials.

[0096] FIGS. 15A-B Top view and cross-sectional view of an intermediate stage in an IC structure fabrication process, in accordance with some illustrative embodiments, are depicted. FIG. 15A and FIG. 15B Top view and cross-sectional view of an intermediate stage in an IC fabrication process, in accordance with some illustrative embodiments, are depicted. FIG. 6A and FIG. 6B Top view and cross-sectional view of an intermediate stage in an IC fabrication process, in accordance with some illustrative embodiments, are depicted. FIG. 15B is a cross-sectional view taken along line B-B in FIG. 15A is a cross-sectional view taken along line B-B inFIG. 15A and FIG. 15B The IC structure shown includes four active regions 202, 204, 206, and 208, defined by STI regions 201, with STI fill material 108 formed in substrate 102. Active regions 202, 204, 206, and 208 extend along the X direction. The IC structure further includes three designated gate regions 212, 214, and 216, extending along the Y direction, which is perpendicular to the X direction. These designated gate regions 212, 214, and 216 are regions where dummy poly gate structures will be formed in subsequent process steps and replaced by metal gate structures (e.g., as shown by metal gate structures 130A or 130B, below). FIGS. 14A-C

[0097] FIG. 15A and FIG. 15B Further shown is high-k dielectric layer 112 formed entirely over substrate 102, and patterned mask P2 formed over high-k dielectric layer 112. The IC structure includes recess 110 in STI fill material 108 at a boundary between STI region 201 and an adjacent active region (e.g., active region 204, as shown), and high-k dielectric layer 112 has a recess 112C within recess 110 of STI fill material 108. Patterned mask P2 has an opening O3 that exposes a region of high-k dielectric layer 112, including recess 112C. FIG. 15B

[0098] As shown from a top view, opening O3 has dimensions X3 and Y3 measured in the X and Y directions, respectively. In some embodiments, the X-direction dimension X3 of mask opening O3 is greater than the X-direction dimension of designated gate region 214 (i.e., the width of poly gate 116A or 116B), but less than the shortest X-direction distance between designated gate regions 212 and 216. Similarly, the Y-direction dimension Y3 of mask opening O3 is greater than the Y-direction dimension of active region 202 or 204, but less than the shortest Y-direction distance between active regions 206 and 208. FIG. 15A By designing mask opening O3 with these particular dimensions, a subsequent patterning process performed on high-k dielectric layer 112 can effectively remove high-k material from recess 110 without adversely affecting the remaining high-k gate dielectric material that serves as a functional gate.

[0099] Further shown are square S3 with a dashed outline, corresponding to the maximum acceptable area of mask opening O3, and square S4 with a dashed outline, corresponding to the minimum acceptable area of mask opening O3. As shown, square S3 is larger than square S4. FIG. 15A FIG. 15A ​​​As shown, the size of square S3 is significantly larger than the size of square S4, which indicates that the mask opening O3 has a wide range of acceptable areas. This wide range relaxes the process window for patterning the high-k dielectric layer 112.

[0100] In FIG. 16A and FIG. 16B , the high-k dielectric layer 112 is patterned in an etching process using the patterned mask P2 as an etching mask, thereby forming an opening O4 extending through the high-k dielectric layer 112 to expose a portion of the STI fill material 108. The etching process removes the recessed portion 112C of the high-k dielectric layer 112 from the recess 110, thereby reducing the risk of electrical leakage from the active region 202 or 204 to a gate structure to be subsequently formed within the designated gate region 214.

[0101] FIGS. 17A-B Top views and cross-sectional views of intermediate stages in an IC structure fabrication process are depicted in accordance with some example embodiments. FIG. 17A and FIG. 17B Top views and cross-sectional views of intermediate stages in an IC fabrication process are depicted similar to those shown in FIG. 6A and FIG. 6B , wherein FIG. 17B is a cross-sectional view taken along line B-B in FIG. 17A . FIG. 17A and FIG. 17B The IC structure shown in FIGS. 14A-C includes four active regions 302, 304, 306, and 308 defined by STI regions 301, wherein the STI fill material 108 is formed in the substrate 102. The active regions 302, 304, and 306 extend along the X direction, and the active region 308 extends along the Y direction, which is perpendicular to the X direction. The IC structure further includes three designated gate regions 312 and 314 extending along the Y direction, and a designated gate region 316 extending along the X direction. These designated gate regions 312, 314, and 316 are regions in which dummy poly-silicon gate structures are to be formed in subsequent process steps and replaced by metal gate structures (e.g., metal gate structures 130A or 130B as shown in

[0102] FIG. 17A and FIG. 17BFurther shown is high-k dielectric layer 112 formed entirely above substrate 102 and patterned mask P3 formed above high-k dielectric layer 112. The IC structure includes recesses, such as recess 110A in STI fill material 108 at the boundary between STI region 301 and active region 306, and recess 110B in STI fill material 108 at the boundary between STI region 301 and active region 306. Recess 110A is adjacent to designated gate region 316, while recess 110B is not adjacent to any designated gate region. High-k dielectric layer 112 has a recess 112C within recess 110A and 110B, respectively.

[0103] Patterned mask P3 has an opening O5 that exposes a region of high-k dielectric layer 112, including recess 112C within recess 110A. In some embodiments, recess 112C within recess 110B is still covered by patterned mask P3, as it is not adjacent to any designated gate region, and therefore does not pose a significant risk of electrical leakage.

[0104] In FIGS. 18A-B and FIGS. 19A-B , high-k dielectric layer 112 undergoes an etching process, using patterned mask P3 as an etching mask. This process forms an opening O6 that extends through high-k dielectric layer 112, exposing a portion of STI fill material 108. The recess 112C of high-k dielectric layer 112 is removed from recess 110A, reducing the risk of electrical leakage from active region 306 to a gate structure that will be subsequently formed in designated gate region 316. In contrast, recess 112C within recess 110B remains intact, as it is not adjacent to any designated gate region, and therefore does not cause electrical leakage.

[0105] FIG. 6A Top views and cross-sectional views of intermediate stages in an IC structure fabrication process are shown, according to some example embodiments. FIG. 6B and FIG. 19B Top views and cross-sectional views of intermediate stages in an IC fabrication process are shown, similar to those shown in FIG. 19A and FIG. 19A , where FIG. 19B is a cross-sectional view taken along line B-B in FIGS. 14A-C . FIG. 19A and FIG. 19BThe illustrated IC structure includes an active region 400 having an irregular pattern defined by STI regions 401 with STI fill material 108 formed in the substrate 102. The active region 400 includes a first active region 402 extending along the X direction and a second active region 404 protruding from a longitudinal side of the first active region 402 when viewed from above. The second active region 404 extends along the X direction and has a length less than the first active region 402. Thus, opposite side surfaces of the second active region 404 are disposed behind the opposite side surfaces of the first active region 402, respectively. The IC structure further includes three designated gate regions 412, 414, and 416 extending along the Y direction. These designated gate regions 412, 414, and 416 are regions where dummy poly gate structures will be formed in subsequent processing steps and replaced by metal gate structures (e.g., as shown by metal gate structures 130A or 130B). FIGS. 20A-B The illustrated metal gate structures 130A or 130B).

[0106] FIG. 6A and FIG. 6B Further shown is a high-k dielectric layer 112 formed entirely above the substrate 102, and a patterned mask P4 formed above the high-k dielectric layer 112. The IC structure includes a recess, such as recess 110 in the STI fill material 108 at the boundary between the STI region 401 and the second active region 404. The recess 110 is adjacent to the designated gate region 412, and the high-k dielectric layer 112 has a recessed portion 112C within the recess 110. The patterned mask P4 has an opening O7 that exposes a region of the high-k dielectric layer 112, including the recessed portion 112C within the recess 110.

[0107] In FIG. 19B and FIG. 19A FIG. 19A FIG. 19B FIGS. 14A-C FIG. 19A FIG. 19B , the high-k dielectric layer 112 is patterned in an etching process using the patterned mask P4 as an etching mask, thereby forming an opening O8 extending through the high-k dielectric layer 112 to expose a portion of the STI fill material 108. The etching process removes the recessed portion 112C of the high-k dielectric layer 112 from the recess 110, thereby reducing the risk of a leakage path from the second active region 404 to a gate structure to be subsequently formed within the designated gate region 412.

[0108] Based on the above discussion, it can be seen that the present disclosure provides advantages in various embodiments. However, it should be understood that other embodiments can provide additional advantages, not all of which necessarily need to be disclosed herein, and not all embodiments require a particular advantage. One advantage is that there is no or only negligible high-k dielectric layer residue in the recess in the STI region. Another advantage is that the risk of a leakage path from the active region to a gate structure on the STI region can be mitigated due to the reduced high-k dielectric layer residue in the recess in the STI region.

[0109] In some embodiments, a method includes the steps of forming a trench in a semiconductor substrate; filling the trench with a trench fill material having a recessed region recessed from a top surface of the trench fill material; depositing a high-k dielectric layer over the semiconductor substrate and the trench fill material; removing a first portion of the high-k dielectric layer from the recessed region of the trench fill material while leaving a second portion of the high-k dielectric layer over the semiconductor substrate; and forming a gate structure over the second portion of the high-k dielectric layer. In some embodiments, the method further includes the step of forming gate spacers at opposing sidewalls of the gate structure after removing the first portion of the high-k dielectric layer. In some embodiments, the gate spacers are formed over the second portion of the high-k dielectric layer. In some embodiments, the method further includes the step of removing a portion of the second portion of the high-k dielectric layer not covered by the gate structure and the gate spacers. In some embodiments, the method further includes the step of forming source / drain epitaxial structures on the semiconductor substrate after removing the first portion of the high-k dielectric layer. In some embodiments, the gate structure includes a polysilicon structure, and the method further includes the step of replacing the polysilicon structure with a metal structure. In some embodiments, the method further includes the step of forming a patterned mask over the second portion of the high-k dielectric layer before removing the first portion of the high-k dielectric layer, while exposing the first portion of the high-k dielectric layer. The first portion of the high-k dielectric layer is etched through the patterned mask as an etch mask. In some embodiments, the method further includes the step of removing the patterned mask after forming the gate structure.

[0110] In some embodiments, a method includes the steps of forming an isolation region adjacent to an active region in a substrate, the isolation region having a recessed region disposed rearward from a top surface of the isolation region; forming a high-k dielectric layer over the active region but not over the recessed region of the isolation region; forming a gate structure over the high-k dielectric layer; and forming gate spacers at opposing sidewalls of the gate structure and over the high-k dielectric layer. In some embodiments, the step of forming the high-k dielectric layer includes the steps of depositing the high-k dielectric layer over the isolation region and the active region, and etching the high-k dielectric layer to remove a portion of the high-k dielectric layer from the recessed region of the isolation region. In some embodiments, the portion of the high-k dielectric layer is in contact with sidewalls of the active region. In some embodiments, the high-k dielectric layer is etched through a patterned photoresist as an etch mask. In some embodiments, the recessed region of the isolation region is adjacent to the active region. In some embodiments, the method further includes the step of patterning the high-k dielectric layer into a gate dielectric layer through the gate spacers and the gate structure as etch masks. In some embodiments, the method further includes the step of replacing the gate structure with a metal gate structure after patterning the high-k dielectric layer into the gate dielectric layer.

[0111] In some embodiments, an IC structure includes an STI region, a first gate structure, and a second gate structure. The STI region is adjacent to an active region in a semiconductor substrate. The first gate structure is located over the active region. The first gate structure includes a high-k gate dielectric layer and a gate metal layer located over the high-k gate dielectric layer. The second gate structure is located over the STI region. In a cross-sectional view taken in a first direction perpendicular to a longitudinal axis of the second gate structure, the second gate structure includes the gate metal layer in contact with the STI region. In some embodiments, in the cross-sectional view, the second gate structure does not have a high-k gate dielectric layer. In some embodiments, in the cross-sectional view, a bottom surface of the gate metal layer of the first gate structure is higher than a bottom surface of the gate metal layer of the second gate structure. In some embodiments, in a cross-sectional view taken in a second direction parallel to the longitudinal axis of the second gate structure, the second gate structure includes separate high-k gate dielectric layers, and a protruding portion of the gate metal layer extends through a region between the high-k gate dielectric layers to the STI region. In some embodiments, the gate metal layer of the second gate structure forms a horizontal interface with the shallow trench isolation region.

[0112] In some embodiments, an IC structure includes a shallow trench isolation region adjacent to an active region in a semiconductor substrate; a first gate structure located over the active region, the first gate structure including a high-k gate dielectric layer and a gate metal layer located over the high-k gate dielectric layer; and a second gate structure located over the shallow trench isolation region, wherein in a cross-sectional view taken in a first direction perpendicular to a longitudinal axis of the second gate structure, the second gate structure does not include a high-k gate dielectric layer. In some embodiments, the second gate structure includes a work function metal layer in contact with the shallow trench isolation region. In some embodiments, in a cross-sectional view taken in a second direction parallel to the longitudinal axis of the second gate structure, the second gate structure includes multiple separate high-k gate dielectric layers.

[0113] In some embodiments, an IC structure includes a shallow trench isolation region adjacent to an active region in a semiconductor substrate; a first gate structure located over the active region, the first gate structure including a high-k gate dielectric layer and a gate metal layer located over the high-k gate dielectric layer; and a second gate structure located over the shallow trench isolation region, wherein in a cross-sectional view taken in a first direction perpendicular to a longitudinal axis of the second gate structure, the second gate structure includes a work function metal layer located over the shallow trench isolation region, the work function metal layer being separated from a recess on the shallow trench isolation region. In some embodiments, the recess is adjacent to a source / drain epitaxial structure on the active region. In some embodiments, the recess is adjacent to a gate spacer located beside the second gate structure.

[0114] The foregoing overview of features of several embodiments enables a person of ordinary skill in the art to better understand the various aspects of the disclosure. The skilled person will understand that the disclosure can readily be used as a basis for designing or modifying other processes and structures for carrying out the same purposes and / or achieving the same advantages as the embodiments introduced herein. The skilled person will also recognize that these equivalent constructions do not depart from the spirit and scope of the disclosure, and that they can be made and used without departing from the spirit and scope of the disclosure.

Claims

1. An integrated circuit structure, characterized by An integrated circuit structure comprising: a shallow trench isolation region adjacent to an active region in a semiconductor substrate; a first gate structure over the active region, the first gate structure comprising a high-k gate dielectric layer and a gate metal layer over the high-k gate dielectric layer; and a second gate structure over the shallow trench isolation region, wherein in a cross-sectional view taken in a first direction perpendicular to a longitudinal axis of the second gate structure, the second gate structure comprises a gate metal layer in contact with the shallow trench isolation region.

2. The integrated circuit structure of claim 1, wherein in the cross-sectional view, the gate metal layer of the second gate structure forms a horizontal interface with the shallow trench isolation region.

3. The integrated circuit structure of claim 1, wherein in the cross-sectional view, a bottom surface of the gate metal layer of the first gate structure is higher than a bottom surface of the gate metal layer of the second gate structure.

4. The integrated circuit structure of claim 1, wherein in a cross-sectional view taken in a second direction parallel to the longitudinal axis of the second gate structure, the second gate structure comprises a plurality of separate high-k gate dielectric layers, and a protruding portion of the gate metal layer extends through a region between the plurality of separate high-k gate dielectric layers to the shallow trench isolation region.

5. An integrated circuit structure, characterized by An integrated circuit structure comprising: a shallow trench isolation region adjacent to an active region in a semiconductor substrate; a first gate structure over the active region, the first gate structure comprising a high-k gate dielectric layer and a gate metal layer over the high-k gate dielectric layer; and a second gate structure over the shallow trench isolation region, wherein in a cross-sectional view taken in a first direction perpendicular to a longitudinal axis of the second gate structure, the second gate structure comprises a work function metal layer in contact with the shallow trench isolation region.

6. The integrated circuit structure of claim 5, wherein the work function metal layer forms a horizontal interface with the shallow trench isolation region.

7. The integrated circuit structure of claim 5, wherein in a cross-sectional view taken in a second direction parallel to the longitudinal axis of the second gate structure, the second gate structure comprises a plurality of separate high-k gate dielectric layers.

8. An integrated circuit structure, characterized by An integrated circuit structure comprising: a shallow trench isolation region adjacent to an active region in a semiconductor substrate; a first gate structure over the active region, the first gate structure comprising a high-k gate dielectric layer and a gate metal layer over the high-k gate dielectric layer; and a second gate structure over the shallow trench isolation region, wherein in a cross-sectional view taken in a first direction perpendicular to a longitudinal axis of the second gate structure, the second gate structure comprises a work function metal layer over the shallow trench isolation region, the work function metal layer separated from a recess in the shallow trench isolation region.

9. The integrated circuit structure of claim 8, wherein the recess is adjacent to a source / drain epitaxial structure on the active region.

10. The integrated circuit structure of claim 8, wherein the recess is adjacent to a gate spacer located beside the second gate structure.

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