Chip packaging structure
By using pin array distribution and bump support design in the chip packaging structure, the problems of chip soldering stability and functional integration are solved, enabling the loading of larger area chips and the integration of more functional pins.
Patent Information
- Application Number
- CN202423276528.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-30
- Publication Date
- 2025-12-19
- Estimated Expiration
- 2034-12-30
AI Technical Summary
In the prior art, the chip packaging structure with lead frame design has poor chip soldering stability and low functional integration during packaging. The functional integration of the chip still needs to be improved, and the soldering stability during packaging is poor.
A chip packaging structure is adopted, which arranges multiple pins of the packaging structure in an array to accommodate a larger chip area, while increasing the number of functional pins. The wire bonding support for the chip solder joints is formed by multiple protrusions on the frame, thereby improving the soldering stability.
This enables the loading of larger area chips and the integration of more functional pins, improves chip soldering stability, and enhances the performance integration of the product.
Smart Images
Figure CN223693128U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The utility model relates to integrated circuit packaging field, specifically, relate to a chip packaging structure. BACKGROUND
[0002] In the integrated circuit packaging process, in the limited product board space, load larger size chip, realize more function pin input and output, is the continuous pursuit of integrated circuit design development.
[0003] The traditional lead frame is loaded with chips through die paddle, and then is welded to the pin to realize the function Pad input and output, which limits the integrated design and function integration of the chip. And COL (Chip on lead) packaging structure cancels the traditional die paddle design, uses the pin as both the pin function input and output and the chip carrier, saves the partition space between die paddle and lead, effectively improves the chip area ratio of the built-in product, and becomes the preferred choice for pursuing small integrated circuit to realize better performance.
[0004] However, the function integration of the existing COL packaging structure still needs to be improved, and the welding stability of the chip during packaging is poor. UTILITY MODEL CONTENTS
[0005] The utility model discloses a kind of chip packaging structures, it is distributed by array to the multiple pins of packaging structure, so that it can load larger area chip, simultaneously, more function pins than traditional design product, more product performance integration can be realized;And the wire bonding support of the multiple protruding parts on frame forms chip welding point, so that welding is more stable.
[0006] To solve the above technical problems, the technical scheme adopted by the utility model is as follows:
[0007] A kind of chip packaging structure, including chip, plastic package, frame, the frame has multiple pins distributed by array on it,
[0008] The chip is attached to the upper surface of the frame, and the welding points of the chip are respectively welded to the corresponding pins by bonding wires.
[0009] Multiple protruding parts are provided on the frame, and the protruding parts are provided corresponding to the multiple welding points of the chip to provide welding support for the multiple welding points.
[0010] The plastic package covers the chip, the bonding wire and the frame, and exposes the multiple pins to the lower surface of the plastic package.
[0011] Further, in the utility model, the frame is provided with an integral hollow region;
[0012] The protruding part extends along the inside of the hollow region;
[0013] The frame is further provided with a concave part corresponding to each protruding part, the concave part extends along the outside of the hollow region, so that the hollow region between the protruding part and the concave part maintains a preset interval.
[0014] Further, in the utility model, the plurality of pins are separated by the hollow region into at least one of a single pin, two integrally connected pins or three integrally connected pins.
[0015] Further, in the utility model, the plurality of pins are arranged in a 4x4 rectangular array.
[0016] Further, in the utility model, the frame is provided with a filling hole at the four corners for filling plastic sealing material.
[0017] Further, in the utility model, the frame is provided with a filling hole at the four corners for filling plastic sealing material.
[0018] Further, in the utility model, the frame is provided with a filling hole at the four corners for filling plastic sealing material.
[0019] Further, in the utility model, the chip edge and the pin edge located at the array periphery have a wire bonding distance of 0.2mm-0.286mm.
[0020] Further, in the utility model, the lower surface of the frame avoids the area of the plurality of pins, which is a half-etching area, the half-etching area is filled with plastic sealing material, so that the plurality of pins are exposed to the lower surface of the plastic sealing body.
[0021] Further, in the utility model, the frame and the pin top surface are provided with an electroplated layer.
[0022] The utility model has at least the following advantages or beneficial effects:
[0023] The packaging structure of the utility model discloses a plurality of pins of array distribution are set up in the frame, the chip is directly pasted on the surface of the frame, makes a plurality of pins of array distribution can be used as functional pin input and output, can be used as the support carrier of chip, can promote the chip area proportion, can load greater chip size, and the pin of array distribution can be more functional I / O pin number compared with the traditional design product, thereby realizing more product performance integration, a plurality of convex parts corresponding with the chip welding point are set up in the frame, can provide the wire bonding support for the plurality of welding points of chip, avoids the welding instability caused by the wire bonding of suspension when welding. BRIEF DESCRIPTION OF DRAWINGS
[0024] In order to more clearly illustrate the technical scheme in the embodiment of the utility model, the following will briefly introduce the drawing needed to be used in the embodiment, it should be understood that the following drawing only shows some embodiments of the utility model, therefore should not be regarded as the limitation to the scope, for ordinary skilled person in the art, under the premise of not paying the creative labor, can also obtain other related drawings according to these drawings.
[0025] Figure 1 The overall section schematic view of the chip packaging structure provided for the application embodiment is provided;
[0026] Figure 2 The bottom surface schematic view of the array pin frame provided for the application embodiment is provided;
[0027] Figure 3 The bonding wire bonding schematic view when the chip is placed in the pin frame provided for the application embodiment is provided;
[0028] Figure 4 The top surface schematic view of the array pin and the frame provided for the application embodiment is provided.
[0029] Icon: 10-chip, 20-bonding wire, 30-plastic package, 40-pin, 50-frame, 51-hollow area, 52-convex part, 53-recess, 54-filling hole, 55-half etching area, 55-electroplating layer, 56-double connection strip, 60-film piece. DETAILED DESCRIPTION
[0030] In order to make the purpose, technical scheme and advantage of the embodiment of the utility model more clear, the following will combine the drawing in the embodiment of the utility model, and the technical scheme in the embodiment of the utility model is clearly and completely described, obviously, the described embodiment is a part of the embodiment of the utility model, instead of all the embodiments. The components of the embodiment of the utility model described and shown in the drawing here can be arranged and designed in various different configurations.
[0031] Therefore, the following detailed description of the embodiments of the utility model provided in the drawings is not intended to limit the scope of the claimed utility model, but only represents selected embodiments of the utility model. Based on the embodiments in the utility model, all other embodiments obtained by those of ordinary skill in the art without creative labor fall within the scope of the utility model protection. Embodiments
[0032] Please refer to Figures 1-4 , it is the structure schematic view of the chip packaging structure in the utility model embodiment shown in the figure;
[0033] The embodiment provides a kind of chip 10 packaging structure, including chip 10, plastic package 30, frame 50, the frame 50 has multiple pins 40 in array distribution on it,
[0034] Chip 10 is attached to the upper surface of frame 50, and the solder joints of chip 10 are respectively welded with corresponding pin 40 by bonding wire 20;
[0035] Multiple protruding parts 52 are provided on frame 50, and the multiple solder joints of chip 10 are provided with protruding parts 52 to provide soldering support for multiple solder joints;
[0036] Plastic package 30 is covered on chip 10, bonding wire 20 and frame 50, and multiple pins 40 are exposed to the lower surface of plastic package 30.
[0037] Below, a kind of chip packaging structure of the present exemplary embodiment will be further described.
[0038] In some embodiments of the present application, refer to Figure 1 In the above packaging structure, chip 10 is directly attached to the upper surface of frame 50 by adhesive film 60, frame 50 is provided with multiple pins 40 in array distribution, and the solder joints of chip 10 are respectively welded with corresponding pin 40 by multiple bonding wires 20;Multiple pins 40 can not only be used as functional pins input and output, but also be used as the support carrier of chip 10, so as to improve the area ratio of chip 10, and larger chip 10 size can be loaded.
[0039] Refer to Figure 2 In the embodiment, multiple pins 40 in array distribution on frame 50 are more than traditional design products in the number of functional I / O pins, so that more product performance integration can be realized, and more functional integrated PMIC products can be developed.
[0040] In the embodiment, the plastic package 30 covers the chip 10, the bonding wire 20 and the frame 50, and the plurality of pins 40 are exposed in a cylindrical shape at the lower surface of the plastic package 30, facilitating electrical connection. In other embodiments, the pins 40 can also be of other shapes, which are specifically designed according to the packaging appearance requirements of the product.
[0041] In some embodiments of the present application, reference is made to Figure 3 The frame 50 is provided with a plurality of protrusions 52 corresponding to the plurality of soldering points of the chip, so as to provide soldering support for the plurality of soldering points. That is, the protrusions 52 are arranged at positions corresponding to the wire-bonding positions of the chip 10, and support can be provided below the soldering points through the protrusions 52, so as to avoid completely suspended wire-bonding, which may cause unstable soldering and abnormal bonding caused by suspended wire-bonding. It should be noted that, considering the stability of the frame 50 and the strength of the pins 40, the protrusions 52 do not correspond to each soldering point, or in other words, the plurality of protrusions 52 correspond to a plurality of soldering points of the chip 10, which refers to a part of the soldering points. Generally, the protrusions 52 are designed below some edge soldering points of the chip 10, and are arranged at corresponding intervals along the edges, so as to support the positions of the chip 10 where the soldering points are concentrated as much as possible, as shown in the part enclosed by the rectangular frame below the edge of the chip 10 in Figure 3 .
[0042] As a preferred embodiment, the frame 50 is provided with an integrally formed hollow region 51. By arranging the hollow region 51, the combination of the frame 50 and the pins 40 can be strengthened during plastic packaging, avoiding the risk of delamination. The protrusions 52 extend along the inside of the hollow region 51, and the frame 50 is further provided with a plurality of recesses 53 corresponding to the plurality of protrusions 52 one by one, and the recesses 53 extend along the outside of the hollow region, so as to maintain a predetermined distance between the protrusions 52 and the recesses 53. For example, the depth of the recesses 53 is the same as the depth of the protrusions 52, so as to ensure that the distance between the hollow regions 51 of the frame 50 is consistent, thereby enhancing the stability.
[0043] As a preferred embodiment, the plurality of pins 40 are separated by the hollow region 51 into at least one of a single pin 40, two integrally connected pins 40 or three integrally connected pins 40. Specifically, as shown in Figure 2 , the plurality of pins 40 can be separated by the hollow region 51 into a combination of a single interval, two adjacent pins and three adjacent pins, that is, a universal functional pin with one-point output, two-point output and three-point output, and the specific separation mode can be designed according to the packaging appearance requirements (POD) of the product.
[0044] As a preferred embodiment, the plurality of pins 40 is arranged in a 4*4 rectangular array, so that the packaging structure can have 16 functional I / O pins, greatly increasing the product performance integration.
[0045] As a preferred embodiment, referring to Figure 2 The four corners of the frame 50 are provided with filling holes 54. During plastic packaging, the filling holes 54 can be filled with plastic packaging material to strengthen the combination of the plastic packaging material and the frame 50, and further avoid the risk of delamination. The filling hole 54 is preferably irregularly shaped as shown, which is beneficial to the filling of the plastic packaging material, and can also be other regular or irregular shapes.
[0046] As a preferred embodiment, double connecting strips 56 are arranged on both sides of the filling hole on the frame 50 to strengthen the support strength of the pins 40.
[0047] As a preferred embodiment, the distance between the center points of the two adjacent pins 40 is 0.4mm±0.025mm, which ensures the number of multifunctional I / O pins while improving the compactness and integration of the product structure.
[0048] As a preferred embodiment, the chip 10 edge and the pin 40 edge located at the array periphery have a wire bonding distance of 0.2mm-0.286mm. Through the array distribution of the plurality of pins 40, the wire bonding distance from the chip 10 edge to the pin 40 edge is reduced. It should be noted that during wire bonding, the space requirement of the solder joint can be reduced by reverse bonding to adapt to the reduction of data, and ultra-low wire bonding arc across the chip 10 can be achieved.
[0049] As a preferred embodiment, referring to Figure 2 The lower surface of the frame 50 avoids the area of the plurality of pins 40, which is a half-etching area 55 filled with plastic packaging material to expose the plurality of pins 40 to the lower surface of the plastic packaging body 30. Specifically, the copper material on the back of the frame 50 that does not need to be exposed is half-etched to form several pits for filling the plastic packaging material, and only the array pins 40 that need to be exposed can be exposed. Good flatness control and strength enhancement of the frame 50 can be achieved to avoid the risk of plastic packaging overflow.
[0050] As a preferred embodiment, referring to Figure 4 The frame 50 and the pin 40 top surface are provided with an electroplated layer 55, and the range of the electroplated layer 55 can be only in the area range of the array pin 40. Through electroplating, a layer of metal plating layer easy to solder can be formed on the surface of the frame 50, which enhances the connection ability between the frame 50 and the bonding wire 20, and at the same time has good conductivity.
[0051] The embodiments of the present application have the following beneficial effects:
[0052] By directly attaching the chip 10 on the array distributed pin frame, the chip can be supported by the pins, thereby increasing the area ratio of the chip 10, and the array distribution of the plurality of pins 40 is designed, so that the number of functional I / O pins is more than that of the traditional design product, and multi-functional integration is realized.
[0053] The protruding parts 52 on the frame 50 form special-shaped wire bonding supports, the protruding parts 52 provide support under the solder joints of the chip 10, avoid completely suspended wire bonding, cause unstable welding, and reduce the bonding abnormality caused by suspended wire bonding as much as possible.
[0054] Through the connection support of the frame 50 and the etching of the back surface of the frame 50, good flatness and strength of the frame 50 can be achieved, and the risks of extension deformation and overflow of the pins 40 can be avoided.
[0055] The above is only a preferred embodiment of the utility model, and is not used for limiting the utility model. For those skilled in the art, the utility model can have various changes and changes. Any modification, equivalent replacement, improvement, etc. within the spirit and principles of the utility model should be included in the protection scope of the utility model.
Claims
1. A chip package structure, characterized by, The chip, the plastic package, and the frame with a plurality of pins arranged in an array, The chip is attached to the upper surface of the frame, and the solder joints of the chip are respectively welded to the corresponding pins by the bonding wires; A plurality of protrusions are arranged on the frame, corresponding to the plurality of solder joints of the chip, for providing welding support for the plurality of solder joints; The plastic package covers the chip, the bonding wires, and the frame, and exposes the plurality of pins on the lower surface of the plastic package.
2. The chip package structure of claim 1, wherein, The frame is provided with an integrally formed hollow area; The protrusions extend along the inside of the hollow area; The frame is further provided with a plurality of recesses corresponding to the plurality of protrusions, which extend along the outside of the hollow area, so that the hollow area between the protrusions and the recesses maintains a predetermined distance.
3. The chip package structure of claim 2, wherein, The plurality of pins are separated by the hollow area into at least one of a single pin, two integrally connected pins, or three integrally connected pins.
4. The chip package structure of any one of claims 1-3, wherein, The plurality of pins are arranged in a 4x4 rectangular array.
5. The chip package structure of claim 1, wherein, Fill holes are provided at the corners of the frame for filling plastic packaging material.
6. The chip package structure of claim 5, wherein, Double connection strips are provided on both sides of the fill holes on the frame to strengthen the pin support strength.
7. The chip package structure of claim 1 or 2, wherein, The distance between the centers of two adjacent pins is 0.4mm±0.025mm.
8. The chip package structure of claim 1 or 2, wherein, The chip edge and the pin edge located at the array periphery have a wire bonding distance of 0.2mm-0.286mm.
9. The chip package structure of claim 1, wherein, The lower surface of the frame avoids the area of the plurality of pins, which is a half-etched area filled with plastic packaging material to expose the plurality of pins on the lower surface of the plastic package.
10. The chip package structure of claim 1, wherein, The frame and the plurality of pins are provided with an electroplated layer.