Package structure of redistribution layer structure with recessed portion and semiconductor package

Abstract

The utility model provides a packaging structure of a redistribution layer structure with a recessed part and a semiconductor package. The package structure includes: a front-side redistribution layer (RDL) structure including a recessed portion; a lower package layer on the front side RDL structure and including a plurality of vias configured to electrically couple the front side RDL structure to the upper package; a first semiconductor die on the front side RDL structure and in the lower package layer, and an integrated passive device (IPD) connected to the front side RDL structure in the recessed portion and electrically coupled to the first semiconductor die. According to the utility model, the size of the primer prohibition area can be reduced.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to a packaging structure and a semiconductor package. BACKGROUND

[0002] The packaging structure can include an integrated passive device (IPD). An IPD is an electronic device that can include one or more passive devices, such as resistors, capacitors, and inductors. IPDs can be designed to provide important passive functions in electronic circuits while occupying a small footprint, reducing parasitic effects, and improving overall performance. IPDs can be used universally in various semiconductor packages and integrated circuits to simplify design, save space, and enhance circuit performance. SUMMARY

[0003] Embodiments of the present application provide a packaging structure, comprising: a front side redistribution layer structure including a recessed portion; a lower encapsulant layer on the front side redistribution layer structure and including a plurality of vias configured to electrically couple the front side redistribution layer structure to an upper package; a first semiconductor die on the front side redistribution layer structure and in the lower encapsulant layer; and an integrated passive device connected to the front side redistribution layer structure in the recessed portion and electrically coupled to the first semiconductor die.

[0004] Embodiments of the present application provide a semiconductor package, comprising: a package substrate; a semiconductor device including a packaging structure on the package substrate, the packaging structure including: a front side redistribution layer structure including a recessed portion; a lower encapsulant layer on the front side redistribution layer structure and including a plurality of vias configured to electrically couple the front side redistribution layer structure to an upper package; a first semiconductor die on the front side redistribution layer structure and in the lower encapsulant layer; and an integrated passive device attached to the front side redistribution layer structure in the recessed portion and electrically coupled to the first semiconductor die; and a package underfill layer between the package substrate and the semiconductor device. BRIEF DESCRIPTION OF DRAWINGS

[0005] The nature of the application content will be best understood from the following detailed description when considered in connection with the accompanying drawings. It should be noted that the various features are not drawn to scale. In fact, the dimensions of the various features can be arbitrarily increased or decreased for clarity of discussion.

[0006] FIG. 1A is a vertical cross-sectional view of a packaging structure according to various embodiments.

[0007] FIG. 1B is a bottom-up plan view of a board side surface of a front side RDL structure in a packaging structure according to one or more embodiments. is a vertical cross-sectional view of a packaging structure according to various embodiments.

[0007] FIG. 1B is a bottom-up plan view of a board side surface of a front side RDL structure in a packaging structure according to one or more embodiments.

[0008] FIG. 1C is a detailed vertical cross-sectional view of a front-side RDL structure according to one or more embodiments.

[0009] FIG. 1D is a detailed vertical cross-sectional view of a recessed portion in a front-side RDL structure according to one or more embodiments.

[0010] FIG. 2A is a vertical cross-sectional view of an intermediate structure including a seed layer on an adhesive layer according to one or more embodiments.

[0011] FIG. 2B is a vertical cross-sectional view of an intermediate structure including a photoresist layer according to one or more embodiments.

[0012] FIG. 2C is a vertical cross-sectional view of an intermediate structure including a via according to one or more embodiments.

[0013] FIG. 2D is a vertical cross-sectional view of an intermediate structure including a via according to one or more embodiments.

[0014] FIG. 2E is a vertical cross-sectional view of an intermediate structure including a first semiconductor die according to one or more embodiments.

[0015] FIG. 2F is a vertical cross-sectional view of an intermediate structure including a lower encapsulation layer according to one or more embodiments.

[0016] FIG. 2G is a vertical cross-sectional view of an intermediate structure including a lower encapsulation layer after a planarization process according to one or more embodiments.

[0017] FIG. 2H is a vertical cross-sectional view of an intermediate structure including a front-side RDL structure according to one or more embodiments.

[0018] FIG. 2I is a vertical cross-sectional view of an intermediate structure including a UBM layer according to one or more embodiments.

[0019] FIG. 2J is a vertical cross-sectional view of an intermediate structure including an IPD according to one or more embodiments.

[0020] FIG. 2K is a vertical cross-sectional view of an intermediate structure including a solder ball according to one or more embodiments.

[0021] FIG. 3 is a flow diagram showing a method of forming a package structure according to one or more embodiments.

[0022] FIG. 4 It is a vertical cross-sectional view of a semiconductor device including an upper package located on a package structure, according to one or more embodiments.

[0023] FIG. 5 This is a vertical cross-sectional view of a semiconductor package containing a semiconductor device on a package substrate according to one or more embodiments.

[0024] FIG. 6 It is a vertical cross-sectional view of a semiconductor device according to one or more embodiments.

[0025] FIG. 7 This is a detailed vertical cross-sectional view of a first alternative design of the front RDL structure according to one or more embodiments.

[0026] FIG. 8 This is a detailed vertical cross-sectional view of a second alternative design for the front RDL structure according to one or more embodiments. Detailed Implementation

[0027] The following utility model description provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and configurations are described below to simplify the utility model description. Of course, these specific examples are merely illustrative and not intended to be limiting. For example, in the following description, the formation of a first feature on or over a second feature may include embodiments where the first and second features are in direct contact, and may also include embodiments where an additional feature is formed between the first and second features so that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances of the utility model description. This repetition is for simplicity and clarity and does not in itself define the relationship between the various embodiments and / or configurations discussed.

[0028] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” “upper,” and similar terms may be used to describe the relationship between one component or feature and another, as shown in the figures. In addition to the orientations depicted in the figures, spatial relative terms are also intended to cover different orientations of components in use or operation. Devices may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein shall be interpreted accordingly.

[0029] IPDs can be used in semiconductor packages to achieve a number of different purposes. For example, by integrating multiple passive devices into a single package, IPDs can minimize valuable circuit board space and reduce the overall size of electronic devices. This is particularly advantageous for modern electronic devices where size constraints are critical, such as smartphones, wearables, and Internet of Things (IoT) devices.

[0030] IPDs can include capacitors and inductors for filtering and signal conditioning. IPDs can also be used to suppress noise, eliminate unwanted frequencies, and shape signal waveforms in various applications, including wireless communication devices and radio frequency (RF) circuits. IPDs can also be used in RF and wireless communication applications to establish impedance matching networks. Such impedance matching networks can help ensure that the input and output impedances of a circuit are matched to optimize power transfer and signal integrity.

[0031] IPDs can also be used for direct current (DC) biasing and alternating current (AC) coupling in various circuits. IPDs can combine DC capacitors and DC bias resistors into a single package, thereby reducing the number of discrete devices required and simplifying circuit layout. IPDs can integrate resistors and capacitors used in voltage divider networks for power management circuits, including power distribution, voltage sensing, and level shifting. IPDs can also be used in timing circuits and oscillators to generate stable clock signals and timing references; in microelectromechanical systems (MEMS) and sensor applications for calibration, signal conditioning, and sensor device interfacing; and in advanced semiconductor packages to enhance signal integrity, minimize parasitic effects, and reduce the need for external devices.

[0032] Generally, the package structure can connect the IPD to a board side surface of a redistribution layer (RDL) structure. In some cases, the IPD can be electrically coupled to a second RDL layer (RDL2) that can be redundant as a ground dummy mesh. The IPD can be formed adjacent to solder balls of a ball grid array (BGA) on the board side surface of the RDL structure. The solder balls can have a height (e.g., a distance from the board side surface) sufficient to provide a gap between the IPD and a package substrate (e.g., a board) on which the package structure is mounted.

[0033] At least one embodiment disclosed herein can include a package structure in which an IPD is attached to an RDL structure in a recessed portion of the RDL structure. In at least one embodiment disclosed herein, the IPD can be formed at least partially within or attached within the recessed portion. The IPD can include, for example, a zero inductance IPD (ZL IPD). The package structure can include, for example, a layer stack package structure. In at least one embodiment, the package structure can include an application processor (AP) device.

[0034] By attaching the IPD to the RDL structure in the recessed portion, the package structure can reduce a height of the solder balls of the BGA. This can allow the embodiment package structure to have a thicker semiconductor die compared to other package structures.

[0035] Further, an IPD underfill layer can be formed in the recessed portion and around at least a portion of the IPD. Attaching the IPD in the recessed portion can reduce a spreading distance of the underfill material along the board side surface of the RDL structure. Thus, attaching the IPD in the recessed portion can help to reduce a size of an underfill keep-out zone (KOZ) compared to other package structures. This can allow ball grid array (BGA) input / output (I / O) solder balls to be formed closer to the IPD, allowing an increase in the ball grid array (BGA) input / output (I / O) count.

[0036] In at least one embodiment, a height of the IPD can be reduced to 79 pm or less, which can be at least 15 pm less than a height of an IPD in a conventional package structure (e.g., 94 pm). In at least one embodiment, a height of the solder balls can be reduced to 111 pm or less, which can be at least 15 pm less than a height of the solder balls in a conventional package structure (e.g., 126 pm).

[0037] In at least one embodiment, the package structure can include an under bump metal (UBM) dam structure (e.g., a metal dam structure) on the board side surface of the RDL structure. The UBM dam structure can help to contain and / or prevent spreading of the IPD underfill layer along the board side surface of the RDL structure. In at least one embodiment, the package structure can also include a barrier ring (e.g., an RDL3 barrier ring) in the recessed portion. The barrier ring can be used to contain and / or prevent spreading of the IPD underfill layer along a bottom surface of the recessed portion. In at least one embodiment, the barrier ring can be omitted. The UBM dam structure can be included in both cases, including the RDL3 barrier ring and not including the RDL3 barrier ring. In both cases, a size of an underfill keep-out zone (KOZ) can be reduced and a BGA I / O count can be increased.

[0038] FIG. 1Ais a vertical cross-sectional view of a package structure according to various embodiments. FIG. 1B is a bottom-up plan view of a board-side surface of a front-side RDL structure 110 in a package structure 100 according to one or more embodiments. FIG. 1A is a detailed vertical cross-sectional view of a portion of a front-side RDL structure according to one or more embodiments. FIG. 1B is a cross-sectional view along line A-A' in FIG. 1C is a detailed vertical cross-sectional view of a recessed portion R FIG. 1D in a front-side RDL structure according to one or more embodiments. 110

[0039] It should be noted that embodiments are not limited to any particular package structure configuration or "layer stack package" configuration. It should also be noted that the terms "proximal" and "distal" can sometimes be used to describe devices of the package structure 100. These terms are with reference to a center portion (e.g., vertical direction) of the package structure 100 in the z-direction (direction z). Thus, for example, a "proximal" side of a redistribution layer can refer to a side of the redistribution layer that is closest to the center portion in the z-direction, and a "distal" side of the redistribution layer can refer to a side of the redistribution layer that is farthest from the center portion in the z-direction.

[0040] As shown in FIG. 1A , the package structure 100 can include a front-side RDL structure 110 and a molded portion 115 on the front-side RDL structure 110. The molded portion 115 can include a first semiconductor die 120 attached to the front-side RDL structure 110. The front-side RDL structure 110 can include a recessed portion R 110 . An integrated passive device (IPD) 500 can be attached to the front-side RDL structure 110 in the recessed portion R 110 .

[0041] In at least one embodiment, the front-side RDL structure 110 can include an alternating stack of a plurality of dielectric layers 114 and a plurality of redistribution layers 113. The present disclosure does not limit the number of dielectric layers 114 and the number of redistribution layers 113 in the front-side RDL structure 110 in any way. Although FIG. 1A four dielectric layers 114 and four redistribution layers 113 are depicted, a greater or lesser number of dielectric layers and redistribution layers can be used.

[0042] ​In at least one embodiment, the dielectric layers 114 can include a dielectric material such as polyimide (PI), epoxy, acrylic, phenolic, benzocyclobutene (BCB), polybenzoxazole (PBO), or any other suitable polymeric class. In some embodiments, the redistribution layers 113 can include an electrically conductive material. The electrically conductive material can include a metal such as copper, aluminum, nickel, titanium, combinations thereof, or other suitable metals. The redistribution layers 113 can include metal interconnect structures (e.g., metal structures that provide electrical connections between nodes in the front-side RDL structure 110).

[0043] The redistribution layers 113 can include a metal seed layer and a metal fill material on the metal seed layer. The metal seed layer can include a stack of a titanium barrier layer and a copper seed layer, for example. The titanium barrier layer can have a thickness in a range from 50 nm to 500 nm, and the copper seed layer can have a thickness in a range from 50 nm to 500 nm. The metal fill material for the redistribution layers 113 can include copper, nickel, or copper and nickel. Other suitable metal fill materials are also within the contemplated scope of the present disclosure. The thickness of the metal fill material deposited for each redistribution layer 113 can be in a range from 2 microns to 40 microns, such as from 4 microns to 10 microns, although lesser or greater thicknesses can also be used.

[0044] In at least one embodiment, the redistribution layers 113 can include a plurality of traces (lines) and a plurality of vias connecting the plurality of traces to one another. The traces can be disposed on the dielectric layers 114, respectively, and can extend along an x-direction (direction x) (e.g., a first horizontal direction) and a y-direction (direction y) (e.g., a second horizontal direction) on a top surface of the dielectric layers 114.

[0045] The dielectric layers 114 in the front-side RDL structure 110 can include a proximal dielectric layer 114-DL1, a distal dielectric layer 114-DL4, and intermediate dielectric layers 114-DL2 and 114-DL3 disposed between the proximal dielectric layer 114-DL1 and the distal dielectric layer 114-DL4. The proximal dielectric layer 114-DL1 can include one or more vias 118 that can be used as RDL bond pads for connecting the first semiconductor die 120 in the molded portion 115 to the front-side RDL structure 110. The proximal dielectric layer 114-DL1 can also include one or more vias 119 that can be used as front-side bond pads for connecting one or more through vias (TVs) 145 in the molded portion 115 to the front-side RDL structure 110. The vias 119 can have a size (e.g., diameter, width in the x-direction, etc.) that is greater than a size of the vias 118. The vias 118 and 119 can be formed concurrently with the redistribution layers 113 and can include a metal such as copper, aluminum, nickel, titanium, combinations thereof, or other suitable metals.

[0046] The distal dielectric layer 114-DL4 can include an under bump metal (UBM) layer 111. The UBM layer 111 can include a metal, such as copper, aluminum, nickel, titanium, combinations thereof, or other suitable metals. A portion of the UBM layer 111 can be disposed on an underside of the distal dielectric layer 114-DL4 and serve as a bond pad. A ball grid array (BGA) including a plurality of solder balls 116 (e.g., ball grid array (BGA) input / output (I / O) solder balls) can be positioned on a board side surface of the distal dielectric layer 114-DL4. The BGA can be used to mount the package structure 100 to a substrate, such as a package substrate or a printed circuit board (PCB).

[0047] The solder balls 116 of the BGA can be disposed on the UBM layer 111, respectively. The solder balls 116 can include a standard solder material (e.g., SAC304 or SAC405). The solder material can include a lead-free solder material. The solder material can include tin and one or more other elements, such as silver, indium, antimony, bismuth, zinc, etc. Other suitable solder materials are within the contemplated scope of the present disclosure. The UBM layer 111 can optionally include micro bumps or metal pillars (e.g., copper pillars).

[0048] The recessed portion R 110 may be positioned on the distal dielectric layer 114-DL4. In at least one embodiment, the recessed portion R 110 may be positioned below the first semiconductor die 120 in the z-direction. The recessed portion R 110 may be positioned near the solder balls 116 in the BGA. The IPD 500 can be positioned in the center of the recessed portion R 110 . The IPD 500 can be electrically coupled to the first semiconductor die 120 through the redistribution layer 113 in the front side RDL structure 110. The IPD 500 can include one or more electronic components, such as resistors, capacitors, inductors, coils, chokes, microstripline, impedance matching elements, baluns, etc.

[0049] The IPD underfill layer 229 can be formed in the recessed portion R 110The IPD underfill layer 229 can help secure the IPD 500 to the front-side RDL structure 110. The IPD underfill layer 229 can have a low viscosity (e.g., less than about 5,000 cP at 10 rpm), can be formed of an epoxy-based polymeric material. In at least one embodiment, the IPD underfill layer 229 can include a capillary underfill that includes a mixture of an epoxy resin and silica. In at least one embodiment, the IPD underfill layer 229 can include a low viscosity suspension of silica in a prepolymer.

[0050] Attaching the IPD 500 to the front-side RDL structure 110 in the recessed portion R 110 may reduce the height of the solder balls 116 of the BGA, as a thicker UBM layer and / or solder ball height will be used to provide clearance for the IPD 500. The attachment of the IPD 500 within the recessed portion R 110 may allow the first semiconductor die 120 to have a greater thickness as compared to semiconductor dies in other package structures. 110

[0051] Attaching the IPD 500 in the recessed portion R 110 may reduce the spreading distance of underfill material along the board-side surface of the front-side RDL structure 110. Accordingly, attaching the IPD 500 in the recessed portion R 110 may help reduce the size of the underfill keep-out zone (KOZ) as compared to other package structures. This can allow the solder balls 116 to be formed closer to the IPD 500, and thereby allow an increase in the ball grid array (BGA) input / output (I / O) count.

[0052] ​A molded portion 115 can be formed on the proximal dielectric layer 114-DL1 of the front-side RDL structure 110. The molded portion 115 can have substantially the same size and shape as the size and shape of the front-side RDL structure 110. The molded portion 115 can include a first semiconductor die 120 attached to (e.g., mounted on) the proximal dielectric layer 114-DL1 of the front-side RDL structure 110. The first semiconductor die 120 can include, for example, a semiconductor chip or a small chip for high performance. High performance computing (HPC) applications, artificial intelligence (AI) applications, and 5G cellular network applications. In at least one embodiment, the first semiconductor die 120 can include a logic die (e.g., a mobile application processor, a microcontroller, etc.) or a memory die (e.g., a dynamic random access memory (DRAM) die, a wide I / O die, a M-RAM die, a R-RAM die, a NAND die, a static random access memory (SRAM), etc.). In at least one embodiment, the first semiconductor die 120 can include a central processing unit (CPU) chip, a graphics processing unit (GPU) chip, a field programmable gate array (FPGA) chip, a network chip, an application specific integrated circuit (ASIC) chip, an artificial intelligence / deep neural network (AI / DNN) accelerator chip, etc., a co-processor, an accelerator, an on-chip memory buffer, a memory cube (e.g., HBM, HMC, etc.), a high data rate transceiver die, an I / O interface die, an IPD die (e.g., an integrated passive device), a power management die (e.g., a power management integrated circuit (PMIC) die), a radio frequency (RF) die, a sensor die, a microelectromechanical system (MEMS) die, a signal processing die (e.g., a digital signal processing (DSP) die), a front-end die (e.g., an analog front end (AFE) die), a monolithic 3D heterogeneous small chip stack die, etc.

[0053] The first semiconductor die 120 can include, for example, an active region 122 on a front side of the first semiconductor die 120 and a semiconductor layer 126 (e.g., a bulk silicon region) on the active region 122. The active region 122 can include a front end of line (FEOL) region including electronic circuits including various electronic devices (e.g., transistors, resistors, etc.). In particular, the FEOL region can include one or more logic circuits including logic devices (e.g., logic gates) and / or one or more memory devices including memory devices (e.g., volatile memory (VM) devices and / or non-volatile memory (NVM)).

[0054] The active region 122 can also include a back end of line (BEOL) region on the FEOL region. The BEOL region can include interlayer dielectric layers having a plurality of dielectric layers. The dielectric layers can include, for example, Si02, a dielectric polymer, or other suitable dielectric material. The interlayer dielectric can include one or more metal interconnect structures formed therein. The metal interconnect structures can include metal traces and metal vias formed in the dielectric layers and provide electrical connections to electronic circuitry in the FEOL region.

[0055] The first semiconductor die 120 can also include one or more semiconductor die contact pads 123 on a surface of the active region 122. The semiconductor die contact pads 123 can include, for example, one or more layers and can include a metal, a metal alloy, and / or other metal-containing compounds (e.g., Cu, Al, Mo, Co, Ru, W, TiN, TaN, WN, etc.). Other suitable metal materials are also within the contemplated scope of the present disclosure.

[0056] The first semiconductor die 120 can also include a semiconductor die passivation layer 125 on a surface of the semiconductor die active region 122. In particular, the semiconductor die passivation layer 125 can at least partially cover the semiconductor die contact pads 123. The semiconductor die passivation layer 125 can include silicon oxide, silicon nitride, a low-k dielectric material such as carbon-doped oxide, an ultra-low-k dielectric material such as porous carbon-doped silicon dioxide, combinations thereof, or other suitable materials. Surfaces of the semiconductor die contact pads 123 can be exposed through openings in the passivation layer 125.

[0057] The first semiconductor die 120 can also include a dielectric layer 121 on the semiconductor die passivation layer 125. The dielectric layer 121 can include a dielectric polymer, silicon oxide, or other suitable dielectric material. A semiconductor die bond pad 127 can be formed in the dielectric layer 121 and contact the exposed surfaces of the semiconductor die contact pads 123 through the openings in the passivation layer 125. The semiconductor die bond pad 127 can have one or more layers and can include a metal, a metal alloy, and / or other metal-containing compounds (e.g., Cu, Al, Mo, Co, Ru, W, TiN, TaN, WN, etc.). Other suitable metal materials are also within the contemplated scope of the present disclosure. The first semiconductor die 120 can be connected to the front-side RDL structure 110 through connecting the semiconductor die bond pad 127 to a via 118 (e.g., RDL bond pad) in the proximal dielectric layer 114-DL1.

[0058] The first semiconductor die 120 can also include a die attach film (DAF) 129 on a backside of the first semiconductor die 120. The DAF 129 can include, for example, a thermoset polymer material that can cure or harden during an assembly process to form an adhesive. The DAF 129 can include, for example, an epoxy, a polyimide, a silicon-based material, or an acrylate-based material.

[0059] As an alternative to the DAF 129, the first semiconductor die can include a backside metal film on a backside of the first semiconductor die 120. The backside metal film can be formed on a surface of the semiconductor layer 126. The backside metal film can have good adhesion to a semiconductor material (e.g., silicon) in the semiconductor layer 126. The backside metal film can include a high thermal conductivity (e.g., k > 20 W / m*k) metal film. The backside metal film (e.g., a high thermal conductivity backside metal film) can include, for example, a sintered metal film.

[0060] The molded portion 115 can also include one or more through vias (TVs) 145 adjacent to the first semiconductor die 120 on the frontside RDL structure 110. The through vias 145 can be configured to electrically couple the frontside RDL structure 110 to the frontside RDL structure 110. Thus, the package structure 100 can accommodate an integrated fan-out structure including an upper package. In particular, the package structure 100 can serve as a lower package of a “package on package (PoP)” structure including an upper package mounted on the lower package.

[0061] The through vias 145 can be connected to the through holes 119 (e.g., RDL bond pads) in the proximal dielectric layer 114-DL1. The through vias 145 can have a cylindrical or columnar shape (e.g., a cylinder shape). Other horizontal cross-sectional shapes can be used for the through vias 145 (e.g., oval, square, rectangular, etc.). The through vias 145 can have a diameter (e.g., a width) in the x-direction that is greater than a width of the through holes 119. The through vias 145 can include a seed layer 212 at an end of the through vias 145. The seed layer 212 can include, for example, copper or one or more other suitable metals. The seed layer 212 can have a height in the z-direction that is substantially the same as a height of the DAF 129 of the first semiconductor die 120. That is, a surface of the seed layer 212 can be substantially coplanar with a surface of the DAF 129 of the first semiconductor die 120. The through vias 145 can have one or more layers and can include metals, metal alloys, and / or other metal-containing compounds (e.g., Cu, Al, Mo, Co, Ru, W, TiN, TaN, WN, etc.). Other suitable metal materials for the through vias 145 are within the contemplated scope of the present disclosure.

[0062] The molded portion 115 can also include an underfill layer 140 on the front-side RDL structure 110. The underfill layer 140 can laterally (e.g., in the x- and y-directions) encapsulate the first semiconductor die 120 and the via 145. In at least one embodiment, the dielectric layer 121 can be omitted, in which case the underfill layer 140 can also be on and around the semiconductor die bonding pads 127 between the first semiconductor die 120 and the front-side RDL structure 110. A surface of the underfill layer 140 can be substantially coplanar with a surface of the seed layer 212 and a surface of the DAF 129. In some embodiments, the underfill layer 140 can include a molding compound, a molding paste, a resin (e.g., an epoxy resin), or a combination thereof, or other suitable encapsulation material.

[0063] Referring to FIG. 1B , the front-side RDL structure 110 can have a square shape or a rectangular shape in the x-y plane. Other shapes of the front-side RDL structure 110 are within the contemplated scope of the present disclosure. FIG. 1B The position of the first semiconductor die 120 relative to the front-side RDL structure 110 is shown using dashed lines in FIG. 5. The first semiconductor die 120 can have a shape that is substantially similar to the shape of the front-side RDL structure 110 in the x-y plane. The first semiconductor die 120 can be positioned at a center region of the front-side RDL structure 110.

[0064] Referring to FIG. 1B , the recessed portion R 110 may have a square shape or a rectangular shape. In at least one embodiment, the recessed portion R 110 may have a shape that is substantially similar to the shape of the front-side RDL structure 110. The IPD 500 can be positioned at a center (e.g., in the x- and / or y-directions) of the recessed portion R 110 . The IPD 500 can have a shape that is substantially similar to the shape of the recessed portion R 110 . The solder balls 116 of the BGA can be formed around a periphery of the recessed portion R 110 .

[0065] A barrier ring 602 (e.g., an RDL3 barrier ring) can be positioned in the recessed portion R 110 . The barrier ring 602 can have a frame shape that is substantially similar to the shape of the recessed portion R 110 . The barrier ring 602 can be formed around an outer periphery of the recessed portion R 110 adjacent to a wall of the recessed portion R 110 . In at least one embodiment, the barrier ring 602 can be positioned inside a perimeter of the recessed portion R 110 (e.g., with the recessed portion R 110(Separation of sidewalls). The distance between the barrier ring 602 and the IPD 500 around the perimeter of the IPD 500 can be substantially uniform. The barrier ring 602 can be formed of the same metallic material as the redistribution layer 113. Other metallic materials used for the barrier ring 602 are within the scope of the intended disclosure.

[0066] The package structure 100 may include a recessed portion R on the board-side surface surrounding the RDL structure 110. 110 The UBM dam structure 604. The UBM dam structure 604 may have a frame shape substantially similar to the frame shape of the retaining ring 602. The UBM dam structure 604 may be located at the weld ball 116 and the recessed portion R. 110 Between. UBM dam structure 604 and the recessed portion R. 110 The space between the recessed portion R 110 The distances around the perimeter can be substantially uniform. The UBM dam structure 604 can also be formed of the same metallic material as the redistribution layer 113. Other metallic materials used for the UBM dam structure 604 are also within the scope of this disclosure.

[0067] refer to FIG. 1C As shown, the redistribution layer 113 may include a first redistribution layer 113-RDL1 located on the distal side of the near-end dielectric layer 114-DL1, a second redistribution layer 113-RDL2 located on the distal side of the intermediate dielectric layer 114-DL2, and a third redistribution layer 113-RDL3 located on the distal side of the intermediate dielectric layer 114-DL3, wherein the intermediate dielectric layer 114-DL3 is located between the near-end dielectric layer 114-DL1 and the distal dielectric layer 114-DL4.

[0068] Depression R 110 It can include the bottom surface R B and side surface R S (For example, the recessed portion R) 110 (The sidewall). Side surface R S Can be with bottom surface R B Forming a right angle. In at least one embodiment, the side surface R S Can be with bottom surface R B Forming an obtuse angle (e.g., in the range of 91 to 135 degrees). The blocking ring 602 can be located on the bottom surface R. B and side surface R S Near the intersection. In at least one embodiment, the blocking ring 602 may be adjacent to the side surface R. S Separation.

[0069] The front-side RDL structure 110 can also include a contact via 110a in the middle dielectric layer 114-DL3. The contact via 110a can contact the second redistribution layer 113-RDL2. An upper surface of the contact via 110a can be substantially coplanar with the bottom surface R 110 of the recessed portion R B (i.e., when the package structure 100 is inverted). The front-side RDL structure 110 can also include a bond pad 110b on the contact via 110a. A width of the bond pad 110b can be substantially equal to or greater than a width of the contact via 110a. The contact via 110a and the bond pad 110b can be formed of the same metal material as the redistribution layer 113. Other metal materials for the contact via 110a and the bond pad 110b are within the contemplated scope of the present disclosure.

[0070] The IPD 500 can include a rectangular or square shape in a vertical cross-sectional view. Other shapes are within the contemplated scope of the present disclosure. The IPD 500 can include a first IPD side 500a facing the front-side RDL structure 110. The IPD 500 can also include a second IPD side 500b positioned opposite the first IPD side 500a and facing away from the front-side RDL structure 110. The IPD 500 can also include a third IPD side 500c connecting the first IPD side 500a and the second IPD side 500b. The IPD 500 can also include a fourth IPD side 500d positioned opposite the third IPD side 500c and connecting the first IPD side 500a and the second IPD side 500b. The IPD 500 can be positioned substantially coplanar with an x-y plane of the front-side RDL structure 110.

[0071] The IPD 500 can include an IPD bond pad 501 (e.g., copper pillar) positioned on the first IPD side 500a. A width of the IPD bond pad 501 can be substantially equal to or greater than a width of the bond pad 110b. The IPD bond pad 501 can be formed of the same metal material as the redistribution layer 113. Other metal materials for the IPD bond pad 501 are within the contemplated scope of the present disclosure.

[0072] The solder bumps 117 between the bond pads 110b on the bottom surface R 110 of the recessed portion R B are connected to the front-side RDL structure 110. The solder bumps 117 can be formed of a material substantially similar to a material of the solder balls 116.

[0073] An IPD underfill layer 229 can be formed on the bottom surface R 110 of the recessed portion R BThe IPD undercoat layer 229 can be formed around the solder bump 117, the IPD bonding pad 501, and the bonding pad 110b. The IPD undercoat layer 229 can fill the entire recessed portion R. 110 The IPD base layer 229 can contact the first IPD side 500a and the recessed portion R. 110 bottom surface R B And completely fill the first IPD side 500a and bottom surface R. B Between and by the side surface R S A defined space. For example... FIG. 1D As shown, the diffusion of the IPD undercoat layer 229 can be stopped by the UBM dam structure 604. This allows the UBM layer 111 (and solder balls 116) to be formed closer to the IPD 500 than in the current package structure.

[0074] refer to FIG. 1D The concave portion R 110 It can include a width W in the x-direction ranging from 100 μm to 1000 μm. R The recessed portion R 110 It can also include along the y-direction in the range of 100 μm to 1000 μm (see...) FIG. 1B The length of the recessed portion R. 110 Width W in the x direction R Can be used with the recessed portion R 110 The lengths in the y-direction may be the same or different. The concave portion R 110 The depth in the z-direction can be approximately equal to the thickness T of the distal dielectric layer 114-DL4. DL In at least one embodiment, the thickness T DL and the concave portion R 110 The depths of both can range from 4 μm to 60 μm (e.g., about 15 μm).

[0075] IPD 500 may include a width W in the x-direction. 500 The width W 500 Smaller than the concave portion R 110 Width W R The recessed portion R 110 Width W R It can be in the range of 50 μm to 500 μm. In at least one embodiment, the recessed portion R 110 Width W R Width W greater than or equal to IPD 500 500 1.4 times that. IPD 500 can include a thickness T in the z-direction. 500 It is in the range of 20μm to 70μm (e.g., approximately 54μm).

[0076] The barrier ring 602 can have a width W in the x-direction ranging from 10 pm to 40 pm 602 and a thickness T in the z-direction ranging from 5 pm to 20 pm 602 The UBM dam structure 604 can also have a width W in the x-direction ranging from 10 pm to 40 pm 604 and a thickness T in the z-direction ranging from 5 pm to 20 pm 604 The thickness T of the UBM dam structure 604 604 may be sufficient to block or deter the spread of the IPD underfill layer 229 along the board side surface of the front side RDL structure 110.

[0077] The first IPD side 500a can be separated from the bottom surface R 110 of the recessed portion R B by a distance D1 ranging from 4 pm to 120 pm. The first IPD side 500a can be separated from the backside surface of the front side RDL structure 110 by a distance D2 less than 20 pm. In at least one embodiment, the first IPD side 500a can be located inside the recessed portion R 110 (e.g., D1 < T DL ; D2 < 0).

[0078] The distance in the z-direction between the second IPD side 500b and the backside surface of the front side RDL structure 110 can be less than or equal to 90 pm (e.g., about 79 pm) (e.g., D2 + T 500 ≤ 90 pm). The distance D3 between the height of the second IPD side 500b in the z-direction and the height of the lower end of the solder ball 116 in the z-direction can range from 20 pm to 40 pm (e.g., about 32 pm). The distance between the board side surface of the front side RDL structure 110 and the lower end of the solder ball 116 can be less than or equal to 120 pm (e.g., about 111 pm) (e.g., D2 + T 500 + D3 ≤ 120 pm).

[0079] The distance D4 in the x-direction between the side surface R 110 of the recessed portion R S and the UBM layer 111 can range from 20 pm to 100 pm. The distance D5 in the x-direction between the UBM layer 111 and the third IPD side 500c can range from 50 pm to 150 pm. The distance D5 can also be considered as the distance between the solder ball 116 and the third IPD side 500c. In at least one embodiment, the distance D5 can be less than 30% of the width W 500 of the IPD 500. The distance D5 can be referred to as a “keep out zone” (KOZ). By attaching the IPD 500 in the recessed portion R 110In this embodiment, the length of the KOZ (e.g., D5) in the package structure 100 can be smaller than the length of the KOZ in other package structures.

[0080] The fourth IPD side 500d and the recessed portion R 110 side surface R S The distance D6 between them can range from 20 μm to 50 μm. The recessed portion R... 110 side surface R S The distance D7 between the dam structure 604 and the UBM dam can be in the range of 5μm to 20μm.

[0081] It should be noted that the above references FIG. 1D The dimensions are intended to be illustrative and do not necessarily limit this disclosure.

[0082] FIG. 2A to FIG. 2K This is a vertical cross-sectional view of various intermediate structures in a method of forming a package structure 100 according to one or more embodiments. Specifically, FIG. 2A This is a vertical cross-sectional view of an intermediate structure including a seed layer 212 located on an adhesive layer 210, according to one or more embodiments.

[0083] refer to FIG. 2A An adhesive layer 210 may be formed on the upper surface of the carrier substrate 5. The carrier substrate 5 may include a semiconductor wafer (e.g., a circular wafer or a rectangular wafer) or a glass substrate. The lateral dimensions of the carrier substrate 5 (e.g., the diameter of a circular wafer or the side length of a rectangular wafer) may range from 100 mm to 500 mm, for example, 200 mm to 400 mm, but smaller or larger lateral dimensions may also be used. The carrier substrate 5 may be transparent or opaque. The thickness of the carrier substrate 5 may be sufficient to provide mechanical support to the package structure 100. For example, the thickness of the carrier substrate 5 may range from 60 micrometers to 1 millimeter, but smaller and larger thicknesses may also be used.

[0084] The adhesive layer 210 may include a photothermal conversion (LTHC) layer or may include a thermally degradable adhesive material. In at least one embodiment, the adhesive layer 210 may cover the entire carrier substrate 5. The LTHC layer may include a solvent-based coating applied using a spin-coating method. The LTHC layer may form a layer that converts ultraviolet light into heat, causing the LTHC layer to lose its adhesiveness. Alternatively, the adhesive layer may include a thermally degradable adhesive material. For example, the adhesive layer may include an acrylic pressure-sensitive adhesive that decomposes at elevated temperatures. The peel temperature of the thermally degradable adhesive material may be in the range of 150°C to 400°C. Other suitable thermally degradable adhesive materials that decompose at other temperatures are also within the scope of this disclosure.

[0085] A seed layer 212 (e.g., a metal seed layer, a copper seed layer, etc.) can be formed on the adhesive layer 210. In at least one embodiment, the seed layer 212 can cover the entire adhesive layer 210. The seed layer 212 may, for example, be formed by depositing the seed layer 212 in a deposition process such as CVD, PECVD, PVD, spin-on, lamination, or other suitable deposition technique. The seed layer 212 can include, for example, one or more layers, and can include one or more metals, metal alloys, and / or other metal-containing compounds (e.g., Cu, Al, Mo, Co, Ru, W, TiN, TaN, WN, etc.). Other suitable metal materials are also within the contemplated scope of the present disclosure.

[0086] FIG. 2B is a vertical cross-sectional view of an intermediate structure including a photoresist layer 214 according to one or more embodiments. The photoresist layer 214 can be formed to have a thickness greater than a thickness of the first semiconductor die 120. The photoresist layer 214 can be patterned to form openings O 214 through the photoresist layer 214. Bottoms of the openings O 214 may be comprised of an upper surface of the seed layer 212. For example, a mask layer (not shown) can be formed on an upper surface of the photoresist layer 214 and patterned to have a pattern in the photoresist layer 214 corresponding to a desired pattern. The photoresist layer 214 can then be patterned by an etching process (e.g., wet etching, dry etching, etc.) through openings in the mask layer to form the openings O 214 . The etching process can be performed until the upper surface of the seed layer 212 is exposed. The mask layer can then be removed to expose the upper surface of the photoresist layer 214.

[0087] FIG. 2C is a vertical cross-sectional view of an intermediate structure including a via 145 according to one or more embodiments. As shown in FIG. 2C , the via 145 can be formed in the openings O 214 in the photoresist layer 214. The via 145 can be formed by electroplating a metal fill material (e.g., copper) in the openings O 214 using the seed layer 212 exposed at the bottoms of the openings O 214 . The metal material used for electroplating can include, for example, one or more layers, and can include metals, metal alloys, and / or other metal-containing compounds (e.g., Cu, Al, Mo, Co, Ru, W, TiN, TaN, WN, etc.). Other suitable metal materials are also within the contemplated scope of the present disclosure.

[0088] The metal fill material fills the openings O 214Thereafter, the upper surface of the metal fill material and the photoresist layer 214 can be planarized, e.g., by chemical mechanical polishing (CMP) or another suitable planarization technique. After planarization, the upper surface of the metal fill material (e.g., the upper surface of the via 145) can be substantially coplanar with the upper surface of the photoresist layer 214.

[0089] FIG. 2D is a vertical cross-sectional view of an intermediate structure including the via 145 according to one or more embodiments. After the upper surface of the metal fill material and the photoresist layer 214 making up the via 145 are planarized, the photoresist layer 214 can then be removed, e.g., by etching (e.g., wet etching, dry etching, etc.). The seed layer 212 can also be etched (e.g., wet etching, dry etching, etc.) to expose the upper surface of the adhesive layer 210 between the vias 145.

[0090] The seed layer 212 can be etched simultaneously in the same etching step as the photoresist layer 214, or etched in a separate step after the photoresist layer 214 is etched. As shown in FIG. 2D after the seed layer 212 is etched, portions of the seed layer 212 can remain unetched beneath the vias 145, respectively.

[0091] FIG. 2E is a vertical cross-sectional view of an intermediate structure including the first semiconductor die 120 according to one or more embodiments. The first semiconductor die 120 can be inverted such that the DAF 129 faces the adhesive layer 210, and then placed on the adhesive layer 210. The entire upper surface of the DAF 129 can contact the upper surface of the adhesive layer 210. In at least one embodiment, the first semiconductor die 120 can be placed on the upper surface of the adhesive layer 210 by a pick-and-place (PnP) process (e.g., a robotic PnP process).

[0092] The first semiconductor die 120 can be placed on the adhesive layer 210 such that a minimum distance Dm (e.g., 100 pm) is maintained between the DAF 129 and an adjacent via 145 around the periphery of the first semiconductor die 120. Pressure can then be applied to the first semiconductor die 120 (indicated by the directional arrow in FIG. 2E ), to press the DAF 129 onto the surface of the adhesive layer 210. The intermediate structure can then be heated (e.g., in an oven) to firmly secure the DAF 129 to the surface of the adhesive layer 210. As shown in FIG. 2E the height of the via 145 can be greater than the height of the first semiconductor die 120.

[0093] FIG. 2Fis a vertical cross-sectional view of an intermediate structure including a lower encapsulant layer 140 according to one or more embodiments. The lower encapsulant layer 140 can be formed through a series of over-molding and planarization processes. In particular, the lower encapsulant layer 140 (e.g., an epoxy mold compound (EMC)) can be formed over the adhesive layer 210 to fill the gap between the first semiconductor die 120 and the via 145 and encapsulate the first semiconductor die 120 and the via 145. The lower encapsulant layer 140 can be formed to have a greater height than the height of the via 145. The lower encapsulant layer 140 can be formed, for example, through a deposition technique such as CVD, PECVD, PVD, spin-on, lamination, or other suitable deposition technique.

[0094] FIG. 2G is a vertical cross-sectional view of an intermediate structure including a lower encapsulant layer 140 after a planarization process according to one or more embodiments. Referring to FIG. 2G A planarization process can be performed on the surface 140a of the lower encapsulant layer 140 until the upper surface 145a of the via 145 and the upper surface 127a of the semiconductor die bond pad 127 are exposed. That is, the planarization process can be performed until the surface 140a of the lower encapsulant layer 140 is substantially coplanar with the upper surface 145a of the via 145 and the upper surface 127a of the semiconductor die bond pad 127. The planarization process can include, for example, a mechanical grinding process and / or a chemical mechanical polishing (CMP) process.

[0095] FIG. 2H is a vertical cross-sectional view of an intermediate structure including a front-side RDL structure 110 according to one or more embodiments. The dielectric layers 114 and redistribution layers 113 can be formed alternately in a series of process steps. In particular, a proximal dielectric layer 114-DL1 can be formed on the lower encapsulant layer 140. The proximal dielectric layer 114-DL1 can be formed, for example, through a deposition process such as CVD, PECVD, PVD, spin-on, lamination, or other suitable deposition technique.

[0096] An opening can be formed (e.g., through etching in a photolithography process) in the proximal dielectric layer 114-DL1. A first redistribution layer 113-RDL1 can then be formed (e.g., through an electroplating process) in the opening and on the proximal dielectric layer 114-DL1 (also referred to as proximal dielectric layer 114p). In this way, a via 118 (e.g., an RDL bond pad) can be formed to contact the semiconductor die bond pad 127, and a via 119 (e.g., a front-side bond pad) can be formed to contact the via 145.

[0097] The remaining dielectric layers 114 and redistribution layers 113 of the front-side RDL structure 110 can then be formed alternately in a similar manner. Specifically, during formation of the third redistribution layer 113-RDL3, a plurality of openings can be formed at locations of the recessed portions R 110 in the middle dielectric layer 114-DL3. Then, when a metal material (e.g., copper) is deposited on the middle dielectric layer 114-DL3 to form the third redistribution layer 113-RDL3, the metal material can be formed in the openings to form contact vias 110a that contact the second redistribution layer 113-RDL2. The metal material can also be formed on the distal surface of the middle dielectric layer 114-DL3 to form a barrier ring 602 and to form bond pads 110b that contact the contact vias 110a. The metal material can then be patterned (e.g., through etching in a photolithography process) to complete formation of the contact vias 110a, the bond pads 110b, the barrier ring 602, and the third redistribution layer 113-RDL3. Thus, in at least one embodiment, the contact vias 110a, the bond pads 110b, the barrier ring 602, and the third redistribution layer 113-RDL3 can all be formed simultaneously and using the same metal material.

[0098] A distal dielectric layer 114-DL4 can then be formed on the middle dielectric layer 114-DL3 and on the third redistribution layer 113-RDL3. Openings O 110 may then be formed in the distal dielectric layer 114-DL4 (e.g., through a photolithography process) so as to expose an upper surface of the third redistribution layer 113-RDL3. At the same time that the openings O 110 are formed, recessed portions R 110 may be formed in the distal dielectric layer 114-DL4. Thus, in at least one embodiment, the openings O 110 and the recessed portions R 110 may be formed simultaneously using the same etching process.

[0099] FIG. 2I is a vertical cross-sectional view of an intermediate structure including a UBM layer 111 according to one or more embodiments. Referring to FIG. 2I , a UBM dam structure 604 can be formed on a surface of the distal dielectric layer 114-DL4. The UBM dam structure 604 can be formed, for example, through a photolithography process in which a photoresist layer (not shown) is deposited on the distal dielectric layer 114-DL4 (also referred to as distal dielectric layer 114d) and is patterned to form openings in the photoresist layer corresponding to the UBM dam structure 604. A metal material can then be deposited in the openings to form the UBM dam structure 604 on the distal dielectric layer 114-DL4. The photoresist layer can then be removed from the surface of the distal dielectric layer 114-DL4 (e.g., through ashing or other suitable process). Openings O110 (see, e.g., FIG. 2H ) to form (e.g., via a plating process) the UBM layer 111. It should be noted that in at least one embodiment, the order of formation can be reversed, such that the UBM layer 111 is formed before the UBM dam structure 604.

[0100] FIG. 2J is a vertical cross-sectional view of an intermediate structure including the IPD 500, in accordance with one or more embodiments. The IPD 500 can be formed on the IPD bond pads 501 along with the solder bumps 117. The IPD 500 can then be connected to the front-side RDL structure 110 in the recessed portion R 110 . Specifically, the IPD 500 can be moved into position over the recessed portion R 110 . For example, an electromechanical pick-and-place (PNP) machine can be used to move the IPD 500. The solder bumps 117 can then be lowered into the recessed portion R 110 and onto the bond pads 110b, respectively. The intermediate device can then be heated to reflow the solder bumps 117 on the bond pads 110b, respectively.

[0101] The IPD underfill layer 229 (e.g., an epoxy-based polymeric material) can then be dispensed (e.g., injected) into the recessed portion R 110 . The IPD underfill layer 229 can be formed continuously under the entire IPD 500. The IPD underfill layer 229 can be dispensed until the IPD underfill layer 229 contacts the UBM dam structure 604, at which point the dispensing can be stopped. The IPD underfill layer 229 can then be cured, for example, in a box oven at a temperature in the range of 120 °C to 180 °C and for a duration in the range of 60 minutes to 120 minutes, to provide sufficient rigidity and mechanical strength to the IPD underfill layer 229.

[0102] FIG. 2K is a vertical cross-sectional view of an intermediate structure including the solder balls 116, in accordance with one or more embodiments. After the UBM layer 111 is formed, the solder balls 116 can be formed on the UBM layer 111, respectively. It should be noted that the solder balls 116 can be formed on the UBM layer 111 before or after the IPD 500 is connected to the front-side RDL structure 110. The solder balls 116 can be formed, for example, by a suitable process such as reflow soldering, evaporation, ball drop, screen printing, or plating.

[0103] After the solder balls 116 are formed on the UBM layer 111, the intermediate structure can be inverted and placed on a carrier tape (not shown). The carrier tape can include a thin, flexible strip made of plastic. The carrier tape can optionally include a pattern of pockets or cavities that precisely match the arrangement of the solder balls 116 on the intermediate structure. The intermediate structure can be positioned so that each solder ball 116 sits within its corresponding pocket. A cover tape (not shown) can then be applied to the carrier tape, sealing the solder balls 116 within their respective pockets. The cover tape can be made of clear plastic and is firmly adhered to the carrier tape, forming a protective barrier.

[0104] The intermediate structure can then be peeled off the carrier substrate 5. The intermediate structure can be peeled off the carrier substrate 5, for example, by decomposing the adhesive layer 210 (e.g., by using heat, ultraviolet (UV) light, etc.). The adhesive layer 210 adheres the carrier substrate 5 to the surface of the intermediate structure. An LTHC cleaning step (e.g., post-laser drilling cleaning) or other suitable cleaning process can then be performed in order to clean the surface of the intermediate structure. The cleaning process can help ensure that all adhesive material from the adhesive layer 210 has been removed from the surface of the intermediate structure.

[0105] Multiple intermediate structures can be formed together in a wafer-level process. In this case, the multiple intermediate structures can be separated into individual units (e.g., into multiple package structures 100). In at least one embodiment, the intermediate structures can be separated using a dicing saw. The dicing saw can saw along the dicing lines that are between the intermediate structures. This can complete the formation of the multiple package structures 100.

[0106] FIG. 3 is a flow diagram showing a method of forming a package structure 100 according to one or more embodiments. Step 310 of the method can include forming a molding portion 115 including a lower encapsulant layer 140, a plurality of vias 145 in the lower encapsulant layer 140, and a first semiconductor die 120 in the lower encapsulant layer 140. Step 320 can include forming a front-side redistribution layer (RDL) structure 110 including a recessed portion R 110 in the molding portion 115, wherein the plurality of vias 145 are configured to electrically couple the front-side RDL structure 110 to an upper encapsulation. Step 330 can include attaching an IPD 500 to the front-side RDL structure 110 in the recessed portion R 110 , wherein the IPD 500 is electrically coupled to the first semiconductor die 120.

[0107] FIG. 4is a vertical cross-sectional view of a semiconductor device 400 including an upper package 40 on a package structure 100 according to one or more embodiments. The semiconductor device 400 can be referred to as a "stacked package."

[0108] The upper package 40 can include sidewalls 40a substantially aligned with sidewalls 100a of the package structure 100. The upper package 40 can include a package substrate 405. The package substrate 405 can include a core substrate or a coreless substrate. The package substrate 405 can include one or more dielectric layers stacked in a thickness direction of the package substrate 405. In at least one embodiment, the package substrate 405 can include a build-up film such as an ABF substrate. In at least one embodiment, the package substrate includes one or more layers of epoxy, such as a BT epoxy, and a dielectric polymer material, such as PI, BCB, or PBO. Other suitable dielectric materials for the package substrate 405 are within the intended scope of the present disclosure.

[0109] The package substrate 405 can include a bottom contact pad 417 on a bottom surface of the package substrate 405. The package substrate can include an upper contact pad 419 on an upper surface of the package substrate 405. The upper contact pad 419 can be electrically connected to the bottom contact pad 417 by one or more interconnect structures 418 (e.g., metal traces and metal vias) in the package substrate 405.

[0110] The semiconductor device 400 can also include a plurality of solder balls 416 for attaching the upper package 40 to the package structure 100. The solder balls 416 can be on the seed layer 212 in the package structure 100. The bottom contact pad 417 in the upper package 40 can contact the solder balls 416 on the seed layer 212. The upper package 40 can be electrically coupled to the package structure 100 (e.g., to the front-side RDL structure 110) through the solder balls 416.

[0111] The upper package 40 can also include a first upper semiconductor die 420 (e.g., a second semiconductor die) mounted on the package substrate 405 (e.g., through hybrid bonding, die attach film, etc.). A center point (in the x-y plane) of the first upper semiconductor die 420 can be substantially aligned in the z-direction with a center point (in the x-y plane) of the first semiconductor die 120 in the package structure 100. The first upper semiconductor die 420 can include an active region 422 connected to the upper contact pad 419 by one or more wires 421.

[0112] The upper package 40 can also include a second upper semiconductor die 520 (e.g., a third semiconductor die) mounted on the first upper semiconductor die 420 (e.g., through hybrid bonding, die attach film, etc.). The second upper semiconductor die 520 can have a width in the x-direction that is less than a width of the first upper semiconductor die 420 in the x-direction. The second upper semiconductor die 520 can include an active region 522 connected to the upper contact pads 419 by one or more wires 423. Each of the first upper semiconductor die 420 and the second upper semiconductor die 520 can be similar in design and / or function to the first semiconductor die 120 in the package structure 100 as described above. In at least one embodiment, each of the first upper semiconductor die 420 and the second upper semiconductor die 520 can include a dynamic random access memory (DRAM) die.

[0113] The upper package 40 can also include an upper encapsulant layer 440 similar to the lower encapsulant layer 140 in the package structure 100. The upper encapsulant layer 440 can be formed on the package substrate 405 and can substantially encapsulate the first upper semiconductor die 420, the second upper semiconductor die 520, the wires 421, and the wires 423.

[0114] Referring to FIG. 4 The semiconductor device 400 can also include a thermally conductive underfill layer 50 positioned between the upper package 40 and the package structure 100. The sidewalls 50a of the thermally conductive underfill layer 50 can be substantially aligned with the sidewalls 40a of the upper package 40, and the thermally conductive underfill layer 50 can be formed around the solder balls 416 and substantially fill a gap (e.g., a space) between a bottom surface of the package substrate 405 in the upper package 40 and an upper surface of the lower encapsulant layer 140, the seed layer 212, and the DAF 129 in the package structure 100 in the package substrate 405. The thermally conductive underfill layer 50 can enhance heat dissipation and thermal performance by improving thermal conductivity (e.g., enhancing heat transfer) between the first semiconductor die 120 and the package substrate 405.

[0115] The thermally conductive underfill layer 50 can help secure the upper package 40 to the package structure 100. The thermally conductive underfill layer 50 can have a low viscosity (e.g., less than about 5,000 cP at 10 rpm) and can be made of an epoxy-based polymeric material. In at least one embodiment, the thermally conductive underfill layer 50 can include a capillary underfill that includes a mixture of an epoxy resin and silica. In at least one embodiment, the thermally conductive underfill layer 50 can include a low viscosity suspension of silica in a prepolymer.

[0116] In at least one embodiment, the thermally conductive underfill layer 50 can have a thermal conductivity greater than 20 W / m-K. The thermally conductive underfill layer 50 can include, for example, a filled polymer underfill. The filled polymer underfill can include a thermally conductive filler, such as ceramic particles, metal particles, or carbon fibers suspended within a polymer material (e.g., a polymer matrix). It should be noted that the underfill material can be modified to a high-k underfill material by adding a higher percentage of filler (e.g., metal filler) or changing the high-k thermally conductive filler in the underfill material.

[0117] The upper package 40 can be fabricated by a process of mounting the first upper semiconductor die 420 (e.g., a second semiconductor die) on the package substrate 405. A pick-and-place machine can be used to position the first upper semiconductor die 420 over the package substrate 405 for subsequent alignment with the first semiconductor die 120. The first upper semiconductor die 420 can be attached to the package substrate 405 by a die attach film, by hybrid bonding, or by other suitable bonding methods.

[0118] The second upper semiconductor die 520 (e.g., a third semiconductor die) can then be mounted on the first upper semiconductor die 420. A pick-and-place machine can also be used to position the second upper semiconductor die 520 over the first upper semiconductor die 420. The second upper semiconductor die 520 can be attached to the first upper semiconductor die 420 by a die attach film, by hybrid bonding, or by other suitable bonding methods. The ends of the wire 421 and the wire 423 can then be attached (e.g., by soldering) to the active region 422 of the first upper semiconductor die 420 and the active region 522 of the second upper semiconductor die 520, respectively. The other ends of the wire 421 and the wire 423 can then be attached (e.g., by soldering) to the upper contact pad 419. The upper encapsulation layer 440 can then be formed on the package substrate 405 in a similar manner as the method of forming the lower encapsulation layer 140 as described above. The solder balls 416 can then be formed on the bottom contact pad 417 in a similar manner as the method of forming the solder balls 116.

[0119] After the upper package 40 is fabricated, the upper package 40 can be mounted on the package structure 100. In at least one embodiment, the upper package 40 can be mounted on the package structure 100 in a wafer-level process before a wafer containing a plurality of package structures 100 is singulated (e.g., by a dicing saw) into a plurality of individual units.

[0120] The upper package 40 can be mounted on the package structure 100 via a pick-and-place machine. A pick-and-place machine can be used to position the upper package 40 above the package structure 100 so as to align the solder balls 416 with portions of the seed layer 212 on the through-holes 145. The pick-and-place machine can then lower the upper package 40 onto the package structure 100, and heat and / or pressure can be applied to reflow the solder balls 416 and bond the upper package 40 to the package structure 100.

[0121] A thermally conductive underfill layer 50 (e.g., an epoxy-based polymer material) can then be dispensed (e.g., injected) onto the upper surface of the package structure 100, beneath the package substrate 405, and around the solder balls 416. Referring to FIG. 5B, the thermally conductive underfill layer 50 can be continuously formed beneath the entire upper package 60. The thermally conductive underfill layer 50 can then be cured, for example, in a box oven, with a heat treatment at a temperature in the range of 120 °C to 180 °C and a duration in the range of 60 minutes to 120 minutes, to give the thermally conductive underfill layer 50 sufficient rigidity and mechanical strength. FIG. 4

[0122] After the thermally conductive package underfill 50 is cured, the intermediate structure can be singulated into individual units (e.g., singulated into a plurality of semiconductor devices 400). In at least one embodiment, the plurality of semiconductor devices 400 can be singulated via the use of a dicing saw.

[0123] FIG. 5 is a vertical cross-sectional view of a semiconductor package 550 including a semiconductor device 400 on a package substrate 510, in accordance with one or more embodiments. The package substrate 510 can include, for example, a core 512, a package substrate upper dielectric layer 514 formed on the core 512 (e.g., a first side or chip side of the package substrate 510), and a package substrate lower dielectric layer 516 formed on the core 512 (e.g., a second side or board side of the package substrate 510). In particular, the package substrate 510 can include a build-up film substrate, such as an Ajinomoto Build-up Film (ABF) substrate. That is, in at least one embodiment, each of the package substrate upper dielectric layer 514 and the package substrate lower dielectric layer 516 can be described as an ABF layer.

[0124] The core 512 can provide rigidity to the package substrate 510. The core 512 can include, for example, an epoxy, such as a bismaleimide triazine epoxy (BT epoxy) and / or a woven glass laminate. The core 512 can alternatively or additionally include an organic material, such as a polymer material. In particular, the core 512 can include a dielectric polymer material, such as polyimide (PI), benzocyclobutene (BCB), or polybenzobisoxazole (PBO). Other suitable dielectric materials are also within the contemplation of the present disclosure. ​

[0125] The core 512 can include one or more vias 512a. The one or more vias 512a can extend from a lower surface of the core 512 to an upper surface of the core 512. The one or more vias 512a can allow for electrical connections between the dielectric layer 514 above the package substrate and the dielectric layer 516 below the package substrate. The one or more vias 512a can include, for example, one or more layers and can include metals, metal alloys, and / or other metal-containing compounds (e.g., Cu, Al, Mo, Co, Ru, W, TiN, TaN, WN, etc.). Other suitable metal materials are also within the intended scope of the present disclosure.

[0126] The dielectric layer 516 below the package substrate can include multiple layers and, in particular, can include an ABF built-in film. The dielectric layer 516 below the package substrate can include an organic material such as a polymeric material. In particular, the dielectric layer 516 below the package substrate can include one or more layers of a dielectric polymeric material such as polyimide (PI), benzocyclobutene (BCB), or polybenzobisoxazole (PBO). Other suitable dielectric materials are also within the intended scope of the present disclosure.

[0127] The dielectric layer 516 below the package substrate can include one or more package substrate lower bonding pads 516a on a board side surface of the dielectric layer 516 below the package substrate. In particular, the package substrate lower bonding pads 516a can be exposed on the board side surface of the dielectric layer 516 below the package substrate. The dielectric layer 516 below the package substrate can also include one or more metal interconnect structures 516b. The metal interconnect structures 516b can be connected to the package substrate lower bonding pads 516a and the vias 512a in the core 512. The metal interconnect structures 516b can include metal layers (e.g., copper traces) and metal vias connecting the metal layers. The package substrate lower bonding pads 516a and the metal interconnect structures 516b can include, for example, one or more layers and can include metals, metal alloys, and / or other metal-containing compounds (e.g., Cu, Al, Mo, Co, Ru, W, TiN, TaN, WN, etc.). Other suitable metal materials for the metal interconnect structures 516b are also within the intended scope of the present disclosure.

[0128] A package substrate lower surface layer 510b can be formed on the board side surface of the package substrate lower dielectric layer 516. The package substrate lower surface layer 510b can partially cover the package substrate lower bond pads 516a. The package substrate lower surface layer 510b can include one or more of a passivation layer and a protective layer. The package substrate lower surface layer 510b can include, for example, a dielectric polymer material such as polyimide (PI), benzocyclobutene (BCB), or polybenzobisoxazole (PBO). The package substrate lower surface layer 510b can alternatively or additionally include silicon oxide, silicon nitride, a low-k dielectric material such as carbon-doped oxide, an ultra-low-k dielectric material such as porous carbon-doped silicon dioxide, or combinations thereof. Other suitable dielectric materials are also within the contemplated scope of the present disclosure.

[0129] A ball grid array (BGA) including a plurality of solder balls 510c can be formed on the board side surface of the package substrate lower dielectric layer 516. The solder balls 510c can allow the semiconductor package 550 to be securely mounted on a substrate, such as a printed circuit board (PCB), and electrically coupled to the PCB substrate. The solder balls 510c can respectively contact the package substrate lower bond pads 516a.

[0130] A package substrate upper dielectric layer 514 can be formed on the upper surface of the core 512. The package substrate upper dielectric layer 514 can also include multiple layers, and in particular, can include an Ajinomoto Build-up Film (e.g., ABF). The package substrate upper dielectric layer 514 can also include an organic material such as a polymer material. In particular, the package substrate upper dielectric layer 514 can include a dielectric polymer material such as polyimide (PI), benzocyclobutene (BCB), or polybenzobisoxazole (PBO). Other suitable dielectric materials are also within the contemplated scope of the present disclosure.

[0131] The package substrate upper dielectric layer 514 can include one or more package substrate upper bond pads 514a on the chip side surface of the package substrate upper dielectric layer 514. In particular, the package substrate upper bond pads 514a can be exposed on the chip side surface of the package substrate upper dielectric layer 514. In at least one embodiment, a bond pad surface layer (not shown) (e.g., one or more layers of metal (e.g., tin, nickel, palladium, gold, etc.) and other materials) can be formed on the package substrate upper bond pads 514a to improve solder joint reliability.

[0132] The dielectric layer 514 on the package substrate can also include one or more metal interconnect structures 514b. The metal interconnect structures 514b can include metal layers (e.g., copper traces) and metal vias connecting the metal layers. The bond pad 514a on the package substrate can be electrically connected to the solder ball 510c of the BGA through the metal interconnect structures 514b, the via 512a, the metal interconnect structures 516b, and the bond pad 516a under the package substrate. The bond pad 514a on the package substrate and the metal interconnect structures 514b can include, for example, one or more layers, and can include metals, metal alloys, and / or other metal-containing compounds (e.g., Cu, Al, Mo, Co, Ru, W, TiN, TaN, WN, etc.). Other suitable metal materials are also within the contemplated scope of the present disclosure.

[0133] The surface layer 510a on the package substrate can be formed on the chip-side surface of the dielectric layer 514 on the package substrate. The surface layer 510a on the package substrate can include a coating layer, a lamination layer, etc. The surface layer 510a on the package substrate can be formed to at least partially cover the bond pad 514a on the package substrate.

[0134] In at least one embodiment, the surface layer 510a on the package substrate can include a solder resist layer (e.g., a solder resist layer). The solder resist layer can include a thin layer of a polymeric material (e.g., an epoxy polymer). The thickness of the solder resist layer can be in a range of about 5 pm to 50 pm. In at least one embodiment, the solder resist layer can have a thickness in a range of about 10 pm to 30 pm. Greater or lesser thicknesses of the solder resist layer can be used. The solder resist layer can be formed to cover the bond pad 514a on the package substrate and other metal components (e.g., wires, copper traces) on the chip-side surface of the package substrate 510. The solder resist layer can protect the bond pad 514a on the package substrate and the other metal components from oxidation. The solder resist layer can also inhibit (e.g., prevent) solder bridges (e.g., unintended electrical connections) from forming between closely spaced metal features. The solder resist layer can include solder resist openings (SROs) over the bond pad 514a on the package substrate, respectively. The upper surface of the bond pad 514a on the package substrate can be exposed through the solder resist openings. The solder resist openings can have tapered sidewalls such that the diameter (in the x-y plane) of the solder resist openings can decrease in a direction toward the bond pad 514a on the package substrate.

[0135] The package substrate top surface layer 510a can alternatively or additionally include a layer other than a solder resist layer, such as a passivation layer or a protective layer. In particular, the package substrate top surface layer 510a can alternatively or additionally include a dielectric polymer material, such as polyimide (PI), benzocyclobutene (BCB), or polybenzobisoxazole (PBO), silicon oxide, silicon nitride, a low-k dielectric material such as carbon-doped oxide, an ultra-low-k dielectric material (e.g., porous carbon-doped silicon dioxide), a combination thereof, or other suitable material. The package substrate top surface layer 510a can alternatively or additionally be formed, for example, by chemical vapor deposition (CVD), physical vapor deposition (PVD), spin coating, lamination, or other suitable deposition technique.

[0136] The solder balls 116 (e.g., BGA) can be connected to the package substrate top bond pads 514a in the package substrate 510 to mount the semiconductor device 400 on the package substrate 510. A package underfill layer 529 can be formed under and around the semiconductor device 400 and the solder balls 116 to secure the semiconductor device 400 to the package substrate 510. The package underfill layer 529 can be formed of an epoxy-based polymeric material.

[0137] Referring to FIG. 5 The package underfill layer 529 can be formed on the IPD underfill layer 229. The package underfill layer 529 can also be formed on exposed portions (e.g., portions not covered by the IPD underfill layer 229) of the IPD 500.

[0138] The semiconductor package 550 can also include a stiffener ring 530, which can be secured to the package substrate 510 by an adhesive 560 such as a silicone adhesive or an epoxy adhesive. Other adhesives are also within the contemplation of the present disclosure. The stiffener ring 530 can be formed of a metal such as copper or an aluminum alloy having a nickel coating. The stiffener ring 530 can optionally be formed of a ceramic material or a hard plastic (polymeric) material. The stiffener ring 530 can be formed on the package substrate 510 to enclose (e.g., surround) the semiconductor device 400 in the x-y plane. The stiffener ring 530 can extend from the package substrate 510 in a substantially vertical direction (e.g., along the z-direction). The stiffener ring 530 can help provide rigidity to the package substrate 510 and the semiconductor device 400.

[0139] FIG. 6 is a vertical cross-sectional view of a semiconductor device 600 in accordance with one or more embodiments. The semiconductor device 600 can be substantially similar to the semiconductor device 400 FIG. 4However, in semiconductor device 600, upper package 40 can be replaced with upper package 60 that includes upper semiconductor die 620. Upper semiconductor die 620 can be substantially the same as first semiconductor die 120. In one embodiment, upper semiconductor die 620 can include a memory die such as a DRAM die.

[0140] Upper semiconductor die 620 can be encapsulated in upper encapsulant layer 640. Upper encapsulant layer 640 can be substantially similar to lower encapsulant layer 140 (e.g., see FIG. 1A). It should be noted that in FIG. 1A ) semiconductor package 550 in semiconductor device 400 can be replaced with semiconductor device 600. FIG. 5

[0141] Upper semiconductor die 620 can be flip-chip mounted on package structure 100. Upper semiconductor die 620 can include active region 622 on a front side of upper semiconductor die 620. Upper semiconductor die 620 can also include semiconductor layer 626 (e.g., a bulk silicon region) on active region 622. The front side of upper semiconductor die 620 can also include passivation layer 650 and a plurality of bond pads 655 in passivation layer 650. Upper semiconductor die 620 can be connected to lower package by a plurality of C4 bumps 621 formed on bond pads 655 and connected to portions of seed layer 212 on through holes 145, respectively. Thermally conductive underfill layer 50 can be formed on package structure 100 and around C4 bumps 621. Thermally conductive underfill layer 50 can completely fill the gap between upper package 60 and package structure 100.

[0142] FIG. 7 is a detailed vertical cross-sectional view of a first alternative design of front side RDL structure 110 according to one or more embodiments. The first alternative design can be substantially similar to the original design of front side RDL structure 110 of FIG. 1A. However, in the first alternative design, front side RDL structure 110 does not include barrier ring 602. In this embodiment, IPD underfill layer 229 can contact the entire sidewall R 110 of recessed portion R s . UBM dam structure 604, which is outside recessed portion R 110 , can stop or prevent the spread of IPD underfill layer 229. Thus, UBM dam structure 604 can be omitted in the first alternative design. FIG. 1C

[0143] FIG. 8 is a detailed vertical cross-sectional view of a second alternative design of front side RDL structure 110 according to one or more embodiments. The second alternative design can be substantially similar to the original design of front side RDL structure 110 of FIG. 1A and the first alternative design of FIG. 1C. FIG. 1C FIG. 1C ​​​of the recessed portion R 110 . However, in a second alternative design, a distal dielectric layer 114-DL4 (e.g., a polyimide layer) can be formed on at least a portion of the barrier ring 602 in the recessed portion R 110 . That is, the barrier ring 602 can protrude in the x-direction from the sidewall Rs of the recessed portion R 602 . In at least one embodiment, the distal dielectric layer 114-DL4 can cover at least 50% of the width W 110 of the barrier ring 602.

[0144] Referring to FIG. 1A-FIG. 6 , the package structure 100 can include a front-side redistribution layer (RDL) structure 110 including a recessed portion R 110 , a lower encapsulant layer 140 positioned on the front-side RDL structure 110 and including a plurality of vias 145 configured to electrically couple the front-side RDL structure 110 to an upper package, a first semiconductor die 120 positioned in the front-side RDL structure 110 and the lower encapsulant layer 140, and an integrated passive device (IPD) 500 connected to the front-side RDL structure 110 in the recessed portion R 110 and electrically coupled to the first semiconductor die 120.

[0145] In some embodiments, the IPD 500 can include a zero inductance IPD (ZL IPD). In some embodiments, the front-side RDL structure 110 can include a plurality of dielectric layers 114, the recessed portion R 110 may be positioned in a distal dielectric layer 114-DL4 of the plurality of dielectric layers 114, and a depth of the recessed portion R 110 may be substantially equal to a thickness of the distal dielectric layer 114-DL4. In some embodiments, the plurality of dielectric layers 114 can include an intermediate dielectric layer 114-DL3 adjacent to the distal dielectric layer 114-DL4, and the IPD 500 can be mounted on the intermediate dielectric layer 114-DL3. In some embodiments, the front-side RDL structure 110 can further include a plurality of redistribution layers 113 and a plurality of contact vias 110a positioned in the intermediate dielectric layer 114-DL3 and contacting redistribution layers 113 of the plurality of redistribution layers 113. In some embodiments, the package structure 100 can further include a plurality of bond pads 110b in the recessed portion R 110 on the intermediate dielectric layer 114-DL3 and respectively contacting the plurality of contact vias 110a, and a plurality of solder bumps 117 respectively positioned on the plurality of bond pads 110b and connecting the IPD 500 to the plurality of bond pads 110b. In some embodiments, the package structure 100 can further include an IPD underfill layer 229 in the recessed portion R 110 between the IPD 500 and the front-side RDL structure 110, and an underfill layer 229 in the recessed portion R110 bottom surface R B and a barrier ring 602 configured to inhibit and / or prevent the spread of the IPD underfill layer 229. In some embodiments, the front side RDL structure 110 can include a board side surface and a recessed portion R 110 may be in the board side surface. In some embodiments, the package structure 100 can further include a UBM dam structure 604 on the board side surface of the front side RDL structure 110 and configured to inhibit and / or prevent the spread of the IPD underfill layer 229. 110 In some embodiments, a distance between the board side surface of the front side RDL structure 110 and the board side surface of the IPD 500 can be 90 pm or less than 90 pm. In one embodiment, the package structure 100 can further include a ball grid array (BGA) including a plurality of solder balls 116 on the board side surface of the front side RDL structure 110, where the IPD 500 can be positioned adjacent to the plurality of solder balls 116. In some embodiments, a distance between the board side surface of the front side RDL structure 110 and an end of the plurality of solder balls 116 can be 120 pm or less than 120 pm. In some embodiments, a width of the recessed portion R 110 may be at least 1.5 times a width of the IPD 500.

[0146] Referring again to FIG. 1A to FIG. 6 , a method of forming the package structure 100 can include forming a molding portion 115 including the lower encapsulant layer 140, the plurality of perforations 145 in the lower encapsulant layer 140, and the first semiconductor die 120 in the lower encapsulant layer 140; forming a front side redistribution layer (RDL) structure 110 on the molding portion 115 including the recessed portion R 110 , where the plurality of perforations 145 are configured to electrically couple the front side RDL structure 110 to the upper package; and attaching an integrated passive device (IPD) 500 to the front side RDL structure 110 in the recessed portion R 110 , where the IPD 500 can be electrically coupled to the first semiconductor die 120.

[0147] In some embodiments, the formation of the front side RDL structure 110 can include depositing a plurality of dielectric layers 114 on the molding portion 115, and etching a distal dielectric layer 114-DL4 of the plurality of dielectric layers 114 to form the recessed portion R 110 In some embodiments, the method can further include forming a UBM dam structure 604 on the board side surface of the front side RDL structure 110 and configured to inhibit and / or prevent the spread of the IPD underfill layer 229. 110forming an IPD underfill layer 229 in the recessed portion R 110 and a barrier ring 602 on the bottom surface R B of the recessed portion R 110 , wherein the barrier ring 602 can be configured to arrest and / or prevent the spread of the IPD underfill layer 229. In some embodiments, the method can further include forming an IPD underfill layer 229 that fills the recessed portion R 110 between the IPD 500 and the front side RDL structure 110, forming an under bump metal (UBM) dam structure 604 on the board side surface of the front side RDL structure 110, wherein the UBM dam structure 604 can be configured to arrest and / or prevent the spread of the IPD underfill layer 229. In some embodiments, the method can further include forming a plurality of solder balls 116 on the board side surface of the front side RDL structure 110, wherein the distance between the board side surface of the front side RDL structure 110 and the end of the plurality of solder balls 116 can be 120 pm or less than 120 pm.

[0148] Referring again to FIGS. 1 to FIG. 6 , the semiconductor package 550 can include a package substrate 510, a semiconductor device 400, 600 including the package structure 100 on the package substrate 510, and a package underfill layer 529 between the package substrate 510 and the semiconductor device 400, 600. The package structure 100 includes a front side redistribution layer (RDL) structure 110, a lower encapsulant layer 140 on the front side RDL structure 110 and including a plurality of vias 145 configured to electrically couple the front side RDL structure 110 to an upper package, a first semiconductor die 120 on the front side RDL structure 110 and in the lower encapsulant layer 140, and an integrated passive device (IPD) 500 attached to the front side RDL structure 110 in the recessed portion R 110 .

[0149] In one embodiment, the semiconductor package 550 can further include an IPD underfill layer 229 in the recessed portion R 110 between the IPD 500 and the front side RDL structure 110, wherein the package underfill layer 529 is on the IPD underfill layer, and a diffusion prevention structure 602, 604 on the front side RDL structure 110 and configured to arrest and / or prevent the spread of the IPD underfill layer 229.

[0150] The foregoing outlines features of several embodiments so that those skilled in the art can better understand the present disclosure presented herein. Those skilled in the art should appreciate that they can readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and / or achieving the same advantages of the embodiments introduced herein without departing from the spirit and scope of the present disclosure. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that various changes, substitutions, and alterations can be made herein without departing from the spirit and scope of the present disclosure.

Claims

1. A package structure, characterized by, including: a front side redistribution layer structure including a recessed portion; a lower encapsulant layer on the front side redistribution layer structure and including a plurality of vias configured to electrically couple the front side redistribution layer structure to an upper package; a first semiconductor die on the front side redistribution layer structure and in the lower encapsulant layer; and an integrated passive device connected to the front side redistribution layer structure in the recessed portion and electrically coupled to the first semiconductor die. The front side redistribution layer structure includes a plurality of dielectric layers, the recessed portion is in a distal dielectric layer of the plurality of dielectric layers, and a depth of the recessed portion is substantially equal to a thickness of the distal dielectric layer.

2. The package structure of claim 1, wherein, The plurality of dielectric layers includes an intermediate dielectric layer adjacent to the distal dielectric layer, and the integrated passive device is mounted on the intermediate dielectric layer.

3. The package structure of claim 2, wherein, The front side redistribution layer structure further includes a plurality of redistribution layers and a plurality of contact vias in the intermediate dielectric layer and contacting redistribution layers of the plurality of redistribution layers.

4. The package structure of claim 3, wherein, further including:

5. The package structure of claim 1, wherein, an integrated passive device underfill layer in the recessed portion between the integrated passive device and the front side redistribution layer structure; and a barrier ring on a bottom surface of the recessed portion and configured to inhibit spreading of the integrated passive device underfill layer. The front side redistribution layer structure includes a board side surface, and the recessed portion is in the board side surface. further including:

6. The package structure of claim 1, wherein, an integrated passive device underfill layer filling the recessed portion between the integrated passive device and the front side redistribution layer structure; and 7. The package structure of claim 6, wherein, a bump under metal dam structure on a board side surface of the front side redistribution layer structure and configured to inhibit spreading of the integrated passive device underfill layer. A width of the recessed portion is at least 1.5 times a width of the integrated passive device. including: a package substrate; 8. The package structure of claim 1, wherein, a semiconductor device including a package structure on the package substrate, the package structure including:

9. A semiconductor package, characterized by, a front side redistribution layer structure including a recessed portion; a lower encapsulant layer on the front side redistribution layer structure and including a plurality of vias configured to electrically couple the front side redistribution layer structure to an upper package; a first semiconductor die on the front side redistribution layer structure and in the lower encapsulant layer; and an integrated passive device attached to the front side redistribution layer structure in the recessed portion and electrically coupled to the first semiconductor die; and a package underfill layer between the package substrate and the semiconductor device. further including: an integrated passive device underfill layer in the recessed portion between the integrated passive device and the front side redistribution layer structure, wherein the package underfill layer is on the integrated passive device underfill layer; a diffusion prevention structure on the front side redistribution layer structure and configured to inhibit spreading of the integrated passive device underfill layer.

10. The semiconductor package of claim 9, wherein, ​ ​ ​ ​

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