Multi-machine communication system based on serial communication bus and liquid crystal panel detection system

Abstract

The embodiment of the utility model relates to a multi-machine communication system based on a serial communication bus and a liquid crystal panel detection system. The multi-machine communication system comprises a first host; the second host is connected with the plurality of slaves through a second control circuit, the second control circuit comprises a bus control module and a plurality of switch branches, the bus control module comprises an input end and a plurality of output ends, the input end is connected with the second host through a serial communication bus, and the control ends of the switch branches are connected with the corresponding output ends. Each slave is in communication connection with the second host through the corresponding switch branch; and when the first host and the second host access the same slave, the second host is configured to output a target signal, so that the output end corresponding to the bus control module outputs a level signal, and the level signal triggers the switch branch corresponding to the same slave to be switched from a closed state to an open state, so that the second host is disconnected from the same slave. According to the technical scheme, the conflict problem caused by multi-host communication competition can be solved.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of communication technology, in particular to a multi-machine communication system based on a serial communication bus and a liquid crystal panel detection system. BACKGROUND

[0002] In industrial production, a host machine often needs to control I2C (Inter-Integrated Circuit) devices or SPI (Serial Peripheral Interface) devices on product equipment. In I2C communication, the host machine sends data to slave devices in one-to-many mode, and the I2C bus protocol supports expansion of 127 slaves, and different slaves are distinguished by unique hardware addresses of each slave. Therefore, the host machine selects a slave for communication according to different I2C addresses, and the master device selects a communication object by address.

[0003] When multiple host machines simultaneously send signals to the same slave, theoretically, the I2C hard-wire arbitration mechanism can automatically determine and filter out the only valid host machine, thereby avoiding bus signal conflicts. However, in the practice of liquid crystal panel detection, it is found that when multiple host machines simultaneously access the same slave, a black screen or abnormal picture phenomenon occurs, which affects the normal operation of the system. The slave can be an EEPROM, an A / D or D / A converter, etc. In SPI communication, similar problems exist when multiple host machines simultaneously access the same slave. CONTENT OF THE UTILITY MODEL

[0004] Therefore, an embodiment of the present application provides a multi-machine communication system based on a serial communication bus and a liquid crystal panel detection system to solve at least one problem in the background art.

[0005] In a first aspect, an embodiment of the present application provides a multi-machine communication system based on a serial communication bus, comprising:

[0006] a first host machine;

[0007] a second host machine connected to multiple slaves through a second control circuit, wherein the second control circuit comprises a bus control module and multiple switch branches, the bus control module comprises an input end and multiple output ends, the input end is connected to the second host machine through a serial communication bus, the control end of each switch branch is connected to a corresponding output end, and each slave is in communication connection with the second host machine through a corresponding switch branch.

[0008] When the first host and the second host access the same slave at the same time, the second host is configured to output a target signal, so that a corresponding output terminal of the bus control module outputs a level signal, which triggers the corresponding switch branch of the same slave to switch from a closed state to an open state, so as to disconnect the second host from the same slave.

[0009] In an optional embodiment, the serial communication bus comprises an I2C bus and / or an SPI bus.

[0010] In an optional embodiment, the switch branch comprises a driver and a relay, an input terminal of the driver is connected with a corresponding output terminal of the bus control module, an output terminal of the driver is connected with a positive voltage through a coil of the relay, a common terminal of the relay is connected with the second host through the serial communication bus, and each slave is connected with a normally open contact of the corresponding relay through the serial communication bus.

[0011] In an optional embodiment, the driver comprises an NPN transistor, a collector of the transistor is connected with the positive voltage through the coil of the relay, an emitter of the transistor is connected with the ground, and a base of the transistor is connected with the corresponding output terminal of the bus control module through a resistor R1 and connected with the ground through a resistor R2.

[0012] In an optional embodiment, the bus control module comprises an I / O expansion chip, the I / O expansion chip comprises a plurality of collector open pins, and the base of the transistor is connected with a corresponding collector open pin through the resistor R1.

[0013] In an optional embodiment, when the serial communication bus is an I2C bus, an SDA pin of the second host is connected with a first movable contact of the relay, an SCL pin of the second host is connected with a second movable contact of the relay, an SDA pin of the slave is connected with a first normally open contact of the relay, and an SCL pin of the slave is connected with a second normally open contact of the relay; and / or,

[0014] When the serial communication bus is an SPI bus, a CS pin of the second host is connected with a movable contact of the relay, and a CS pin of the slave is connected with a normally open contact of the relay.

[0015] In an optional embodiment, the first host is directly connected with at least one slave through the serial communication bus, and / or the first host is connected in communication with at least one slave through a first control circuit.

[0016] In combination with the first aspect of the present application, in an optional implementation, the system further comprises:

[0017] A third host, which is communicatively connected with the second host through a corresponding switch branch, and is configured as a system master or a system slave.

[0018] In combination with the first aspect of the present application, in an optional implementation, the first host is the third host.

[0019] In the second aspect, the embodiments of the present application provide a liquid crystal panel detection system, which comprises the multi-host communication system based on the serial communication bus as described in the first aspect.

[0020] The multi-host communication system based on the serial communication bus and the liquid crystal panel detection system provided by the embodiments of the present application can set a second control circuit between the second host and the plurality of slaves, wherein the second control circuit comprises a bus control module and a plurality of switch branches, each slave is connected with the bus control module through a switch branch, the bus control module can output a high or low level signal from a corresponding output end according to a command sent by the second host, the high or low level signal controls the conduction or isolation of the corresponding switch branch, wherein the first host and the second host can access a certain slave, when the first host communicates with the slave, if the second host also accesses the slave, the second host can discover that the first host is accessing the slave, and then sends a target command to the bus control module, the corresponding output end of the bus control module outputs a corresponding level signal, the level signal triggers the switch branch connected with the slave to be disconnected, at this time, the communication between the second host and the slave is disconnected, the isolation control of the second host can be realized, the access of the first host to the slave is prevented from being interfered by the second host, and the conflict problem caused by the communication competition of multiple hosts in practice is effectively solved.

[0021] Additional aspects and advantages of the present application will be made apparent by the following description and the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0022] The accompanying drawings, which are included to provide a further understanding of the present application, constitute a part of the present application, illustrate the illustrative embodiments of the present application and the description thereof, and serve to explain the present application, and do not constitute improper limitations on the present application. In the drawings:

[0023] Figure 1 A structural schematic diagram of the multi-host communication system based on the serial communication bus provided by an embodiment of the present application;

[0024] Figure 2 A structural schematic diagram of the connection between the first host and the slave in an embodiment of the present application;

[0025] Figure 3 FIG. 6 is a schematic diagram of a structure of a switch branch in an embodiment of the present application;

[0026] Figure 4 FIG. 7 is a schematic diagram of a structure of a second control circuit in an embodiment of the present application;

[0027] Figure 5 FIG. 8 is a schematic diagram of a structure of a bus control module in an embodiment of the present application;

[0028] Figure 6 FIG. 9 is another schematic diagram of a structure of a multi-machine communication system based on a serial communication bus in an embodiment of the present application. DETAILED DESCRIPTION

[0029] In order to make the technical solutions and the beneficial effects of the present application more apparent and understandable, the technical solutions in the embodiments of the present application will be described clearly and completely below by way of listing specific embodiments. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without any creative effort fall within the scope of protection of the present application.

[0030] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present application belongs. The terminology used in the description of the present application solely for the purpose of describing the specific embodiments of the present application, and is not intended to limit the present application.

[0031] It can be understood that the terms "first", "second", and the like as used in the present application can be used herein to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish the first element from another element. For example, without departing from the scope of the present application, a first resistor can be called a second resistor, and similarly, a second resistor can be called a first resistor. The first resistor and the second resistor are both resistors, but they are not the same resistor. When "first" is described, it does not necessarily mean that "second" exists; when "second" is discussed, it does not necessarily mean that the first element, component, region, layer, or part exists in the present application. As used herein, the singular forms "a", "an", and "the" can also be intended to include the plural forms, unless the context clearly indicates otherwise. The meaning of "a plurality of" is two or more, unless otherwise specifically limited. It should also be understood that the term "comprising", when used in the specification, determines the presence of the stated features, but does not exclude the presence or addition of one or more other features. As used herein, the term "and / or" includes any and all combinations of the associated listed items.

[0032] It can be understood that, in the context of the present application, "connection" means that the connected end and the connected end have mutual electrical signal or data transmission, which can be understood as "electrical connection", "communication connection" and the like. In the context of the present application, "A is directly connected to B" means that A and B do not include other components except wires.

[0033] Embodiments of the present application provide a multi-machine communication system based on a serial communication bus, which is applied to liquid crystal panel detection and supports I2C communication and SPI communication. The serial communication bus can be an I2C bus and / or an SPI bus. Generally, the multi-machine communication system supports I2C communication or SPI communication, and in some specific cases, it also supports I2C communication and SPI communication. The multi-machine communication can be the communication between a host and a slave, or the communication between hosts when the host is set as a system slave.

[0034] In some embodiments, as shown in Figure 1 The multi-machine communication system includes a first host and a second host.

[0035] In at least one embodiment, the first host can be directly connected to at least one slave through the serial communication bus.

[0036] Taking the I2C bus as an example, the I2C bus includes an SDA line and an SCL line. When there is one first host, the first host can have a device A1, the slave can have a device a1, a device a2 and a device a3, the SDA pins of the device A1 are all connected to the SDA line, the SCL pins of the device A1 are all connected to the SCL line, the SDA pins of the device a1, the device a2 and the device a3 are all connected to the SDA line, and the SCL pins of the device a1, the device a2 and the device a3 are all connected to the SCL line. In this embodiment, only two lines (the SDA line and the SCL line) are used to realize multi-machine communication between the host and the slave. As shown in Figure 2 When there are multiple first hosts, for example, the first host has a device A1 and a device A2, both the device A1 and the device A2 can access the device a1. Based on the I2C arbitration mechanism, when the device A1 and the device A2 send signals to the I2C bus at the same time, the hardware logic can automatically filter the only valid host. However, in the practice of liquid crystal panel detection, when the device A1 and the device A2 are connected to the I2C bus at the same time, the screen of the display panel often appears black or abnormal, so there is still a conflict situation of mutual interference when the device A1 and the device A2 compete for the I2C bus at the same time.

[0037] In some embodiments, as shown in Figure 1As shown, the second host connects multiple slaves through the second control circuit, and the first host and the second host communicate with the required slave according to the requirement. The second control circuit includes a bus control module and multiple switch branches. The bus control module includes an input end and multiple output ends. The input end is connected with the second host through a serial communication bus. The control end of the switch branch is connected with the corresponding output end. Each slave is connected with the second host through the corresponding switch branch.

[0038] In the embodiment, the second control circuit is provided between the second host and the multiple slaves. The second control circuit mainly includes a bus control module and multiple switch branches. Each slave is connected with the second host through a switch branch. The bus control module has multiple output pins. Each output pin can control the on-off of a corresponding switch branch.

[0039] Further, the switch branch includes a driver and a relay. The input end of the driver is connected with the corresponding output end of the bus control module. The output end is connected with the positive voltage through the relay coil. The common end of the relay is connected with the second host through the serial communication bus. Each slave is connected with the normally open contact of the corresponding relay through the serial communication bus. When the bus control module outputs a level signal to the driver through a certain output pin, the driver is triggered to drive the relay to turn on or off. Generally, the switch branch controls the on-off between the slave and the second host. When the second host needs to access a certain slave, the corresponding switch branch is turned on. If the relay in the switch branch is a normally open switch, in this case, multiple slaves can be prevented from being connected to the I2C bus at the same time. A second host does not need to carry too many online slaves at the same time, and the situation that the number of online slaves is too large to need to reduce the speed, for example, from 400 kbps to 100 kbps, can be avoided. Therefore, the slave is connected with the normally open contact of the relay.

[0040] That is, when the second host needs to access a certain slave, the second host is configured to output a certain specific signal, so that the corresponding output end of the bus control module outputs a corresponding level signal. The corresponding level signal triggers the corresponding switch branch of the slave to switch from the normally off state to the closed state. At this time, the first host and the slave do not communicate.

[0041] As shown in Figure 3 and Figure 4 As shown in Figure 4 Q1 and Q2 in the middle are different drivers, and K1 and K2 are different relays. As shown in Figure 3As shown, the driver Q can be an NPN transistor, the collector C of the transistor is connected to the positive voltage SYS_5V through the relay coil, a reverse parallel diode D is connected to the relay coil, the emitter E is connected to the ground, the base B is connected to the corresponding output end of the bus control module through the resistor R1, and the base B is connected to the ground through the resistor R2. In addition, the bus control module includes an I / O expansion chip, the I / O expansion chip includes a plurality of open collector pins (OC pins), and the base B of the transistor is connected to the corresponding open collector pin through the resistor R1.

[0042] When the serial communication bus is an I2C bus, the I2C bus has an SDA line and an SCL line, and correspondingly, the contacts of the relay should have two groups. The slave and the second master are connected through the relay in the following specific form: the SDA pin of the second master is connected to the first movable contact of the relay, and the SCL pin is connected to the second movable contact of the relay; the SDA pin of the slave is connected to the first normally open contact of the relay, and the SCL pin is connected to the second normally open contact of the relay.

[0043] As shown in Figure 3 When the relay K needs to be closed, the end of the relay coil away from the positive voltage SYS_5V should be connected to the ground, and then the level of the base B of the NPN transistor is high, that is, the OC pin needs to output a high-level signal at this time. Similarly, when the relay K needs to be disconnected, the OC pin should output a low-level signal. As shown in Figure 3 The OPEN signal or the CLOSE signal output by the OC pin is for the internal transistor of the chip, and the OPEN signal represents that the internal transistor is cut off. At this time, the OC pin can output a high-level signal through a pull-up resistor, so that the driver Q is turned on, and the relay K is powered on to connect the I2C bus (OUT_SDA and OUT_SCL) of the slave and the I2C bus (IN_SDA and IN_SCL) of the second master.

[0044] In addition, the first master is not limited to being directly connected to the slave through the I2C bus. In some embodiments, the first master can be connected to at least one slave through a first control circuit. The first master and the second master are two different independent devices, and the first master can be directly connected to the slave through the I2C bus, or a control circuit can be arranged on the I2C bus to communicate with the second master in a similar connection form.

[0045] In some embodiments, the multi-machine communication system can include a third host, which is communicatively connected with the second host through a corresponding switch branch, and the third host is set as a system master or a system slave. In the multi-machine communication, the second host and the third host cannot simultaneously serve as the master for communication, and the third host can be set as a system slave to realize the communication between the second host and the third host, thereby realizing the access of the second host to the third host. In some specific cases, the first host can also be referred to as the third host, and at this time, the first host is connected with a switch branch in the second control circuit.

[0046] In some embodiments, when the first host and the second host access the same slave, the second host is configured to output a target signal, so that a corresponding output terminal of the bus control module outputs a level signal, and the level signal triggers the corresponding switch branch of the same slave to switch from a closed state to an open state, so as to disconnect the second host from the same slave, thereby realizing the isolation control of the second host in the system.

[0047] Taking the second host 3 device A3 as an example, the I2C bus is connected with the device A1 and the device A3, the device A3 can know that the device A1 and the device a1 are communicating according to the I2C arbitration mechanism, the device A3 generates a corresponding command according to the current situation, the I / O expansion chip receives the command through the I2C bus, and outputs a low-level signal at the corresponding OC pin, the NPN transistor serves as a driver, the base thereof is in a low-level state, the collector and the emitter of the transistor are cut off, and the collector and the emitter are approximately open, no continuous current passes through the relay coil, the coil is de-energized, the moving contact and the normally open contact of the relay are disconnected, that is, the relay is disconnected, and then the communication between the device A3 and the device a1 is interrupted, at this time, only the device A1 communicates with the device a1, thereby realizing that only one host accesses the slave at the same time, and avoiding bus conflicts.

[0048] In order to better understand the embodiments of the present application, the following will take the serial communication bus as an example to introduce in detail.

[0049] As shown in Figures 3 to 6 The bus control module is a general remote bus control module CH423S, the I2C bus of the CH423S accesses an external detection device serving as a second host, a PMIC (Power Management Integrated Circuit, power management integrated circuit) on a TCON (Timing Controller, timing controller) board serves as a first host, the PMIC reads data of an EEPROM, a FLASH or other storage chips serving as a slave under a certain condition, and the external detection device can access the PMIC, the EEPROM, the FLASH or other storage chips.

[0050] AsFigure 4 As shown, it is assumed that the EEPROM matches the OC0 pin, the driver Q1 and the relay K1 of the CH423S. In one aspect, when the PMIC accesses the EEPROM, the I2C bus is simultaneously connected to the external detection device and the PMIC, the external detection device actively pulls down the OC0 pin, the low-level signal output by the OC0 pin makes the driver Q1 cut off, the relay K1 is disconnected, and the bus connection between the external detection device and the EEPROM is disconnected, that is, the external detection device is isolated, realizing the isolation control in the case of multiple hosts accessing the same slave, realizing that only one host accesses the slave at the same time, and avoiding bus conflicts.

[0051] On the other hand, as shown, when the PMIC does not access the EEPROM, the external detection device needs to interact with the EEPROM, the external detection device sends a command to the CH423S, the OC0 pin outputs the OPEN_I2C_1 signal, at this time the internal transistor in the CH423S cuts off, the OC0 pin outputs a high-level signal through the pull-up resistor, the high-level signal makes the driver Q1 conduct, the relay K1 is grounded away from the SYS_5V end, there is a current flowing through the coil of the relay K1, the relay K1 is powered on to conduct the external detection device and the EEPROM, thereby realizing the communication between the external detection device and the EEPROM. Figure 3

[0052] In addition, when multiple same slave devices are connected to a host, the same slave device addresses are the same, which is easy to cause communication abnormalities. Optionally, multiple bus control modules are connected to the host, and each slave device can be distinguished by being connected to different bus control modules.

[0053] In some embodiments, when the serial communication bus is an SPI bus, the CS pin of the second host is connected to the movable contact of the relay, and the CS pin of the slave is connected to the normally open contact of the relay. The SPI bus includes an SCLK line, a MOSI line, a MISO line and a CS line, the CS line is a chip selection line, the bus control module is connected to the second host through the SPI bus, wherein the bus control module and the second host share the SCLK line, the MOSI line and the MISO line, and the second host generally needs to reserve an additional CS pin to connect the bus control module. The second host and the slave share the SCLK line, the MOSI line and the MISO line, and the CS pin of the second host is connected to the CS pin of the slave through the relay. Compared with connecting the SCLK line, the MOSI line, the MISO line and the CS line to the relay, this connection mode saves the wiring harness. In addition, the control of the second control circuit when the serial communication bus is an SPI bus is similar to the principle of the I2C bus, and therefore will not be described in detail here.

[0054] ​The embodiment of the present application further provides a liquid crystal panel detection system, comprising the multi-machine communication system based on the serial communication bus as described above.

[0055] The technical features of the above-described embodiments can be combined in any manner. To make the description concise, all possible combinations of the technical features in the above-described embodiments are not described, but as long as the combinations of the technical features do not exist in contradiction, they shall be considered within the scope of the present disclosure.

[0056] The above-described embodiments only express several implementation manners of the present application, and the description is relatively specific and detailed, but it shall not be understood as a limitation on the patent application scope. It should be pointed out that, for those skilled in the art, several modifications and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the patent protection scope of the present application shall be subject to the appended claims.

Claims

1. A multi-computer communication system based on a serial communication bus, characterized by include: First host; The second host is connected to multiple slave devices through a second control circuit. The second control circuit includes a bus control module and multiple switch branches. The bus control module includes an input terminal and multiple output terminals. The input terminal is connected to the second host through a serial communication bus. The control terminal of each switch branch is connected to the corresponding output terminal. Each slave device communicates with the second host through a corresponding switch branch. When the first host and the second host access the same slave device, the second host is configured to output a target signal, causing the bus control module to output a level signal at the corresponding output terminal. This level signal triggers the corresponding switch branch of the same slave device to switch from a closed state to an open state, thereby causing the second host to disconnect from the same slave device.

2. The system of claim 1, wherein, The serial communication bus includes an I2C bus and / or an SPI bus.

3. The system of claim 1, wherein, The switching branch includes a driver and a relay. The input terminal of the driver is connected to the corresponding output terminal of the bus control module. The output terminal is connected to a positive voltage through the relay coil. The common terminal of the relay is connected to the second master through the serial communication bus. Each slave device is connected to the normally open contact of the corresponding relay through the serial communication bus.

4. The system of claim 3, wherein, The driver includes an NPN transistor. The collector of the transistor is connected to a positive voltage through the relay coil, the emitter is grounded, the base is connected to the corresponding output terminal of the bus control module through resistor R1, and the base is grounded through resistor R2.

5. The system of claim 4, wherein, The bus control module includes an I / O expansion chip, which includes multiple open-collector pins. The base of the transistor is connected to the corresponding open-collector pin through the resistor R1.

6. The system of claim 3, wherein, When the serial communication bus is an I2C bus, the SDA pin of the second master is connected to the first moving contact of the relay, and the SCL pin is connected to the second moving contact of the relay; the SDA pin of the slave is connected to the first normally open contact of the relay, and the SCL pin is connected to the second normally open contact of the relay; and / or, When the serial communication bus is an SPI bus, the CS pin of the second master is connected to the moving contact of the relay, and the CS pin of the slave is connected to the normally open contact of the relay.

7. The system of claim 1, wherein, The first host is directly connected to at least one slave device via the serial communication bus, and / or the first host is communicatively connected to at least one slave device via a first control circuit.

8. The system of claim 1, wherein, Also includes: The third host is connected to the second host via a corresponding switch branch, and the third host is configured as a system host or a system slave.

9. The system of claim 8, wherein, The first host is the third host.

10. A liquid crystal panel inspection system characterized by comprising: Including the multi-machine communication system based on a serial communication bus as described in any one of claims 1 to 9.

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