Multi-source input watchdog circuit
By using a multi-source input watchdog circuit structure, the limitations of monitoring a single chip and the problem of fixed delay thresholds in existing technologies are solved, enabling efficient monitoring and reset of multi-chip architectures and improving the stability and reliability of the system.
Patent Information
- Application Number
- CN202520064229.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-10
- Publication Date
- 2025-12-23
- Estimated Expiration
- 2035-01-10
AI Technical Summary
Existing watchdog circuits are limited to monitoring a single microprocessor or system, which increases the complexity and cost of circuit design in multi-chip architectures. They cannot ensure that all chips operate normally at the same time, and the fixed delay threshold affects the stability and reliability of the system.
The watchdog circuit adopts a multi-source input structure, including a clock signal synchronization module, a power supply module, a function integration module, a parallel monitoring module, and a reset module. It monitors multiple chips in parallel through a single-pole multi-channel selection switch and allows adjustment of the delay threshold, enabling simultaneous monitoring and reset of DSP, CPLD, and FPGA.
It reduces circuit costs and footprint, improves monitoring efficiency for multi-chip architectures, ensures timely fault detection, and enhances system stability and reliability.
Smart Images
Figure CN223712158U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The utility model belongs to circuit technical field, more specifically, relate to a kind of watchdog circuit based on multi-source input. BACKGROUND
[0002] With the continuous development of integrated circuit technology, Digital signal processor (Digital signal processor, for short DSP), Complex programmable logic device (Complex programmable logic device, for short CPLD) and Field programmable gate array (Field programmable gate array, for short FPGA) and other programmable logic devices have been widely used in various complex control and signal processing, the stability and reliability of these devices are crucial to the monitored system, and Watchdog circuit as a kind of efficient system monitoring and fault recovery mechanism, its role is to monitor the running state of the monitored system in real time, and timely trigger the monitored system reset when detecting abnormality, to restore the normal operation of the system.
[0003] At present, the existing watchdog technology adopts single monitoring mode, that is, a watchdog circuit is used to monitor a chip, the mode transmits the periodic clock signal generated by the connected chip into the watchdog signal input end (WDI) as the watchdog signal, and connects the output end (WDO) of the watchdog circuit to the reset end (RESET) of the chip, so as to realize the monitoring of single chip, and the design of such watchdog circuit is relatively simple, easy to integrate and test.
[0004] However, the above existing watchdog circuit still has some defects that cannot be ignored:
[0005] 1, the watchdog circuit is limited to monitoring a single microprocessor or system, and has great limitations when facing multi-chip architecture, specifically, the one-to-one monitoring mode (i.e. one watchdog circuit corresponds to one chip) not only greatly increases the complexity of circuit design, but also leads to the increase of circuit cost and the increase of circuit area;
[0006] 2, the watchdog circuit lacks effective mechanism to monitor multiple chips or processor cores simultaneously, and when facing multi-chip architecture, the watchdog circuit cannot ensure that all chips are in normal running state at the same time, thereby increasing the risk of not discovering the fault of the monitored system in time;
[0007] 3、the watchdog circuit delay threshold is fixed, and with the increase of the complexity of the microprocessor and the monitored system, the microprocessor or the monitored system cannot effectively generate and transmit the watchdog feeding signal to the watchdog circuit within a given time, which hinders the monitoring and reset functions of the watchdog circuit, thereby affecting the stability and reliability of the monitored system. Utility model content
[0008] In view of the above defects or improvement needs of the prior art, the utility model provides a kind of watchdog circuit based on multi-source input, its purpose is to, solve the monitoring of the existing watchdog circuit to single microprocessor or system, when facing the architecture of multiple chips, it shows greater limitation, not only greatly increase the complexity of circuit design, also lead to the increase of circuit cost and the increase of circuit occupied area technical problem, and when facing the architecture of multiple chips, traditional watchdog circuit cannot ensure that all chips are in normal operating state simultaneously, thereby increasing the risk of monitored system failure not being discovered in time technical problem, and the delay threshold of existing watchdog circuit is fixed, and with the increase of the complexity of the microprocessor and the monitored system, the microprocessor or the entire monitored system cannot effectively generate and transmit the watchdog feeding signal to the watchdog circuit within a given time, which hinders the monitoring and reset functions of the watchdog circuit, thereby affecting the stability and reliability of the monitored system technical problem.
[0009] To achieve the above object, according to one aspect of the utility model, a kind of multi-source input watchdog circuit, including clock signal synchronization module, power module, functional integrated module, parallel monitoring module, and reset module, clock signal synchronization module and the input end of functional integrated module are electrically connected;
[0010] Power module and the monitoring standby battery voltage end of functional integrated module, voltage output end, power supply voltage end, ground and oscillation output end are electrically connected;
[0011] Parallel monitoring module and the watchdog feeding signal input end of functional integrated module are electrically connected;
[0012] The reset end of functional integrated module and the watchdog signal output end of parallel monitoring module are electrically connected;
[0013] Reset module and the reset output end of functional integrated module are electrically connected.
[0014] Preferably, clock signal synchronization module is the first schmitt trigger inverter, its input end is electrically connected with external clock signal, and the oscillation input end of functional integrated module is electrically connected with output end;
[0015] The first schmitt trigger inverter adopts the schmitt trigger inverter of model 74LS14.
[0016] Preferably, the power module comprises a power supply and a ground wire;
[0017] The power supply is electrically connected to the voltage output end and the power supply voltage end of the function integrated module;
[0018] The ground wire is electrically connected to the monitoring backup battery voltage end, the ground end, and the oscillation output end of the function integrated module.
[0019] Preferably, the function integrated module adopts a watchdog chip with a model of MAX691.
[0020] Preferably, the parallel monitoring module comprises a first single-pole multi-throw channel selection switch, a digital signal processor, a complex programmable logic device, and a field programmable gate array;
[0021] One side of the first single-pole multi-throw channel selection switch is connected to the watchdog signal input end of the function integrated module, and the other side of the first single-pole multi-throw channel selection switch is connected to the general input and output end of the digital signal processor, the periodic signal generation end of the complex programmable logic device, and the periodic signal generation end of the field programmable gate array;
[0022] The reset ends of the digital signal processor, the complex programmable logic device, and the field programmable gate array are electrically connected to the watchdog signal output end of the function integrated module.
[0023] Preferably, the first single-pole multi-throw channel selection switch adopts a single-pole three-throw switch with a model of MTS-103;
[0024] The digital signal processor adopts a DSP chip with a model of TMS320F2810PBKA;
[0025] The complex programmable logic device adopts a CPLD chip with a model of HMC853LC3CTR;
[0026] The field programmable gate array adopts a FPGA chip with a model of XC3S50A-4VQG100C.
[0027] Preferably, the reset module comprises a first Schottky diode, a second Schottky diode, a first resistor, a first switch, and a power supply;
[0028] The positive pole of the power supply is connected to one end of the first resistor, and the other end of the first resistor branches into two parallel branches;
[0029] In the first branch, the first resistor is connected to the anode of the first Schottky diode, and the cathode of the first Schottky diode is connected to the reset end of the function integrated module, forming a direct reset trigger loop;
[0030] In the second branch, the first resistor is connected to the anode of the second Schottky diode, and the cathode of the second Schottky diode is connected to one side of the first switch, and the other side of the first switch is connected to the ground, forming a manual reset loop.
[0031] Preferably, the first Schottky diode and the second Schottky diode are both BAS85 type Schottky diodes.
[0032] The resistance of the first resistor is 1kΩ.
[0033] The first switch AN1 is a KW12-D428 type push button switch.
[0034] The power supply is 3.3V, and the RS-150-3.3 type power supply is used.
[0035] Overall, compared with the prior art, the above technical scheme conceived by the utility model can achieve the following beneficial effects:
[0036] 1. The utility model adopts a watchdog circuit to monitor multiple programmable logic devices such as digital signal processors (DSP), complex programmable logic devices (CPLD), and field programmable gate arrays (FPGA), thereby reducing costs and saving circuit area. Therefore, the existing watchdog circuit is limited to monitoring a single microprocessor or system, which exhibits great limitations when facing a multi-chip architecture, not only greatly increasing the complexity of circuit design, but also leading to an increase in circuit cost and circuit area.
[0037] 2. The utility model places a single-pole multi-path switch W1 at the watchdog signal input end (WDI) of the MAX691 chip U83, and connects the right side of the single-pole multi-path switch W1 to the DSP, CPLD, and FPGA chips, thereby realizing the function of a watchdog circuit monitoring multiple chips such as DSP, CPLD, and FPGA. Therefore, when facing a multi-chip architecture, the traditional watchdog circuit cannot ensure that all chips are in a normal operating state at the same time, thereby increasing the risk of the monitored system failure not being discovered in time.
[0038] 3, The utility model discloses a programmable logic device such as DSP, CPLD, FPGA produces the periodic clock signal as the dog feeding signal, input to the watchdog signal input end (WDI) of MAX691 chip, and the watchdog signal output end (WDO) of U83 is connected to the reset port (RESET) of programmable logic device such as DSP, CPLD, FPGA, thereby can pass through programmable logic device such as DSP, CPLD, FPGA and adjust the delay threshold of watchdog circuit, therefore can solve the existing watchdog circuit delay threshold is more fixed, and along with the complexity of microprocessor and the monitored system increases, leads to microprocessor or monitored system in the time of being defined, cannot effectively generate and transmit the dog feeding signal to the watchdog circuit, hinders the monitoring and reset function that watchdog circuit plays, thereby influence the stability and reliability of monitored system's technical problem. BRIEF DESCRIPTION OF DRAWINGS
[0039] Figure 1 It is the circuit structure diagram of the watchdog circuit of the utility model based on multi-source input;
[0040] Figure 2 It is the circuit diagram of traditional watchdog circuit;
[0041] Figure 3 It is the structure block diagram of functional integration module in the watchdog circuit of the utility model. DETAILED DESCRIPTION
[0042] In order to make the utility model's purpose, technical scheme and advantage more clearly clear, following combining with the drawing and example, this utility model carries out further detailed explanation. It should be understood that the specific embodiment described here is only used to explain the utility model, and is not used to limit the utility model. Besides, the technical features involved in each embodiment of the utility model described below can be combined with each other as long as they do not conflict with each other.
[0043] As Figure 1 The utility model discloses a kind of multi-source input's watchdog circuit, including clock signal synchronization module 1, power module 2, functional integration module 3, parallel monitoring module 4, and reset module 5.
[0044] The utility model increases parallel monitoring module 4 on the basis of traditional watchdog circuit (as shown in Figure 2 Reset function is added in reset module 5.
[0045] The clock signal synchronization module 1 is electrically connected with the input end (OSC IN) of the function integrated module 3, the power module 2 is electrically connected with the monitoring standby battery voltage end (VBATT), the voltage output end (VOUT), the power supply voltage end (VCC), the ground end (GND) and the oscillation output end (OSC SEL) of the function integrated module 3, the parallel monitoring module 4 is electrically connected with the watchdog feeding signal input end (WDI) of the function integrated module 3, the watchdog signal output end (WDO) of the function integrated module 3 is electrically connected with the reset end (RESET) of the parallel monitoring module 4, and the reset module 5 is electrically connected with the reset output end (RESET OUT) of the function integrated module 3. Electrically connected.
[0046] As shown in Figure 1 The clock signal synchronization module 1 is specifically a first Schmitt trigger inverter U82A, the input end of which is electrically connected with the external clock signal EXTCLK, and the output end of which is electrically connected with the oscillation input end 11 (OSC IN) of the function integrated module 3.
[0047] The first Schmitt trigger inverter U82A is a Schmitt trigger inverter manufactured by Shenzhen Yueshan Sheng Electronics Technology Co., Ltd., and the model number is 74LS14.
[0048] The power module 2 includes a power supply VCC and a ground wire GND, the power supply VCC is electrically connected with the voltage output end 2 (VOUT) and the power supply voltage end 3 (VCC) of the function integrated module 3, and the ground wire GND is electrically connected with the monitoring standby battery voltage end 1 (VBATT), the ground end 4 (GND) and the oscillation output end 8 (OSC SEL) of the function integrated module 3.
[0049] The function integrated module 3 is a watchdog chip manufactured by Yadiano Semiconductor Technology Co., Ltd., and the model number is MAX691, as shown in Figure 3 .
[0050] The parallel monitoring module 4 includes a first single-knife multi-path channel selection switch W1, a digital signal processor DSP_WD, a complex programmable logic device CPLD_WD and a field programmable gate array FPGA_WD.
[0051] One side of the first single-pole multi-path channel switch W1 is connected to the watchdog signal input end 11 (WDI) of the function integrated module 3, and the other side of the first single-pole multi-path channel switch W1 is connected to the general-purpose input / output (GPIO) end of the digital signal processor DSP_WD, the cycle signal generation end of the complex programmable logic device CPLD_WD, and the cycle signal generation end of the field programmable gate array FPGA_WD. The reset ends (RESET) of the digital signal processor DSP_WD, the complex programmable logic device CPLD_WD, and the field programmable gate array FPGA_WD are electrically connected to the watchdog signal output end 14 (WDO) of the function integrated module 3.
[0052] The first single-pole multi-path channel switch W1 is a single-pole three-throw switch manufactured by Dongguan Dongyi Parts Electronics Co., Ltd. and has a model number MTS-103. The digital signal processor DSP_WD is a DSP chip manufactured by Shenzhen Jinhuayang Century Technology Co., Ltd. and has a model number TMS320F2810PBKA. The complex programmable logic device CPLD_WD is a CPLD chip manufactured by Ruinada Technology (Shenzhen) Co., Ltd. and has a model number HMC853LC3CTR. The field programmable gate array FPGA_WD is an FPGA chip manufactured by Shenzhen Dongxinsheng Technology Co., Ltd. and has a model number XC3S50A-4VQG100C.
[0053] The reset module 5 includes a first Schottky diode D1, a second Schottky diode D2, a first resistor R242, a first switch AN1, and a power supply.
[0054] One end of the first resistor R242 is connected to the positive pole of the power supply. The other end of the first resistor R242 branches into two parallel branches. In the first branch, the first resistor R242 is connected to the anode of the first Schottky diode D1, and the cathode of the first Schottky diode D1 is connected to the reset end 15 (RESET) of the function integrated module 3, thereby forming a direct reset trigger loop. In the second branch, the first resistor R242 is connected to the anode of the second Schottky diode D2, and the cathode of the second Schottky diode D2 is connected to one side of the first switch AN1. The other side of the first switch AN1 is connected to the ground, thereby forming a manual reset loop. By controlling the first switch AN1, the current in the second branch can be turned on or turned off, thereby manually resetting the function integrated module 3.
[0055] The first Schottky diode D1 and the second Schottky diode D2 are BAS85 Schottky diodes manufactured by Kefan Micro Semiconductor (Shenzhen) Co., Ltd.; the first resistor R242 has a resistance of 1 kΩ, and is a resistor manufactured by Shiyang Chaiqiumai Electronic Commerce Co., Ltd.; the first switch AN1 is a button switch with a model number of KW12-D428 and manufactured by Zhejiang Lemar Electrical Co., Ltd.; and the power supply is a power supply with a model number of RS-150-3.3 and manufactured by Shenzhen Norsenmand Machine Manufacturing.
[0056] The working principle of the utility model is that firstly, the power module 2 is electrically connected with the monitoring standby battery voltage terminal (VBATT), voltage output terminal (VOUT), power supply voltage terminal (VCC), ground terminal (GND) and oscillation output terminal (OSCSEL) of the function integrated module 3, thereby supplying power for the multi-source input watchdog circuit. Then, one side of the first single-pole multi-path channel switch W1 is connected to the watchdog signal input terminal 11 (WDI) of the function integrated module 3, thereby enabling the multi-input source watchdog circuit to periodically receive the watchdog signal from the digital signal processor DSP_WD, the complex programmable logic device CPLD_WD and the field programmable gate array FPGA_WD chip. Subsequently, the watchdog signals are selected by the first single-pole multi-path channel switch W1 according to the watchdog signals input by the three chips. Then, the multi-source watchdog circuit uses the clock signal generated by the internal oscillator as the time interval reference. At the same time, the input terminal of the first Schmitt trigger inverter U82A of the clock signal synchronization module 1 is electrically connected with the external clock signal EXTCLK, and the output terminal is electrically connected with the oscillation input terminal 11 (OSC IN) of the function integrated module 3, thereby maintaining the stability of the clock signal by using the signal output by the Schmitt trigger inverter, and judging the received watchdog signal. Finally, if the watchdog signal input terminal 11 (WDI) of the function integrated module 3 does not receive the watchdog signal within the preset time, the function integrated module 3 will output a low-level reset signal through the watchdog signal output terminal 14 (WDO), the signal is sent to the reset end (RESET) of the currently selected one of the digital signal processor DSP_WD, the complex programmable logic device CPLD_WD or the field programmable gate array FPGA_WD through the first single-pole multi-path channel switch W1, so as to force the selected chip to reset, thereby jumping out of the program lock and the error state.
[0057] Those skilled in the art can easily understand that the above description is only a preferred embodiment of the utility model, and is not used to limit the utility model, and any modification, equivalent replacement and improvement made within the spirit and principle of the utility model should be included in the protection scope of the utility model.
Claims
1. A multi-source input watchdog circuit, comprising a clock signal synchronization module, a power supply module, a function integration module, a parallel monitoring module, and a reset module, characterized in that, The clock signal synchronization module and the function integration module are electrically connected at their input terminals; The power module and the functional integration module are electrically connected to the monitoring backup battery voltage terminal, voltage output terminal, power supply voltage terminal, grounding terminal, and oscillation output terminal. The watchdog feed signal input terminals of the parallel monitoring module and the functional integration module are electrically connected; The watchdog signal output terminal of the functional integration module is electrically connected to the reset terminal of the parallel monitoring module; The reset module is electrically connected to the reset output terminal of the function integration module.
2. The multi-source input watchdog circuit according to claim 1, characterized in that, The clock signal synchronization module is the first Schmitt trigger inverter, whose input is electrically connected to the external clock signal and whose output is electrically connected to the oscillation input of the functional integration module. The first Schmitt trigger inverter uses a 74LS14 Schmitt trigger inverter.
3. The multi-source input watchdog circuit according to claim 2, characterized in that, The power module includes power and ground wires; The voltage output terminal and the power supply voltage terminal of the power and function integration module are electrically connected; The ground wire is electrically connected to the monitoring backup battery voltage terminal, ground terminal, and oscillation output terminal of the functional integration module.
4. The multi-source input watchdog circuit according to claim 3, characterized in that, The functional integration module uses a watchdog chip of model MAX691.
5. The multi-source input watchdog circuit according to claim 4, characterized in that, The parallel monitoring module includes a first single-pole multiplexer, a digital signal processor, a complex programmable logic device, and a field-programmable gate array; One side of the first single-pole multiplexer is connected to the watchdog signal input terminal of the functional integration module, and the other side of the first single-pole multiplexer is connected to the general-purpose input / output terminal of the digital signal processor, the periodic signal generation terminal of the complex programmable logic device, and the periodic signal generation terminal of the field-programmable gate array. The reset terminal of a digital signal processor, a complex programmable logic device, and a field-programmable gate array are electrically connected to the watchdog signal output terminal of a functional integration module.
6. The multi-source input watchdog circuit according to claim 5, characterized in that, The first single-pole multi-channel selection switch uses a single-pole three-throw switch of model MTS-103; The digital signal processor uses a DSP chip of model TMS320F2810PBKA; The complex programmable logic device uses a CPLD chip of model HMC853LC3CTR; The field-programmable gate array uses an FPGA chip of model XC3S50A-4VQG100C.
7. The multi-source input watchdog circuit according to claim 6, characterized in that, The reset module includes a first Schottky diode, a second Schottky diode, a first resistor, a first switch, and a power supply; The positive terminal of the power supply is connected to one end of the first resistor, and the other end of the first resistor branches out into two parallel branches. In the first branch, the first resistor is connected to the anode of the first Schottky diode, and the cathode of the first Schottky diode is connected to the reset terminal of the functional integrated module, forming a direct reset trigger circuit; In the second branch, the first resistor is connected to the anode of the second Schottky diode, and the cathode of the second Schottky diode is connected to one side of the first switch. The other side of the first switch is connected to the ground wire, forming a manual reset circuit.
8. The multi-source input watchdog circuit according to claim 7, characterized in that, Both the first and second Schottky diodes are BAS85 Schottky diodes. The resistance of the first resistor is 1 kiloohm; The first switch AN1 is a push-button switch of model KW12-D428; The power supply is 3.3V, and it uses a power supply model RS-150-3.3.