Power-on power supply and enable circuit in motor driving system

Abstract

The utility model discloses a power-on power supply and enable circuit in a motor driving system, which relates to the technical field of motor driving systems and comprises a startup bias module, a real-time voltage and current detection module and an output control module. The real-time voltage and current detection module is used for monitoring the power supply consumption condition of an internal control unit of the motor driving system and synchronously outputting an effective power-on enable signal; the startup bias module is used for shielding a high-voltage component of a power supply signal of an external power supply; and the output control module is used for forming power supply required by an internal control unit of the motor driving system. A real-time voltage and current detection module is used for monitoring the power supply consumption condition of an internal control unit of the motor driving system, and a startup bias module is used for shielding unnecessary high-voltage components in a power supply signal of an external power supply of the motor driving system; and finally, stable and reasonable power supply required by an internal control unit of the motor driving system is formed through the output control module.

Description

Technical Field

[0001] This utility model relates to the field of motor drive system technology, and in particular to a power supply and enable circuit in a motor drive system. Background Technology

[0002] In the design and application of motor drive systems, ensuring a stable and adequate power supply to the internal control unit is crucial. This not only affects the normal startup and operation of the entire system, but also directly impacts its performance and lifespan.

[0003] However, in real-world applications, the external power supply for the application system is often not a constant voltage source under ideal conditions. Its voltage value will vary depending on the specific application scenario, and the effects of factors such as inductor commutation and power transistor switching within the motor drive system itself must also be considered.

[0004] It is evident that the external power supply model of a real motor drive system is equivalent to a voltage source with significant voltage amplitude fluctuations. Therefore, given the large real-time voltage variations, it is crucial to design a reasonable and effective power supply and enable circuit for the internal control unit to ensure the motor drive system can start up and operate normally in a timely manner. Utility Model Content

[0005] To solve the above-mentioned technical problems, this utility model provides a power-on supply and enable circuit in a motor drive system, characterized in that it includes a power-on bias module, a real-time voltage and current detection module, and an output control module, wherein:

[0006] The real-time voltage and current testing module is used to monitor the power consumption of the internal control unit of the motor drive system.

[0007] The power-on bias module is used to shield the high-voltage component of the external power supply signal;

[0008] The output control module is used to provide a stable and reasonable power supply required by the internal control unit of the motor drive system, and the real-time voltage and current detection module can synchronously output an effective power-on enable signal to ensure that the motor drive system is powered on and started in a timely manner.

[0009] Furthermore, the power-on bias module includes a self-biased current source circuit and a common gate circuit.

[0010] Furthermore, the self-biased current source circuit includes a first resistor R1, a first PMOS transistor P1, a second PMOS transistor P2, and a third PMOS transistor P3, wherein:

[0011] The first resistor R1, the drain of the first PMOS transistor P1, the gate of the first PMOS transistor P1, and the gate of the second PMOS transistor P2 are all connected to the gate of the third PMOS transistor P3.

[0012] The source of the first PMOS transistor P1, the source of the second PMOS transistor P2, and the source of the third PMOS transistor P3 are all connected to the port VDD.

[0013] Furthermore, the common-gate circuit includes a first NMOS transistor N1, a second NMOS transistor N2, and a third NMOS transistor N3, wherein:

[0014] The drain of the second PMOS transistor P2, the gate of the third NMOS transistor N3, the drain of the third NMOS transistor N3, and the gate of the second NMOS transistor N2 are all connected to the gate of the first NMOS transistor N1.

[0015] The drain of the third PMOS transistor P3 is connected to the drain of the second NMOS transistor N2;

[0016] The source of the third NMOS transistor N3 is connected to port V1;

[0017] The source of the second NMOS transistor N2 is connected to port V2;

[0018] The source of the first NMOS transistor N1 is connected to port V3.

[0019] Furthermore, the real-time voltage and current verification module includes a conversion circuit, a reference level generation and voltage upper limit clamping circuit, a voltage comparison output circuit, a waveform shaping circuit, and a current amplitude detection circuit.

[0020] Furthermore, the conversion circuit and the reference level generation and voltage upper limit clamping circuit are simultaneously formed by a fourth NMOS transistor N4, a fifth NMOS transistor N5, a sixth NMOS transistor N6, and a seventh NMOS transistor N7 connected in series.

[0021] Furthermore, the voltage comparison output circuit includes an eighth NMOS transistor N8, a ninth NMOS transistor N9, a tenth NMOS transistor N10, and an eleventh NMOS transistor N11, wherein:

[0022] The drain of the seventh NMOS transistor N7, the gate of the seventh NMOS transistor N7, the gate of the eighth NMOS transistor N8, the gate of the ninth NMOS transistor N9, the gate of the tenth NMOS transistor N10, and the gate of the eleventh NMOS transistor N11 are all connected to the source of the sixth NMOS transistor N6.

[0023] The sources of the seventh NMOS transistor N7, the eighth NMOS transistor N8, the ninth NMOS transistor N9, the tenth NMOS transistor N10, the eleventh NMOS transistor N11, the fifteenth NMOS transistor N15, and the sixteenth NMOS transistor N16 are all connected to the port GND.

[0024] Furthermore, the waveform shaping circuit includes a twelfth NMOS transistor N12, a thirteenth NMOS transistor N13, a fourteenth NMOS transistor N14, a fifteenth NMOS transistor N15, a sixteenth NMOS transistor N16, a fourth PMOS transistor P4, a fifth PMOS transistor P5, and a first capacitor C1, wherein:

[0025] The drain of the tenth NMOS transistor N10 and the drain of the eleventh NMOS transistor N11 are both connected to the source of the twelfth NMOS transistor N12;

[0026] The source of the thirteenth NMOS transistor N13 and the source of the fourteenth NMOS transistor N14 are both connected to the drain of the fifteenth NMOS transistor N15;

[0027] The drains of the eighth NMOS transistor N8, the ninth NMOS transistor N9, the twelfth NMOS transistor N12, the lower end of the first capacitor C1, the gate of the thirteenth NMOS transistor N13, the gate of the fifteenth NMOS transistor N15, and the gate of the fourth PMOS transistor P4 are all connected to port V2.

[0028] The upper end of the first capacitor C1, the source of the fourth PMOS transistor P4, the drain of the fourteenth NMOS transistor N14, and the source of the fifth PMOS transistor P5 are all connected to port V3.

[0029] The drain of the fifth PMOS transistor P5 and the drain of the sixteenth NMOS transistor N16 are both connected to port V4.

[0030] The drain of the fourth PMOS transistor P4, the drain of the thirteenth NMOS transistor N13, the gate of the fourteenth NMOS transistor N14, the gate of the fifth PMOS transistor P5, the gate of the sixteenth NMOS transistor N16, and the gate of the twelfth NMOS transistor N12 are all connected to the port VEN.

[0031] Furthermore, the current amplitude detection circuit includes a first diode D1, which is connected to port V3.

[0032] Furthermore, the output control module includes a sixth PMOS transistor P6, wherein:

[0033] The source of the sixth PMOS transistor P6 is connected to port V3;

[0034] The gate of the sixth PMOS transistor P6 is connected to port V4;

[0035] The drain of the sixth PMOS transistor P6 is connected to port VOUT.

[0036] Compared with the prior art, the embodiments of this utility model have the following beneficial effects:

[0037] When the real-time power supply voltage of the external power supply to the motor drive system fluctuates significantly, the real-time voltage and current detection module monitors the power consumption of the internal control unit of the motor drive system. The power-on bias module shields the external power supply signal of the motor drive system from unnecessary high-voltage components. Finally, the output control module forms a stable and reasonable power supply required by the internal control unit of the motor drive system. At the same time, the real-time voltage and current detection module will also output an effective power-on enable signal to ensure that the motor drive system can be powered on in a timely manner. Attached Figure Description

[0038] Figure 1 This is a schematic diagram of the principle disclosed in the embodiment of this utility model;

[0039] Figure 2 This is a circuit schematic diagram disclosed in an embodiment of the present utility model.

[0040] In the picture:

[0041] 10. Power-on bias module; 20. Real-time voltage and current testing module; 30. Output control module. Detailed Implementation

[0042] To make the technical solutions and effects of this utility model clearer, the technical solutions of this utility model will be clearly and completely described below with reference to the accompanying drawings in the embodiments. Obviously, the described embodiments are some embodiments of this utility model, but not all embodiments.

[0043] This utility model aims to provide a power supply and enable circuit in a motor drive system, which ensures a stable and reasonable power supply to the internal control unit of the motor drive system when the real-time power supply voltage of the external power supply to the motor drive system changes significantly, and at the same time outputs an effective power-on enable signal to ensure that the motor drive system can be powered on and started in a timely manner.

[0044] Please refer to Figure 1 The power supply and enable circuit in the motor drive system provided by this utility model mainly includes a power-on bias module 10, a real-time voltage and current detection module 20, and an output control module 30.

[0045] The power-on bias module 10 is connected to ports VDD and GND. The power-on bias module 10 is used to shield the high-voltage component of the external power supply signal.

[0046] The real-time voltage and current testing module 20 is connected to the power-on bias module 10, and the real-time voltage and current testing module 20 is connected to port VEN and port GND. The real-time voltage and current testing module 20 is used to monitor the power consumption of the internal control unit of the motor drive system; and the real-time voltage and current testing module 20 can synchronously output an effective power-on enable signal to ensure that the motor drive system is powered on in a timely manner.

[0047] The input terminal of the output control module 30 is connected to the power-on bias module 10 and the real-time voltage and current detection module 20; the output terminal of the output control module 30 is connected to the VOUT port. The output control module 30 is used to provide a stable and reasonable power supply required by the internal control unit of the motor drive system.

[0048] Among them, port GND is the reference ground; port VDD is the external power supply port; port VOUT is used to output a stable and reasonable power supply signal to the internal control unit of the motor drive system; and port VEN is used to output a timely and effective power-on enable signal.

[0049] Ports V1, V2, V3, and V4 are the communication ports between the power-on bias module 10, the real-time voltage and current testing module 20, and the output control module 30, respectively.

[0050] First, the power-on bias module 10 in this embodiment will be described.

[0051] Please see Figure 2 The power-on bias module 10 includes a self-biased current source circuit and a common gate circuit.

[0052] The self-biased current source circuit includes a first resistor R1, a first PMOS transistor P1, a second PMOS transistor P2, and a third PMOS transistor P3.

[0053] The first resistor R1, the drain of the first PMOS transistor P1, the gate of the first PMOS transistor P1, and the gate of the second PMOS transistor P2 are all connected to the gate of the third PMOS transistor P3; the source of the first PMOS transistor P1, the source of the second PMOS transistor P2, and the source of the third PMOS transistor P3 are all connected to the port VDD.

[0054] The common gate circuit includes a first NMOS transistor N1, a second NMOS transistor N2, and a third NMOS transistor N3.

[0055] In this configuration, the drain of the second PMOS transistor P2, the gate of the third NMOS transistor N3, the drain of the third NMOS transistor N3, and the gate of the second NMOS transistor N2 are all connected to the gate of the first NMOS transistor N1; the drain of the third PMOS transistor P3 is connected to the drain of the second NMOS transistor N2; the source of the third NMOS transistor N3 is connected to port V1; the source of the second NMOS transistor N2 is connected to port V2; and the source of the first NMOS transistor N1 is connected to port V3.

[0056] Next, the real-time voltage and current testing module 20 in this embodiment will be described.

[0057] Please see Figure 2 The real-time voltage and current testing module 20 includes a conversion circuit, a reference level generation and voltage upper limit clamping circuit, a voltage comparison output circuit, a waveform shaping circuit, and a current amplitude detection circuit.

[0058] The current-to-voltage conversion circuit and the reference level generation and voltage upper limit clamping circuit are formed simultaneously by the fourth NMOS transistor N4, the fifth NMOS transistor N5, the sixth NMOS transistor N6 and the seventh NMOS transistor N7 connected in series.

[0059] The voltage comparison output circuit includes the eighth NMOS transistor N8, the ninth NMOS transistor N9, the tenth NMOS transistor N10, and the eleventh NMOS transistor N11.

[0060] The drain and gate of the seventh NMOS transistor N7, the gate of the eighth NMOS transistor N8, the gate of the ninth NMOS transistor N9, the gate of the tenth NMOS transistor N10, and the gate of the eleventh NMOS transistor N11 are all connected to the source of the sixth NMOS transistor N6; the source of the seventh NMOS transistor N7, the source of the eighth NMOS transistor N8, the source of the ninth NMOS transistor N9, the source of the tenth NMOS transistor N10, the source of the eleventh NMOS transistor N11, the source of the fifteenth NMOS transistor N15, and the source of the sixteenth NMOS transistor N16 are all connected to the port GND.

[0061] The waveform shaping circuit includes the twelfth NMOS transistor N12, the thirteenth NMOS transistor N13, the fourteenth NMOS transistor N14, the fifteenth NMOS transistor N15, the sixteenth NMOS transistor N16, the fourth PMOS transistor P4, the fifth PMOS transistor P5, and the first capacitor C1.

[0062] Among them, the drain of the tenth NMOS transistor N10 and the drain of the eleventh NMOS transistor N11 are both connected to the source of the twelfth NMOS transistor N12; the source of the thirteenth NMOS transistor N13 and the source of the fourteenth NMOS transistor N14 are both connected to the drain of the fifteenth NMOS transistor N15; the drain of the eighth NMOS transistor N8, the drain of the ninth NMOS transistor N9, the drain of the twelfth NMOS transistor N12, the lower end of the first capacitor C1, the gate of the thirteenth NMOS transistor N13, the gate of the fifteenth NMOS transistor N15, and the gate of the fourth PMOS transistor P4 are all connected to port V2.

[0063] The upper end of the first capacitor C1, the source of the fourth PMOS transistor P4, the drain of the fourteenth NMOS transistor N14, and the source of the fifth PMOS transistor P5 are all connected to port V3.

[0064] The drain of the fifth PMOS transistor P5 and the drain of the sixteenth NMOS transistor N16 are both connected to port V4.

[0065] The drain of the fourth PMOS transistor P4, the drain of the thirteenth NMOS transistor N13, the gate of the fourteenth NMOS transistor N14, the gate of the fifth PMOS transistor P5, the gate of the sixteenth NMOS transistor N16, and the gate of the twelfth NMOS transistor N12 are all connected to the port VEN.

[0066] The current amplitude detection circuit includes a first diode D1, which is connected to port V3.

[0067] Finally, the output control module 30 in this embodiment will be described.

[0068] Please see Figure 2 The output control module 30 includes a sixth PMOS transistor, P6.

[0069] The source of the sixth PMOS transistor P6 is connected to port V3; the gate of the sixth PMOS transistor P6 is connected to port V4; and the drain of the sixth PMOS transistor P6 is connected to port VOUT.

[0070] In a further embodiment of this utility model:

[0071] When an external power supply with fluctuating voltage amplitude supplies power to the motor drive system, the power-on bias module 10 checks whether the voltage amplitude meets the minimum requirements for the unit's operation. When the external power supply voltage amplitude exceeds the minimum operating voltage amplitude requirement of the power-on bias module 10, the self-biased current source circuit, composed of the first resistor R1, the first PMOS transistor P1, the second PMOS transistor P2, and the third PMOS transistor P3, starts operating and automatically activates the common-gate circuit composed of the third NMOS transistor N3, the second NMOS transistor N2, and the first NMOS transistor N1. At this time, the clamping property of the common-gate circuit enables the power-on bias module 10 to shield unnecessary high-voltage components in the external power supply signal. Subsequently, the power-on bias module 10 allows its ports V1 and V2 to generate current signals that can reflect the external power supply information in real time, and transmits them to the real-time voltage and current verification module 20 for processing. At the same time, the power-on bias module 10 also allows the first NMOS transistor N1 to generate a pull-up current at its port V3. The intensity of this current is jointly determined by the real-time voltage and current verification unit communicating with port V3 and the output control unit.

[0072] In a further embodiment of this utility model:

[0073] After the real-time voltage and current testing module 20 obtains the current signal reflecting the external power supply information from port V1, it converts it into a voltage signal through a conversion circuit at port V1 and processes it.

[0074] When the amplitude of the converted voltage signal is less than the reference voltage, the reference level generation and voltage upper limit clamping circuit cancels its clamping function, indicating that the amplitude of the external power supply voltage does not meet the output power supply conditions; the voltage comparison output circuit outputs high impedance. According to Ohm's law, the current signal from the power-on bias module 10 is automatically converted into a high-level voltage signal at port V2, and then shaped and output by the waveform shaping circuit. On the one hand, it makes the port VEN signal low, indicating that the motor drive system is not allowed to be powered on at this time; on the other hand, it makes the port V4 high, so as to control the gate of the sixth PMOS transistor P6 in the output control module 30 to be turned off. At this time, the port VOUT will not output the power supply voltage to the internal control unit of the motor drive system.

[0075] When the amplitude of the converted voltage signal is large enough to clamp the reference level and the voltage upper limit clamping circuit, the voltage signal is clamped at the reference voltage amplitude level, indicating that the external power supply voltage amplitude meets the output power supply conditions, that is, it meets the requirements for normal operation of the internal control unit of the motor drive system. The voltage comparison output circuit pulls down and absorbs all current signals from the power-on bias unit at port V2, so that port V2 is automatically converted to a low-level voltage signal; after being shaped by the waveform shaping circuit, on the one hand, port V4 is at a low level, and the gate of the sixth PMOS transistor P6 in the output control module 30 is turned on; on the other hand, the port VEN signal is at a high level, indicating that the motor drive system is allowed to be powered on immediately.

[0076] During the waveform shaping output process of the above waveform shaping circuit, a stable delay time is formed by the charging and discharging characteristics of the first capacitor C1, which ensures that the port VEN signal has a minimum low level duration, thus facilitating timely and effective sampling of the signal by external related systems.

[0077] After the output control module 30 is turned on, it outputs a stable and reasonable supply voltage to the internal control unit of the motor drive system through the drain of the sixth PMOS transistor P6 in the output control module 30 via port VOUT. Simultaneously, the output control module 30 feeds back the supply current information to port V3, which is then judged by the current amplitude detection circuit inside the real-time voltage and current verification module 20. When the supply current exceeds the normal range, the first diode D1 turns on and forcibly reduces the amplitude of the voltage signal at port V1, making it lower than the reference voltage. This causes the voltage comparison output circuit inside the real-time voltage and current verification module 20 to output a high impedance, ultimately making the port VEN signal low and port V4 high. This signals to the outside that the motor drive system is not allowed to be powered on, and the output control module 30 is turned off. Port VOUT no longer outputs power to the internal control unit of the motor drive system. This process defines the normal range of the supply current and indirectly defines the current intensity of the power supply circuit, ensuring the reasonable and effective power consumption of the internal control unit of the motor drive system.

[0078] Although embodiments of the present invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the present invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A power-on supply and enable circuit in a motor drive system, characterized in that, It includes a power-on bias module (10), a real-time voltage and current testing module (20), and an output control module (30), wherein: The real-time voltage and current testing module (20) is used to monitor the power consumption of the internal control unit of the motor drive system; The power-on bias module (10) is used to shield the high-voltage component of the external power supply signal; The output control module (30) is used to form a stable and reasonable power supply required by the internal control unit of the motor drive system, and the real-time voltage and current detection module (20) can synchronously output an effective power-on enable signal to ensure that the motor drive system is powered on and started in time.

2. The power supply and enable circuit in the motor drive system according to claim 1, characterized in that, The power-on bias module (10) includes a self-biased current source circuit and a common gate circuit.

3. The power supply and enable circuit in the motor drive system according to claim 2, characterized in that, The self-biased current source circuit includes a first resistor R1, a first PMOS transistor P1, a second PMOS transistor P2, and a third PMOS transistor P3, wherein: The first resistor R1, the drain of the first PMOS transistor P1, the gate of the first PMOS transistor P1, and the gate of the second PMOS transistor P2 are all connected to the gate of the third PMOS transistor P3. The source of the first PMOS transistor P1, the source of the second PMOS transistor P2, and the source of the third PMOS transistor P3 are all connected to the port VDD.

4. The power supply and enable circuit in the motor drive system according to claim 3, characterized in that, The common-gate circuit includes a first NMOS transistor N1, a second NMOS transistor N2, and a third NMOS transistor N3, wherein: The drain of the second PMOS transistor P2, the gate of the third NMOS transistor N3, the drain of the third NMOS transistor N3, and the gate of the second NMOS transistor N2 are all connected to the gate of the first NMOS transistor N1. The drain of the third PMOS transistor P3 is connected to the drain of the second NMOS transistor N2; The source of the third NMOS transistor N3 is connected to port V1; The source of the second NMOS transistor N2 is connected to port V2; The source of the first NMOS transistor N1 is connected to port V3.

5. The power supply and enable circuit in the motor drive system according to claim 1, characterized in that, The real-time voltage and current testing module (20) includes a conversion circuit, a reference level generation and voltage upper limit clamping circuit, a voltage comparison output circuit, a waveform shaping circuit, and a current amplitude detection circuit.

6. The power supply and enable circuit in the motor drive system according to claim 5, characterized in that, The conversion circuit and the reference level generation and voltage upper limit clamping circuit are simultaneously formed by the fourth NMOS transistor N4, the fifth NMOS transistor N5, the sixth NMOS transistor N6, and the seventh NMOS transistor N7 connected in series.

7. The power supply and enable circuit in the motor drive system according to claim 6, characterized in that, The voltage comparison output circuit includes an eighth NMOS transistor N8, a ninth NMOS transistor N9, a tenth NMOS transistor N10, and an eleventh NMOS transistor N11, wherein: The drain of the seventh NMOS transistor N7, the gate of the seventh NMOS transistor N7, the gate of the eighth NMOS transistor N8, the gate of the ninth NMOS transistor N9, the gate of the tenth NMOS transistor N10, and the gate of the eleventh NMOS transistor N11 are all connected to the source of the sixth NMOS transistor N6. The sources of the seventh NMOS transistor N7, the eighth NMOS transistor N8, the ninth NMOS transistor N9, the tenth NMOS transistor N10, the eleventh NMOS transistor N11, the fifteenth NMOS transistor N15, and the sixteenth NMOS transistor N16 are all connected to the port GND.

8. The power supply and enable circuit in the motor drive system according to claim 7, characterized in that, The waveform shaping circuit includes a twelfth NMOS transistor N12, a thirteenth NMOS transistor N13, a fourteenth NMOS transistor N14, a fifteenth NMOS transistor N15, a sixteenth NMOS transistor N16, a fourth PMOS transistor P4, a fifth PMOS transistor P5, and a first capacitor C1, wherein: The drain of the tenth NMOS transistor N10 and the drain of the eleventh NMOS transistor N11 are both connected to the source of the twelfth NMOS transistor N12; The source of the thirteenth NMOS transistor N13 and the source of the fourteenth NMOS transistor N14 are both connected to the drain of the fifteenth NMOS transistor N15; The drains of the eighth NMOS transistor N8, the ninth NMOS transistor N9, the twelfth NMOS transistor N12, the lower end of the first capacitor C1, the gate of the thirteenth NMOS transistor N13, the gate of the fifteenth NMOS transistor N15, and the gate of the fourth PMOS transistor P4 are all connected to port V2. The upper end of the first capacitor C1, the source of the fourth PMOS transistor P4, the drain of the fourteenth NMOS transistor N14, and the source of the fifth PMOS transistor P5 are all connected to port V3. The drain of the fifth PMOS transistor P5 and the drain of the sixteenth NMOS transistor N16 are both connected to port V4. The drain of the fourth PMOS transistor P4, the drain of the thirteenth NMOS transistor N13, the gate of the fourteenth NMOS transistor N14, the gate of the fifth PMOS transistor P5, the gate of the sixteenth NMOS transistor N16, and the gate of the twelfth NMOS transistor N12 are all connected to the port VEN.

9. The power supply and enable circuit in the motor drive system according to claim 5, characterized in that, The current amplitude detection circuit includes a first diode D1, which is connected to port V3.

10. The power supply and enable circuit in the motor drive system according to claim 1, characterized in that, The output control module (30) includes a sixth PMOS transistor P6, wherein: The source of the sixth PMOS transistor P6 is connected to port V3; The gate of the sixth PMOS transistor P6 is connected to port V4; The drain of the sixth PMOS transistor P6 is connected to port VOUT.

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