Chip capacitor checking jig
By improving the limiting chamber structure of the chip capacitor counting fixture, the chip capacitor is positioned upright instead of lying flat, and is guided to slide into the positioning area, thus solving the problem of inaccurate counting and improving the accuracy and efficiency of counting.
Patent Information
- Application Number
- CN202520147324.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-21
- Publication Date
- 2025-12-26
- Estimated Expiration
- 2035-01-21
AI Technical Summary
In the prior art, the chip capacitor counting fixture is prone to inaccurate counting, especially since flat chip capacitors are prone to stacking, leading to incorrect counting.
A chip capacitor counting fixture was designed. The chip capacitors in the limiting chamber can only be placed upright and cannot be laid flat. The opening area of the limiting chamber is small and is divided into a positioning area and a material guiding area. The material guiding area guides the chip capacitors to slide into the positioning area. The counting process is optimized by the material guiding fence.
It improves the accuracy of the number of cores in the chip capacitor, reduces the number of stacked chip capacitors, lowers the core count error rate, and reduces the number of shakes and wear.
Smart Images
Figure CN223728260U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The utility model relates to electronic technical field relates to a chip capacitor production chip capacitor nuclear number fixture. BACKGROUND
[0002] Chip capacitor has the advantages of small size, thin thickness, low equivalent series resistance, low loss, and application frequency up to tens of GHZ. At the same time, due to the use of gold electrode, chip welding and gold wire bonding can be carried out. It is widely used in small and microwave occasions, widely used in microwave communication lines, optical transceiver, and signal generator and other equipment, playing the role of direct current blocking, RF bypass, filtering, tuning and other functions.
[0003] In the production and sales process of chip capacitors, it is usually necessary to count the number of batches of chip capacitors. The nuclear number of conventional capacitors is usually counted by using a capacitor nuclear number fixture. The capacitor nuclear number fixture usually includes a bottom plate and a limiting frame arranged around the bottom plate. A plurality of transverse walls and longitudinal walls are arranged in an array on the bottom plate and are perpendicularly fitted with each other. Two adjacent transverse walls and two adjacent longitudinal walls form a limiting chamber matched with the capacitor product. A large number of capacitors are stacked on the bottom plate of the capacitor nuclear number fixture, and the capacitor nuclear number fixture is shaken. The capacitors are shaken in the space surrounded by the bottom plate and the limiting frame and fall into the limiting chamber until one limiting chamber contains one capacitor. The excess capacitors can be poured out. By comparing the weight of the empty capacitor nuclear number fixture and the capacitor nuclear number fixture with full load, the weight of a single capacitor can be converted, and the number of capacitors can be converted from the total weight of the batch of capacitor products. However, the present application has found that the use of the capacitor nuclear number fixture of the prior art for counting chip capacitors often results in inaccurate counting, and the number of chip capacitors cannot be correctly converted by weight. SUMMARY
[0004] Therefore, the purpose of the utility model is to overcome the defects or deficiencies of the prior art, and to provide a chip capacitor nuclear number fixture.
[0005] A chip capacitor nuclear number fixture includes a bottom plate, a plurality of transverse walls and longitudinal walls arranged in an array on the bottom plate and perpendicular to the bottom plate, and the transverse walls and longitudinal walls are perpendicularly fitted with each other. Two adjacent transverse walls, two adjacent longitudinal walls and the bottom plate form a limiting chamber, and the chip capacitor can be vertically arranged in the limiting chamber. When the chip capacitor is vertically arranged in the limiting chamber, the shortest side of the chip capacitor is parallel to the bottom plate. The shortest distance between two adjacent transverse walls is greater than 1 times the length of the shortest side of the chip capacitor and less than 2 times the length of the shortest side of the chip capacitor.
[0006] Compared with the prior art, the chip capacitor can only be vertically arranged in the limiting chamber instead of being horizontally arranged in the limiting chamber, so that the chip capacitor is vertically arranged in the limiting chamber, the opening area of the limiting chamber is reduced, the height is maintained, the flat chip capacitor can be stably arranged in the limiting chamber, and the chip capacitor is not easy to fall out again. Compared with being horizontally arranged in the limiting chamber, the chip capacitor is vertically arranged in the limiting chamber, so that the number of stacked chip capacitors is reduced, and the core number accuracy is improved.
[0007] Further, the length of the limiting chamber is that when the chip capacitor is vertically arranged in the limiting chamber, the length of the other side of the chip capacitor which is parallel to the bottom plate and perpendicular to the shortest side is L, the shortest distance between the two adjacent longitudinal walls is greater than L and less than 2L; the height of the transverse wall is 0.5-1.5 times the height of the chip capacitor; the height of the longitudinal wall is 0.5-1.5 times the height of the chip capacitor, that is, the height of the limiting chamber is 0.5-1.5 times the height of the chip capacitor.
[0008] Further, the area of the opening of the limiting chamber is greater than the area of the bottom surface of the limiting chamber.
[0009] Further, each transverse wall comprises a transverse wall lower part vertically arranged on the bottom plate and a transverse wall upper part vertically arranged on the top surface of the transverse wall lower part, the top surface width of the transverse wall upper part is less than the bottom surface width of the transverse wall upper part; each longitudinal wall comprises a longitudinal wall lower part vertically arranged on the bottom plate and a longitudinal wall upper part vertically arranged on the top surface of the longitudinal wall lower part, the top surface width of the longitudinal wall upper part is less than the bottom surface width of the longitudinal wall upper part.
[0010] Further, the cross section of the transverse wall upper part in the height direction is a trapezoid; the cross section of the longitudinal wall upper part in the height direction is a trapezoid.
[0011] Further, the cross section of the transverse wall upper part in the height direction is an isosceles trapezoid; the cross section of the longitudinal wall upper part in the height direction is an isosceles trapezoid.
[0012] Further, the transverse wall lower parts of the two adjacent transverse walls, the longitudinal wall lower parts of the two adjacent longitudinal walls and the bottom plate form a positioning area of the limiting chamber; the width of the positioning area of the limiting chamber is 1.2-1.5 times the length of the shortest side of the chip capacitor; the length of the positioning area of the limiting chamber is greater than or equal to 1.2L and less than or equal to 1.5L; the height of the positioning area of the limiting chamber is 0.8-1.2 times the height of the chip capacitor. The positioning area is used for positioning the chip capacitor, and each positioning area can accommodate at most one chip capacitor; the material guiding area is used for guiding the chip capacitor to more easily slide into the positioning area of the limiting chamber.
[0013] Further, the upper part of the horizontal wall of the two adjacent horizontal walls and the upper part of the vertical wall of the two adjacent vertical walls form a material guiding area of the limiting chamber; the width of the upper opening of the material guiding area is 1.2-1.5 times of the shortest distance between the two horizontal walls; the length of the upper opening of the material guiding area is 1.2-1.5 times of the shortest distance between the two vertical walls; the distance between the top surface and the bottom surface of the upper part of the horizontal wall is greater than the length of the shortest side of the chip capacitor; the distance between the top surface and the bottom surface of the upper part of the vertical wall is greater than the length of the shortest side of the chip capacitor; the included angle between the inner side wall of the upper part of the horizontal wall at the material guiding area of the limiting chamber and the bottom plate is 30-60°; the included angle between the inner side wall of the upper part of the vertical wall at the material guiding area of the limiting chamber and the bottom plate is 30-60°. When the size of the material guiding area is in the range, the chip capacitor can be efficiently guided to slide into the limiting chamber, and the efficiency of the core number jig is improved; and if there is already one chip capacitor in the positioning area, the excess chip capacitor in the material guiding area can also be removed from the limiting chamber position by shaking, tilting or sweeping, so that only one chip capacitor can be stably erected in the positioning area.
[0014] Further, the top surface of the upper part of the horizontal wall and the top surface of the upper part of the vertical wall form a mesh top surface; the chip capacitor core number jig further comprises a mesh material guiding fence, which is arranged on the mesh top surface and covers the mesh top surface; the top surface of the material guiding fence is an arc surface; the width of the top surface of the upper part of the horizontal wall is less than 0.5 times of the height of the chip capacitor; and the width of the top surface of the upper part of the vertical wall is less than 0.5 times of the height of the chip capacitor.
[0015] Further, a limiting frame is further arranged on the periphery of the bottom plate, and a material cleaning opening is arranged at the corner of the limiting frame. BRIEF DESCRIPTION OF DRAWINGS
[0016] Figure 1 It is a structural schematic diagram of the chip capacitor in the erected state;
[0017] Figure 2 It is a top view of the chip capacitor core number jig;
[0018] Figure 3 It is a sectional view of the chip capacitor core number jig along the A-A sectional line; Figure 4
[0019] Figure 4 It is a side view structural schematic diagram of the limiting chamber;
[0020] Figure 5 It is a front view structural schematic diagram of the limiting chamber;
[0021] Figure 6 It is a front view structural schematic diagram of the chip capacitor erected in the limiting chamber;
[0022] Figure 7 A side view of the structure of a chip capacitor installed in a limiting chamber;
[0023] Figure 8 This is a top view of the confinement chamber.
[0024] Reference numerals: 10 Base plate, 11 Horizontal wall, 11a Upper part of horizontal wall, 11b Lower part of horizontal wall, 12 Longitudinal wall, 12a Upper part of longitudinal wall, 12b Lower part of longitudinal wall, 13 Filling wall, 14 Positioning area, 15 Guide area, 20 Limiting frame, 21 Clearing port, 30 Guide fence, 40 Chip capacitor, 40a Shortest side of chip capacitor, 40b Long side of chip capacitor, 40c High side of chip capacitor. Detailed Implementation
[0025] This invention analyzes why existing chip capacitor counting jigs often fail to accurately determine the number of chip capacitors. It was found that when using conventional chip capacitor counting jigs, multiple chip capacitors are frequently positioned within a single limiting chamber. Typically, operators consider the jig to be fully loaded when each limiting chamber contains a capacitor, and the number of capacitors in each chamber is assumed to be the same as the number of limiting chambers on the limiting plate. However, when multiple chip capacitors fall into a single limiting chamber, a jig considered fully loaded actually contains more capacitors than the number of limiting chambers. This leads to an overestimation of the weight of individual capacitors calculated from the weight of the jig itself, resulting in an underestimation of the total number of chip capacitors calculated from the total weight of the entire batch.
[0026] This invention further analyzes the reasons for this problem. Chip capacitors are relatively thin, being flat rectangular sheets, typically square sheets. Existing chip capacitor counting fixtures have relatively large openings in terms of length, width, and height, ensuring that at most one traditional capacitor with a thicker, more three-dimensional shape can be placed flat within the counting chamber. When the chip capacitor is placed flat within the counting chamber, its shortest side is perpendicular to the base plate of the counting fixture, while the other two sides, longer than the shortest side, are parallel to the base plate. While existing counting fixtures can limit the entry of at most one traditional capacitor into the counting chamber, multiple flat chip capacitors can easily enter in a stacked state, leading to inaccurate counting. However, simply reducing the height of the counting chamber to only allow one chip capacitor to be placed flat results in a shallow chamber, causing the chip capacitor to easily leave the counting chamber when the counting fixture is repeatedly moved.
[0027] Therefore, this utility model, through improvements to the core number fixture, no longer allows the chip capacitor to be placed flat within the limiting chamber, but rather it must be erected upright within the limiting chamber. For example... Figure 1As shown, when the chip capacitor is vertically arranged in the limiting chamber, the shortest side 40a of the chip capacitor is parallel to the bottom plate of the core number jig; another side of the chip capacitor 40 which is parallel to the bottom plate and perpendicular to the shortest side 40a of the chip capacitor is the long side 40b of the chip capacitor; and the side of the chip capacitor which is perpendicular to the bottom plate is the high side 40c of the chip capacitor. The length of the shortest side 40a of the chip capacitor represents the thickness of the chip capacitor 40, the length of the long side 40b of the chip capacitor represents the length of the chip capacitor 40, and the length of the high side 40c of the chip capacitor represents the height of the chip capacitor. The length of the chip capacitor 40 is L, the thickness is W, and the height is H. Compared with being placed horizontally in the limiting chamber, the chip capacitor is vertically arranged in the limiting chamber, so that the opening area of the limiting chamber is smaller, a certain height is still maintained, the flat chip capacitor can be stably arranged vertically in a limiting chamber and is not easy to fall out again, the number of stacked chip capacitors is reduced, and the core number accuracy is improved.
[0028] Further, the utility model considers that the flat chip capacitor usually freely falls above the bottom plate of the core number jig in a horizontal posture, and is not easy to stand up and enter the limiting chamber. Therefore, the utility model thinks that the area of the opening of the limiting chamber is greater than the area of the bottom surface of the limiting chamber, so as to facilitate the chip capacitor to slide into the limiting chamber. Through further analysis and optimization experiment, the utility model divides the limiting chamber into a positioning area located on the bottom plate and a hopper-shaped material guiding area located above the positioning area. The hopper-shaped material guiding area can guide the chip capacitor to more easily slide into the limiting chamber, and the chip capacitor finally vertically arranged in the positioning area after sliding into the limiting chamber. Further, the utility model limits the positioning area to at most accommodate one chip capacitor by analyzing and optimizing the size parameters of the positioning area and the material guiding area, and makes the material guiding area can efficiently guide the chip capacitor to enter; when there is one chip capacitor in the positioning area, the excess chip capacitors located in the material guiding area can also easily leave the limiting chamber.
[0029] The scheme of the utility model will be described in detail in combination with the drawings.
[0030] As shown in the drawings, Figures 2-3 A chip capacitor core number jig, as shown in the drawings, comprises a bottom plate 10, a plurality of horizontal walls 11 and a plurality of vertical walls 12 which are arranged in an array on the bottom plate 10 and are perpendicular to the bottom plate 10, and a limiting frame 20 arranged on the periphery of the bottom plate 10.
[0031] As shown in the drawings, Figures 2-5As shown in the figure, the bottom plate 10 is rectangular, and the lateral walls 11 and the longitudinal walls 12 are perpendicularly fitted with each other. Two adjacent lateral walls 11, two adjacent longitudinal walls 12 and the bottom plate 10 form a limiting chamber. The height of the lateral walls 11 and the longitudinal walls 12 is equal, and the height is 0.5-1.5 times the height H of the chip capacitor. The height of the limiting frame 20 is greater than the height of the lateral walls 11 and the longitudinal walls 12, and the limiting frame 20 is provided with a cleaning port 21 at the corner. Preferably, the bottom plate 10, the lateral walls 11 and the longitudinal walls 12 are integrally formed.
[0032] Specifically, as shown in the figure, Figures 4-5 The lateral wall 11 includes a lateral wall lower part 11b erected on the bottom plate 10 and a lateral wall upper part 11a erected on the top surface of the lateral wall lower part 11b, and the top surface width of the lateral wall upper part 11a is less than the bottom surface width of the lateral wall upper part 11a. Each longitudinal wall 12 includes a longitudinal wall lower part 12b erected on the bottom plate 10 and a longitudinal wall upper part 12a erected on the top surface of the longitudinal wall lower part 12b, and the top surface width of the longitudinal wall upper part 12a is less than the bottom surface width of the longitudinal wall upper part 12a. The lateral wall lower parts 11b of two adjacent lateral walls 11, the longitudinal wall lower parts 12b of two adjacent longitudinal walls 12 and the bottom plate 10 form a positioning area 14 of the limiting chamber, which is used to position the chip capacitor 40 in an erected state in the limiting chamber more stably. The lateral wall upper parts 11a of two adjacent lateral walls 11 and the longitudinal wall upper parts 12a of two adjacent longitudinal walls 12 form a material guiding area 15 of the limiting chamber, which is used to guide the chip capacitor 40 to slide into the positioning area 14 of the limiting chamber.
[0033] In this embodiment, as shown in the figure, Figures 4-5As shown, the cross section of the lower part 11b of the lateral wall along the height direction is rectangular, and the cross section of the lower part 12b of the longitudinal wall along the height direction is rectangular, so the lower parts 11b of the two adjacent lateral walls 11 are parallel to each other, the lower parts 12b of the two adjacent longitudinal walls 12 are parallel to each other, and the positioning area 14 of the limiting chamber in this embodiment is a cubic space. The shortest distance between the lower parts 12b of the two adjacent longitudinal walls 12 is the shortest distance between the two adjacent longitudinal walls 12, and this distance is the length of the positioning area 14 of the limiting chamber. The length of the positioning area 14 of the limiting chamber is greater than 1 times the length L of the chip capacitor 40 and less than 2 times the length L of the chip capacitor 40. The shortest distance between the lower parts 11b of the two adjacent lateral walls 11 is the shortest distance between the two adjacent lateral walls 11, and this distance is the width of the positioning area 14 of the limiting chamber. The width of the positioning area 14 of the limiting chamber is greater than 1 times the thickness W of the chip capacitor 40 and less than 2 times the thickness W of the chip capacitor 40. The lower parts 11b and 12b are of the same height, and the height is the height of the positioning area 14. The height of the positioning area 14 is greater than or equal to 0.5 times the height H of the chip capacitor 40, and is preferably 0.8-1.2 times the height H of the chip capacitor 40. Within this size range, the positioning area 14 can effectively position the chip capacitor 40 standing in the positioning area 14, so that it will not easily leave the positioning area 14 of the limiting chamber under normal shaking, and at most only one chip capacitor 40 can be in the positioning area 14, enhancing the positioning effect of the positioning area 14 and ensuring the counting efficiency of the counting tool.
[0034] As Figures 4-5As shown, the upper part 11a of the lateral wall is isosceles trapezoidal in cross section along the height direction, and the top width of the upper part 11a of the lateral wall is smaller than the bottom width; the upper part 12a of the longitudinal wall is isosceles trapezoidal in cross section along the height direction, and the top width of the upper part 12a of the longitudinal wall is smaller than the bottom width; the material guiding area 15 of the limiting chamber in this embodiment is in the shape of a bucket, and the upper opening and the lower opening of the bucket-shaped material guiding area 15 are both rectangular. The shortest distance between the bottoms of two adjacent upper parts 12a of the longitudinal wall is the length of the lower opening of the material guiding area 15; the shortest distance between the bottoms of two adjacent upper parts 11a of the lateral wall is the width of the lower opening of the material guiding area 15. The length of the lower opening of the material guiding area 15 is equal to the length of the positioning area 14, and the width of the lower opening of the material guiding area 15 is equal to the width of the positioning area 14. The shortest distance between the tops of two adjacent upper parts 12a of the longitudinal wall is the length of the upper opening of the material guiding area 15; the shortest distance between the tops of two adjacent upper parts 11a of the lateral wall is the width of the upper opening of the material guiding area 15. The length of the upper opening of the material guiding area 15 is greater than the length of the lower opening, and preferably: the length of the positioning area 14 of the limiting chamber is 1.2-1.5 times the length L of the chip capacitor 40, and the length of the upper opening of the material guiding area 15 is 1.2-1.5 times the length of the positioning area 14. The width of the upper opening of the material guiding area 15 is greater than the width of the lower opening, and preferably: the width of the positioning area 14 of the limiting chamber is 1.2-1.5 times the thickness W of the chip capacitor 40, and the width of the upper opening of the material guiding area 15 is 1.2-1.5 times the width of the positioning area 14. The distance between the top and the bottom of the upper part 11a of the lateral wall is equal to the distance between the top and the bottom of the upper part 12a of the longitudinal wall, and the distance between the top and the bottom of the upper part 11a of the lateral wall and the distance between the top and the bottom of the upper part 12a of the longitudinal wall can both represent the height of the material guiding area 15. The height of the material guiding area 15 is greater than the thickness W of the chip capacitor 40. In the preferred embodiment, the height of the material guiding area 15 is greater than 1 times the thickness W of the chip capacitor 40 and less than 1 times the height H of the chip capacitor 40, on the premise that the total height of the positioning area 14 and the material guiding area 15 of the limiting chamber is less than or equal to 1.5 times the height of the chip capacitor 40. When the size of the material guiding area 15 is within this range, the chip capacitor 40 can be efficiently guided to slide into the limiting chamber, and the efficiency of the core counting jig is improved; and if there is already a chip capacitor 40 in the positioning area 14, the chip capacitor 40 in the material guiding area can also be made to leave the position of the limiting chamber by shaking, tilting or sweeping, so as to ensure that only one chip capacitor 40 can be stably erected in the positioning area 14 in the limiting chamber. Further, in an embodiment, the included angle between the inner side wall of the upper part 11a of the lateral wall at the material guiding area 15 of the limiting chamber and the bottom plate 10 is 30-60°; the included angle between the inner side wall of the upper part 12a of the longitudinal wall at the material guiding area 15 of the limiting chamber and the bottom plate 10 is 30-60°. The inner side wall of the upper part 11a of the lateral wall at the material guiding area 15 of the limiting chamber and the inner side wall of the upper part 12a of the longitudinal wall at the material guiding area 15 of the limiting chamber are both the inner side walls of the bucket-shaped material guiding area 15.At this angle, the material guiding area 15 can more efficiently guide the chip capacitor 40 to slide into the limiting chamber and stand in the positioning area 14, and can also more efficiently slide away or be pushed away from the limiting chamber when there are already chip capacitors 40 in the positioning area 14, so that only one chip capacitor 40 is stably and vertically arranged in the positioning area 14 of the limiting chamber.
[0035] When the chip capacitor counting jig is used, a handful of chip capacitors 40 are scattered on the counting jig, and the counting jig is shaken, so that the chip capacitors 40 change the placement direction under the shaking, and are guided by the material guiding area 15 of the bucket shape to slide into the limiting chamber and finally stand in the positioning area 14 of the limiting chamber. Figures 6-7 As shown in the figure, when the chip capacitor 40 stands in the positioning area 14 of the limiting chamber, the shortest side 40a of the chip capacitor is parallel to the bottom plate 10, the long side 40b of the chip capacitor is parallel to the bottom plate 10 and perpendicular to the shortest side 40a of the chip capacitor, and the high side 40c of the chip capacitor is perpendicular to the bottom plate 10. The structure of the limiting chamber can only allow at most one chip capacitor 40 to enter the positioning area 14 of the limiting chamber, and after the chip capacitor 40 stands in the positioning area 14 of the limiting chamber, it will not easily leave the positioning area 14 of the limiting chamber under normal shaking. When one chip capacitor 40 stands in the positioning area 14 of each limiting chamber, the counting jig is tilted, and the excess chip capacitors 40 are poured out from the material removing port 21.
[0036] Further, the utility model finds that the top surfaces of all the horizontal wall upper portions 11a and the top surfaces of all the longitudinal wall upper portions 12a in the counting jig form a meshed top surface. Since the top surfaces of the horizontal wall upper portions 11a and the top surfaces of the longitudinal wall upper portions 12a all have a certain width, the chip capacitors 40 can be kept on the meshed top surface, and need to be shaken intentionally for multiple times to slide into the limiting chamber through the material guiding area 15, which to some extent affects the counting efficiency and increases the abrasion probability of the chip capacitors 40. Therefore, the utility model is further improved through analysis and summary:
[0037] The width of the top surface of the horizontal wall upper portion 11a is less than 0.5 times the height H of the chip capacitor 40, and the width of the top surface of the longitudinal wall upper portion 12a is less than 0.5 times the height H of the chip capacitor, so that the chip capacitor 40 is not easy to keep balanced on the meshed top surface and is more likely to fall into the material guiding area 15 of the limiting chamber. Further, as shown in the figure, a meshed material guiding fence 30 is arranged on the meshed top surface. Figures 4-8 The bottom surface of the material guiding fence 30 is covered by the meshed top surface, and the top surface of the material guiding fence 30 is an arc surface, which can guide the chip capacitors 40 falling above to fall in the direction of the limiting chamber, reduce the shaking frequency, and improve the counting efficiency. Preferably, as shown in the figure, the material guiding fence 30 is arranged on the meshed top surface.Figure 8 As shown, the corner portions of the grid of the netted material transfer fence are rounded, and the corner portions of the vertical joints between the adjacent horizontal walls 11 and vertical walls 12 are rounded. The rounded corner portions help avoid dust accumulation at the corners and facilitate cleaning.
[0038] Further, as shown, Figures 2-3 As shown, the area of the bottom plate 10 where the horizontal walls 11 and vertical walls 12 are concentrated is the core area of the bottom plate 10, which is preferably arranged at the middle of the bottom plate 10, and the area of the bottom plate 10 outside the core area is the peripheral area of the bottom plate 10. The filling walls 13 are arranged on the peripheral area of the bottom plate 10, which surround the periphery of the horizontal walls 11 and vertical walls 12 at the edge of the core area and have the same height as the horizontal walls 11 and vertical walls 12. The filling walls 13 can fill the bottom plate 10 from the edge to the core area to the same height as the horizontal walls 11 and vertical walls 12, so that the chip capacitor 40 can fall on the filling walls 13 at the same height as the horizontal walls 11 and vertical walls 12 when it is at the peripheral area, which facilitates the chip capacitor 40 to be shaken to the core area more easily. Preferably, the bottom plate 10, the horizontal walls 11, the vertical walls 12, the material transfer fence 30, and the filling walls 13 are integrally formed.
[0039] Compared with the prior art, the chip capacitor core number jig provided by the utility model has the following advantages:
[0040] 1. Each limiting chamber can accommodate only one chip capacitor 40, and the chip capacitor 40 can be vertically arranged only in the positioning area 14 of the limiting chamber.
[0041] 2. The limiting chamber includes the positioning area 14 and the material guiding area 15, the material guiding area 15 can guide the chip capacitor 40 to enter the positioning area 14 of the limiting chamber and finally be vertically arranged in the positioning area 14 of the limiting chamber, thereby improving the core number efficiency.
[0042] 3. The material transfer fence is additionally arranged, so that the chip capacitor 40 is more easily guided to enter the limiting chamber, thereby further improving the core number efficiency, reducing the shaking frequency, and further reducing the abrasion of the chip capacitor 40.
[0043] The terms used in the embodiments of the present application are merely for the purpose of describing specific embodiments, and are not intended to limit the embodiments of the present application. The singular forms "a", "an" and "the" used in the embodiments of the present application and the claims are also intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that "several" means two or more, unless otherwise stated. The above description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. In the description of the present application, the specific meanings of the above terms in the present application can be understood by those skilled in the art according to the specific circumstances.
[0044] The above embodiments only express several implementation manners of the utility model, the description is more specific and detailed, but can not therefore be understood as the limitation of the utility model patent range. It should be pointed out that for ordinary skilled person in the art, without departing from the utility model concept, several modifications and improvements can be made, which belong to the protection range of the utility model.
Claims
1. A chip capacitor core counting jig, characterized by, The application relates to a chip capacitor limiting room. The chip capacitor is vertically arranged in the limiting room, and the shortest side of the chip capacitor is parallel to the bottom plate; the shortest distance between two adjacent horizontal walls is greater than 1 times the length of the shortest side of the chip capacitor and less than 2 times the length of the shortest side of the chip capacitor.
2. The chip capacitor core counting tool of claim 1, wherein: When the chip capacitor is vertically arranged in the limiting room, the length of the other side of the chip capacitor which is parallel to the bottom plate and perpendicular to the shortest side is L, the shortest distance between two adjacent vertical walls is greater than L and less than 2L; the height of the horizontal wall is 0.5-1.5 times the height of the chip capacitor; the height of the vertical wall is 0.5-1.5 times the height of the chip capacitor.
3. The chip capacitor core counting tool of claim 2, wherein: The area of the opening of the limiting room is greater than the area of the bottom surface of the limiting room.
4. The chip capacitor core counting tool of claim 3, wherein: Each horizontal wall comprises a horizontal wall lower part vertically arranged on the bottom plate and a horizontal wall upper part vertically arranged on the top surface of the horizontal wall lower part; the top surface width of the horizontal wall upper part is less than the bottom surface width of the horizontal wall upper part; each vertical wall comprises a vertical wall lower part vertically arranged on the bottom plate and a vertical wall upper part vertically arranged on the top surface of the vertical wall lower part; the top surface width of the vertical wall upper part is less than the bottom surface width of the vertical wall upper part.
5. The chip capacitor core counting tool of claim 4, wherein: The cross section of the horizontal wall upper part along the height direction is trapezoidal; the cross section of the vertical wall upper part along the height direction is trapezoidal.
6. The chip capacitor core counting tool of claim 5, wherein: The cross section of the horizontal wall upper part along the height direction is isosceles trapezoidal; the cross section of the vertical wall upper part along the height direction is isosceles trapezoidal.
7. The chip capacitor core counting tool of claim 6, wherein: The horizontal wall lower part of two adjacent horizontal walls, the vertical wall lower part of two adjacent vertical walls and the bottom plate form a positioning area of the limiting room; the width of the positioning area of the limiting room is 1.2-1.5 times the length of the shortest side of the chip capacitor; the length of the positioning area of the limiting room is greater than or equal to 1.2L and less than or equal to 1.5L; the height of the positioning area of the limiting room is 0.8-1.2 times the height of the chip capacitor.
8. The chip capacitor core counting tool of claim 7, wherein: The horizontal wall upper part of two adjacent horizontal walls and the vertical wall upper part of two adjacent vertical walls form a material guiding area of the limiting room; the width of the upper opening of the material guiding area is 1.2-1.5 times the shortest distance between two horizontal walls; the length of the upper opening of the material guiding area is 1.2-1.5 times the shortest distance between two vertical walls; the distance between the top surface and the bottom surface of the horizontal wall upper part is greater than the length of the shortest side of the chip capacitor; the distance between the top surface and the bottom surface of the vertical wall upper part is greater than the length of the shortest side of the chip capacitor; the included angle between the inner side wall of the horizontal wall upper part at the material guiding area of the limiting room and the bottom plate is 30-60 degrees; the included angle between the inner side wall of the vertical wall upper part at the material guiding area of the limiting room and the bottom plate is 30-60 degrees.
9. The chip capacitor core counting tool of claim 4, wherein: The top surface of the upper part of the transverse wall and the top surface of the upper part of the longitudinal wall jointly form a mesh top surface; the chip capacitor core number jig further comprises a mesh material guiding fence, which is arranged on the mesh top surface and covers the mesh top surface; the top surface of the material guiding fence is a curved surface; the width of the top surface of the upper part of the transverse wall is less than 0.5 times the height of the chip capacitor; the width of the top surface of the upper part of the longitudinal wall is less than 0.5 times the height of the chip capacitor.
10. The chip capacitor core counting tool of any of claims 1-9, wherein: Further comprising a limiting frame arranged at the periphery of the bottom plate, and a material cleaning opening is arranged at the corner of the limiting frame.