Optical module

Abstract

The optical module provided by the utility model comprises a circuit board which is provided with a limiting amplifier and a reset signal generation circuit; the light receiving component comprises a photoelectric detector and a trans-impedance amplifier, the photoelectric detector is used for receiving burst light receiving signals, the input end of the trans-impedance amplifier is electrically connected with the photoelectric detector, and the output end of the trans-impedance amplifier is electrically connected with the limiting amplifier; the reset signal generation circuit comprises: a time delay sub-circuit, the input end of which is used for inputting a detection signal and performing time delay processing on the detection signal; the exclusive-OR gate comprises a first input end and a second input end; the first input end is used for inputting a detection signal, and the second input end is connected with the output end of the delay sub-circuit; the output end of the exclusive-OR gate is connected with the reset input end of the transimpedance amplifier, and the exclusive-OR gate outputs a first reset signal based on a detection signal and a delayed detection signal, so that the transimpedance amplifier is reset based on the first reset signal. And rapid resetting of the transimpedance amplifier is facilitated.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the field of optical communication technology, and in particular to an optical module. BACKGROUND

[0002] With the development of new business and application modes such as cloud computing, mobile Internet, video, etc., the progress of optical communication technology becomes increasingly important. In optical communication technology, the optical module, as one of the key devices in optical communication equipment, can realize optical-electric signal conversion; in the development process of optical communication technology, the data transmission rate of the optical module is required to be continuously improved. CONTENT OF THE INVENTION

[0003] Some embodiments provide an optical module, which facilitates fast resetting of a transimpedance amplifier.

[0004] Some embodiments provide an optical module, which comprises:

[0005] a circuit board, configured with an amplitude limiting amplifier and a reset signal generation circuit;

[0006] an optical receiving component, electrically connected to the circuit board; the optical receiving component comprises a photodetector and a transimpedance amplifier, the photodetector is configured to receive a burst optical receiving signal, an input end of the transimpedance amplifier is electrically connected to the photodetector, and an output end of the transimpedance amplifier is electrically connected to the amplitude limiting amplifier;

[0007] The reset signal generation circuit comprises:

[0008] a delay sub-circuit, configured to input a detection signal and delay process the detection signal;

[0009] an XOR gate, comprising a first input end and a second input end; the first input end is configured to input the detection signal, and the second input end is connected to an output end of the delay sub-circuit; an output end of the XOR gate is connected to a reset input end of the transimpedance amplifier, and the XOR gate outputs a first reset signal based on the detection signal and the delay-processed detection signal, so that the transimpedance amplifier is reset based on the first reset signal.

[0010] One of the above technical solutions has the following advantages or beneficial effects: The reset signal generating circuit is arranged on the circuit board, and the output end of the reset signal generating circuit is connected to the reset input end of the trans-impedance amplifier. The reset signal generating circuit generates a first reset signal, and the trans-impedance amplifier can be reset based on the first reset signal. The reset signal generating circuit includes a delay sub-circuit and an XOR gate. The first input end of the XOR gate and the input end of the delay sub-circuit are respectively inputted with a detection signal, the second input end of the XOR gate is connected to the output end of the delay sub-circuit, and the delay sub-circuit processes the detection signal to be transmitted to the second input end of the XOR gate after time delay. The XOR gate performs XOR operation on the signals at the first input end and the second input end to generate the first reset signal. Generally, when the optical receiving component suddenly receives an optical receiving signal, the host board card sends a reset signal to the trans-impedance amplifier, and the host board card often generates the reset signal based on the optical receiving component receiving the optical signal, so that the reset signal arrives at the trans-impedance amplifier relatively late. The first reset signal generated by the reset signal generating circuit arrives earlier than the reset signal sent by the host board card, so that the trans-impedance amplifier can receive the reset signal relatively early, so as to reset as soon as possible and reduce the situation that the optical receiving signal will be restored to an abnormal electrical signal due to the relatively late arrival of the reset signal.

[0011] Some embodiments provide an optical module, wherein the end of the circuit board is formed with a gold finger, and the gold finger includes a reset pin; and an OR gate is further arranged on the circuit board.

[0012] The first input end of the OR gate is connected to the output end of the XOR gate, the second input end of the OR gate is connected to the reset pin, and the output end of the OR gate is connected to the reset input end of the trans-impedance amplifier.

[0013] One of the above technical solutions has the following advantages or beneficial effects: The reset pin is included in the gold finger formed at the end of the circuit board, and the reset pin can be used to transmit a reset signal sent by a host board card. An OR gate is arranged on the circuit board, the first input end of the OR gate is connected to the output end of the reset signal generating circuit, the second input end of the OR gate is connected to the reset pin, and the OR gate performs OR operation on a first reset signal generated by the reset signal generating circuit and a reset signal sent by the host board card, so that the trans-impedance amplifier can receive the reset signal at least twice during the process that the optical receiving component suddenly receives an optical receiving signal, thereby ensuring the stability of the burst operation of the optical receiving component.

[0014] Some embodiments provide an optical module, wherein the delay sub-circuit includes a buffer and a delay device, the input end of the buffer is used to input a detection signal, the output end of the buffer is connected to the input end of the delay device, and the output end of the delay device is connected to the second input end of the XOR gate.

[0015] One of the above technical solutions has the following advantages or beneficial effects: the delay sub-circuit includes a buffer and a delay device, the delay device can use resistance and capacitance, etc., to delay the detection signal by using the buffer and the delay device, so that the detection signal is delayed to reach the second input end of the XOR gate.

[0016] Some embodiments provide an optical module, wherein the SD detection circuit is packaged in the limiting amplifier, detection signal output pins are formed on the limiting amplifier, and the input end of the delay sub-circuit and the first input end of the XOR gate are respectively connected to the detection signal output pins of the limiting amplifier, so as to facilitate the reset signal generation circuit to generate the first reset signal based on the SD detection signal output by the limiting amplifier.

[0017] One of the above technical solutions has the following advantages or beneficial effects: the SD detection circuit is packaged in the limiting amplifier, and detection signal output pins are formed on the limiting amplifier. The input end of the delay sub-circuit and the first input end of the XOR gate are respectively connected to the detection signal output pins of the limiting amplifier, so as to facilitate the reset signal generation circuit to generate the first reset signal based on the SD detection signal output by the limiting amplifier.

[0018] Some embodiments provide an optical module, wherein the SD detection circuit is packaged in the limiting amplifier, detection signal output pins are formed on the limiting amplifier, and the input end of the delay sub-circuit and the first input end of the XOR gate are respectively connected to the detection signal output pins of the limiting amplifier, so as to facilitate the reset signal generation circuit to generate the first reset signal based on the SD detection signal output by the limiting amplifier.

[0019] One of the above technical solutions has the following advantages or beneficial effects: the SD detection circuit is packaged in the limiting amplifier, and detection signal output pins are formed on the limiting amplifier. The input end of the delay sub-circuit and the first input end of the XOR gate are respectively connected to the detection signal output pins of the limiting amplifier, so as to facilitate the reset signal generation circuit to generate the first reset signal based on the SD detection signal output by the limiting amplifier.

[0020] Some embodiments provide an optical module, wherein the optical receiving component further includes a socket and a cap, and pins are arranged on the socket; the photodetector and the transimpedance amplifier are arranged on the socket, the photodetector is wire-bonded to the transimpedance amplifier, and the transimpedance amplifier is connected to the circuit board through the pins.

[0021] One of the above technical solutions has the following advantages or beneficial effects: the optical receiving component includes a socket and a cap, which facilitates packaging of the photodetector and the transimpedance amplifier. Pins are formed on the socket, the photodetector is wire-bonded to the transimpedance amplifier, and the transimpedance amplifier is wire-bonded to the corresponding pins, so as to be electrically connected to the circuit board through the pins, facilitating electrical connection of the transimpedance amplifier with the limiting amplifier and the reset signal generation circuit.

[0022] Some embodiments provide an optical module, wherein the circuit board is further provided with a large-small light judgment circuit and a reset signal expansion circuit;

[0023] The input end of the large-small light judgment circuit is connected with the photodetector, so as to compare the light power intensity of the optical receiving signal burst-received by the photodetector with the light power threshold value; the output end of the large-small light judgment circuit outputs a first indication signal or a second indication signal, wherein the first indication signal is used to indicate that the light power intensity of the optical receiving signal is greater than or equal to the light power threshold value, and the second indication signal is used to indicate that the light power intensity of the optical receiving signal is less than the light power threshold value;

[0024] The reset signal expansion circuit comprises:

[0025] A logic switch, whose control end is connected with the output end of the large-small light judgment circuit, whose first input end inputs a first reference voltage, and whose second input end inputs a second reference voltage, wherein the first reference voltage is less than the second reference voltage; the logic switch turns on its second input end and output end based on the first indication signal, and turns on its first input end and output end based on the second indication signal;

[0026] A first MOS tube, whose gate electrode is electrically connected with the output end of the logic switch, and whose source electrode is electrically connected with a power supply input end;

[0027] A second capacitor, one end of which is electrically connected with the drain electrode of the first MOS tube, and the other end of which is grounded;

[0028] An inverter, the input end of which is electrically connected with the drain electrode of the first MOS tube;

[0029] A second MOS tube, whose drain electrode is electrically connected with the drain electrode of the first MOS tube, whose source electrode is electrically connected with the ground, and whose gate electrode inputs a reset signal;

[0030] An OR gate, whose first input end is connected with the output end of the inverter, and whose second input end inputs the reset signal.

[0031] One of the above technical solutions has the following advantages or beneficial effects: the circuit board is provided with a large-small light judgment circuit and a reset signal expansion circuit. The large-small light judgment circuit is connected with the photodetector, and is used to compare the light power intensity of the optical receiving signal with the light power threshold value, so as to output the corresponding indication signal based on different comparison results. The reset signal expansion circuit is connected with the large-small light judgment circuit and the limiting amplifier, and adjusts the expansion of the reset signal based on the indication signal output by the large-small light judgment circuit, so as to adjust the width of the reset signal transmitted to the limiting amplifier, so that the discharging time of the AC coupling capacitor in the limiting amplifier is more appropriate.

[0032] The reset signal broadening circuit includes a logic switch, a first MOSFET, a second capacitor, an inverter, another second MOSFET, and an OR gate. The control terminal of the logic switch is connected to the output of the magnitude light judgment circuit. The output of the logic switch is connected to the gate of the first MOSFET. The first input of the logic switch receives a first reference voltage, and the second input receives a second reference voltage, where the first reference voltage is less than the second reference voltage. The source of the first MOSFET is connected to the power input. The drain of the first MOSFET is connected to one end of the second capacitor, the input of the inverter, and the drain of the second MOSFET, respectively. The other end of the second capacitor is grounded. The output of the inverter is connected to the first input of the OR gate. The source of the second MOSFET is grounded. The gate of the second MOSFET and the second input of the OR gate are respectively input to the reset signal. The logic switch selects to conduct either the output of the logic switch and the first voltage input, or selects to conduct either the output of the logic switch or the second voltage input, based on the indication signal output by the magnitude light judgment circuit. When a reset signal is input, the gate of the second MOSFET is high, the second MOSFET is turned on, and the output of the OR gate is high. When the reset signal changes from high to low, the second MOSFET is turned off, and the first MOSFET is turned on to charge the second capacitor. The voltage across the second capacitor rises from low to high, corresponding to a high output voltage from the inverter. When the voltage across the second capacitor reaches the inverter's threshold, the inverter output switches to low, thus widening the reset signal. When the logic switch turns on the first voltage input, the logic switch outputs a first reference voltage, making the gate voltage of the first MOSFET equal to the first reference voltage. The voltage difference V between the source and gate of the first MOSFET... SG The first MOSFET has a relatively large on-state current, and the second capacitor has a short charging time, resulting in a relatively short recovery time for the reset signal. When the logic switch turns on the second voltage input, it outputs a second reference voltage, making the gate voltage of the first MOSFET equal to the second reference voltage. The voltage difference V between the source and gate of the first MOSFET... sg Because the current drawn by the first MOSFET is relatively small, the charging time of the second capacitor is long, resulting in a relatively long widening time for the reset signal. Thus, the widening time of the reset signal can be adjusted using the reset signal widening circuit, which in turn adjusts the reset discharge time of the limiting amplifier.

[0033] In some embodiments, an optical module is provided, wherein the light size determination circuit includes:

[0034] A mirror current source is connected in series between the photodetector and the reverse high voltage input terminal;

[0035] The sampling sub-circuit is connected at one end to the mirror current source and at the other end to ground;

[0036] An operational amplifier, the input of which is connected to one end of the sampling sub-circuit;

[0037] A comparator has a first input connected to the output of the operational amplifier, a second input for inputting a threshold voltage, and an output connected to the control terminal of the logic switch to output the first indication signal or the second indication signal.

[0038] One of the above technical solutions has the following advantages or beneficial effects: the mirror current source is used to mirror the photocurrent generated by the photodetector. The mirror output photocurrent is converted into a voltage signal by the sampling circuit to obtain a sampling voltage, which can indicate the optical power intensity of the optical receiving signal. The operational amplifier is used to amplify the sampling voltage by a preset ratio to facilitate the use of the sampling voltage in the large light judgment circuit. The comparator is used to compare the sampling voltage and the threshold voltage to output an indication signal based on the comparison result of the sampling voltage and the threshold voltage, thereby realizing the comparison of the optical power intensity of the optical receiving signal and the optical power threshold.

[0039] Some embodiments provide an optical module, and the sampling circuit includes a sampling resistor and a first capacitor. One end of the sampling resistor is connected to the mirror current source, and the other end of the sampling resistor is grounded. One end of the first capacitor is connected to one end of the sampling resistor, and the other end of the first capacitor is connected to the other end of the sampling resistor.

[0040] One of the above technical solutions has the following advantages or beneficial effects: the sampling circuit includes a sampling resistor and a first capacitor, and the two ends of the sampling resistor are connected in parallel with the first capacitor. The optical receiving signal is in a burst mode, and the first capacitor can store electric charge and discharge when the photodetector does not receive the optical receiving signal to buffer the instability of the comparator when there is no light.

[0041] Some embodiments provide an optical module, and the second input of the logic switch is connected to the output of the operational amplifier.

[0042] One of the above technical solutions has the following advantages or beneficial effects: the second voltage input of the logic switch is connected to the output of the operational amplifier, so that the logic switch can adjust the voltage of the second voltage input based on the intensity of the received optical power when the optical power intensity of the optical receiving signal is greater than or equal to the optical power threshold, thereby being able to adjust the signal spreading time based on the intensity of the received optical power. BRIEF DESCRIPTION OF DRAWINGS

[0043] In order to more clearly illustrate the technical solutions in the present disclosure, the drawings used in some embodiments of the present disclosure will be briefly introduced as follows. Obviously, the drawings in the following description are only some drawings of the embodiments of the present disclosure, and other drawings can also be obtained by those skilled in the art according to these drawings. In addition, the drawings in the following description can be regarded as schematic diagrams, and are not limited to the actual size, actual process, actual timing of signals, etc. of the products involved in the embodiments of the present disclosure.

[0044] Figure 1 Partial structure diagram of an optical communication system according to some embodiments;

[0045] Figure 2 Partial structure diagram of a host computer according to some embodiments;

[0046] Figure 3 Structure diagram of an optical module according to some embodiments;

[0047] Figure 4 Exploded view of an optical module according to some embodiments;

[0048] Figure 5 Structure diagram of an optical receiving component according to some embodiments;

[0049] Figure 6 Partial structure diagram of an optical receiving component according to some embodiments;

[0050] Figure 7 Structure diagram of a circuit board according to some embodiments;

[0051] Figure 8 Circuit diagram of a transimpedance amplifier and a limiting amplifier according to some embodiments;

[0052] Figure 9 System timing diagram according to some embodiments;

[0053] Figure 10 Circuit diagram of another transimpedance amplifier and limiting amplifier according to some embodiments;

[0054] Figure 11 Circuit diagram of a reset signal generation circuit according to some embodiments;

[0055] Figure 12 Timing diagram of generation of a first reset signal according to some embodiments;

[0056] Figure 13 Another system timing diagram according to some embodiments;

[0057] Figure 14A circuit schematic of an optical module according to some embodiments;

[0058] Figure 15 A circuit schematic of a size light judging circuit according to some embodiments;

[0059] Figure 16 A circuit schematic of a reset signal stretching circuit according to some embodiments;

[0060] Figure 17 A timing diagram of a reset signal stretching according to some embodiments;

[0061] Figure 18 A timing diagram of a reset signal stretching according to some embodiments;

[0062] Figure 19 A circuit schematic of an optical module according to some embodiments;

[0063] Figure 20 A timing diagram of a reset signal stretching according to some embodiments. DETAILED DESCRIPTION

[0064] Some embodiments of the present disclosure will be described in detail below with reference to the drawings. However, the described embodiments are only some embodiments of the present disclosure, not all embodiments. Based on the embodiments provided in the present disclosure, all other embodiments obtained by those of ordinary skill in the art are within the scope of protection of the present disclosure.

[0065] Unless otherwise required by context, the term "comprises" is to be interpreted as an open, inclusive meaning, i.e. "including but not limited to"; the terms "first", "second" are not to be interpreted as indicating or implying relative importance or indicating the upper limit of the number; the term "multiple" means two or more; the term "connected" should be interpreted broadly, for example, "connected" can be fixedly connected, or detachably connected, or integrated, can be directly connected, or indirectly connected through an intermediate medium; the use of the terms "adapted to" or "configured to" means open and inclusive language, which does not exclude devices adapted to or configured to perform additional tasks or steps; the terms "parallel", "vertical", "same", "consistent" or "flush" and the like are not limited to absolute mathematical relationships, but also include acceptable error ranges generated in practice, and also include differences based on the same design concept but due to manufacturing reasons.

[0066] In optical communication technology, in order to establish information transmission between information processing devices, information is loaded onto light, and the transmission of information is carried out by using the propagation speed of light. The light loaded with information is an optical signal. The optical signal can reduce the loss of optical power when transmitted in an optical information transmission device, and realize long-distance transmission of the optical signal. At the same time, the cost of optical information transmission devices such as optical fibers is lower than that of electrical information transmission devices such as copper wires. Therefore, optical communication technology can realize high-speed, long-distance and low-cost information transmission.

[0067] Information processing devices generally include optical network terminals (ONUs), gateways, routers, switches, mobile phones, computers, servers, tablets, televisions, etc. Optical information transmission devices generally include optical fibers and optical waveguides, etc. The signals that information processing devices can recognize and process are electrical signals, while optical communication technology uses optical signals for transmission, which requires optical modules to convert optical signals and electrical signals.

[0068] Optical modules can realize the mutual conversion of optical signals and electrical signals between information processing devices and optical information transmission devices. In some embodiments, at least one of the optical signal input end or the optical signal output end of the optical module is connected with an optical fiber, and at least one of the electrical signal input end or the electrical signal output end of the optical module is connected with an optical network terminal; a first optical signal from the optical fiber is transmitted to the optical module, the optical module converts the first optical signal into a first electrical signal, and transmits the first electrical signal to the optical network terminal; a second electrical signal from the optical network terminal is transmitted to the optical module, the optical module converts the second electrical signal into a second optical signal, and transmits the second optical signal to the optical fiber.

[0069] Since multiple information processing devices can transmit information through electrical signals, at least one of the multiple information processing devices needs to be directly connected with the optical module, without the need for all information processing devices to be directly connected with the optical module. Here, the information processing device directly connected with the optical module is also referred to as the host computer of the optical module. In addition, the optical signal input end or the optical signal output end of the optical module is referred to as an optical port, and the electrical signal input end or the electrical signal output end of the optical module is referred to as an electrical port.

[0070] Figure 1 A partial structure diagram of an optical communication system according to some embodiments. As shown in Figure 1 , the optical communication system mainly includes a remote information processing device 1000, a local information processing device 2000, a host computer 100 of an optical module, an optical module 200, an optical fiber 101 and a network cable 103, wherein the optical fiber 101 belongs to an optical information transmission device, and the network cable 103 belongs to an electrical information transmission device.

[0071] In some embodiments, one end of the optical fiber 101 extends towards the remote information processing device 1000, and the other end of the optical fiber 101 is connected to the optical module 200 through the optical port of the optical module 200. The optical signal can be totally reflected in the optical fiber 101, and the propagation of the optical signal in the direction of total reflection can maintain the original optical power. The optical signal is totally reflected multiple times in the optical fiber 101 to transmit the optical signal from the remote information processing device 1000 to the optical module 200, or to transmit the optical signal from the optical module 200 to the remote information processing device 1000, thereby realizing long-distance information transmission based on low power loss.

[0072] The optical communication system includes one or more optical fibers 101. In some embodiments, the optical fiber 101 is detachably connected to the optical module 200; in some embodiments, the optical fiber 101 is non-detachably connected to the optical module 200.

[0073] The host computer 100 is configured to provide a data signal to the optical module 200, or receive a data signal from the optical module 200, or monitor or control the working state of the optical module 200.

[0074] The host computer 100 includes a housing accommodating the optical module 200, and an optical module interface 102 disposed on the housing. The optical module 200 is inserted into the housing through the optical module interface 102, so that the host computer 100 and the optical module 200 establish a one-way or two-way electrical signal connection.

[0075] The host computer 100 further includes an external electrical interface, which can access an electrical signal network. In some embodiments, the external electrical interface includes a universal serial bus (USB) interface or a network cable interface 104. The network cable interface 104 is configured to access a network cable 103, so that the host computer 100 and the network cable 103 establish a one-way or two-way electrical signal connection.

[0076] One end of the network cable 103 is connected to the local information processing device 2000, and the other end of the network cable 103 is connected to the host computer 100, so that an electrical signal connection is established between the local information processing device 2000 and the host computer 100 through the network cable 103. In some embodiments, a third electrical signal emitted by the local information processing device 2000 is transmitted to the host computer 100 through the network cable 103, the host computer 100 generates a second electrical signal according to the third electrical signal, the second electrical signal from the host computer 100 is transmitted to the optical module 200, the optical module 200 converts the second electrical signal into a second optical signal, and transmits the second optical signal to the optical fiber 101, and the second optical signal is transmitted to the remote information processing device 1000 in the optical fiber 101.

[0077] In some embodiments, the first optical signal from the remote information processing device 1000 is transmitted through the optical fiber 101, the first optical signal from the optical fiber 101 is transmitted to the optical module 200, the optical module 200 converts the first optical signal into a first electrical signal, the optical module 200 transmits the first electrical signal to the host computer 100, the host computer 100 generates a fourth electrical signal according to the first electrical signal, and the fourth electrical signal is transmitted to the local information processing device 2000.

[0078] In some embodiments, the optical module is a tool for converting optical signals and electrical signals, and in the conversion process of the optical signals and the electrical signals, the information does not change, and the encoding or decoding mode of the information changes.

[0079] The host computer 100 includes an optical network terminal, an optical line terminal (OLT), an optical network device (ONT), or a data center server, etc.

[0080] Figure 2 A partial structure diagram of a host computer according to some embodiments. In order to clearly show the connection relationship between the optical module 200 and the host computer 100, Figure 2 Only the structure of the host computer 100 related to the optical module 200 is shown. As Figure 2 shown, in some embodiments, the host computer 100 further includes a PCB circuit board 105 arranged in the accommodation cavity, and a cage 106 arranged on the surface of the PCB circuit board 105; the optical module 200 is inserted into the cage 106 and fixed by the cage 106.

[0081] In some embodiments, the cage 106 is provided with a heat sink 107, which can dissipate heat for the optical module; in some embodiments, the heat sink 107 has a fin or other protruding structure to increase the heat dissipation area.

[0082] In some embodiments, the cage 106 is internally provided with an electrical connector configured to access the electrical port of the optical module 200.

[0083] In some embodiments, the optical module 200 is inserted into the cage 106 of the host computer 100, and the optical module 200 is fixed by the cage 106. The heat generated by the optical module 200 is conducted to the cage 106, and then diffused through the heat sink 107.

[0084] In some embodiments, the optical module 200 is inserted into the cage 106 of the host computer 100, and the electrical port of the optical module 200 is connected with the electrical connector inside the cage 106, so that the optical module 200 and the host computer 100 establish an electrical signal connection.

[0085] In some embodiments, the optical port of the optical module 200 is connected with the optical fiber 101, so that the optical module 200 establishes optical signal connection with the optical fiber 101.

[0086] Figure 3 FIG. 1 is a structural diagram of an optical module according to some embodiments, Figure 4 FIG. 2 is an exploded view of the optical module according to some embodiments. As shown in Figure 3 and Figure 4 In some embodiments, the optical module 200 includes a shell, which includes an upper shell 201 and a lower shell 202. The upper shell 201 covers the lower shell 202, forming two openings 203 and 204, one of which is an electrical port and the other of which is an optical port. In some embodiments, the shell forms one opening, which is both an electrical port and an optical port.

[0087] In some embodiments, the upper shell 201 and the lower shell 202 are made of metal material, which is conducive to electromagnetic shielding and heat dissipation.

[0088] The assembly method of the upper shell 201 and the lower shell 202 facilitates the installation of the circuit board 300, the optical transmitting component 400, and the optical receiving component 500 into the shell, and the upper shell 201 and the lower shell 202 can encapsulate and protect the above-mentioned components.

[0089] The direction of the connection of the two openings 203 and 204 can be consistent with the length direction of the optical module 200, or can be inconsistent with the length direction of the optical module 200. For example, the opening 203 is located at the end of the optical module 200 (the right end of FIG. 1), and the opening 204 is also located at the end of the optical module 200 (the left end of FIG. 1). Alternatively, the opening 203 is located at the end of the optical module 200, and the opening 204 is located at the side of the optical module 200. Figure 3 Figure 3

[0090] In some embodiments, the lower shell 202 includes a bottom plate 2021 and two lower side plates 2022 located on both sides of the bottom plate 2021 and perpendicular to the bottom plate 2021; the upper shell 201 includes a cover plate 2011, which covers the two lower side plates 2022 of the lower shell 202 to form the shell.

[0091] In some embodiments, the lower shell 202 includes a bottom plate 2021 and two lower side plates 2022 located on both sides of the bottom plate 2021 and perpendicular to the bottom plate 2021; the upper shell 201 includes a cover plate 2011 and two upper side plates 2012 located on both sides of the cover plate 2011 and perpendicular to the cover plate 2011, and the two upper side plates 2012 and the two lower side plates 2022 are combined to cover the lower shell 202 by the upper shell 201. ​​

[0092] As shown in Figure 3 and Figure 4 In some embodiments, the light module includes a circuit board 300 disposed in the housing, the circuit board 300 including circuit traces, electronic components and chips, etc. The electronic components and chips are connected according to the circuit design through the circuit traces to realize the functions of power supply, electrical signal transmission and grounding, etc. The electronic components can include capacitors, resistors, transistors, metal oxide semiconductor field effect transistors (MOSFETs). The chips can include microcontroller units (MCUs), laser drive chips, transimpedance amplifiers (TIAs), limiting amplifiers (LAs), clock and data recovery chips (CDRs), power management chips, digital signal processing (DSP) chips.

[0093] In some embodiments, the circuit board includes a rigid circuit board, which can also realize the bearing function due to its relatively hard material, such as the rigid circuit board can stably bear the above-mentioned electronic components and chips; the rigid circuit board can also be inserted into the electrical connector in the cage 106 of the upper computer 100.

[0094] In some embodiments, the circuit board also includes a flexible circuit board, which can be used independently; it can also be used in cooperation with the rigid circuit board.

[0095] In some embodiments, the circuit board also includes a gold finger formed on the surface of its end, the gold finger being composed of a plurality of pins independent of each other.

[0096] In some embodiments, the gold finger 301 is disposed on the surface of one side of the circuit board 300 (for example, the upper surface as shown in Figure 4 In some embodiments, the gold finger 301 is disposed on the surfaces of both upper and lower sides of the circuit board 300 to provide a larger number of pins to adapt to occasions requiring a large number of pins.

[0097] In some embodiments, the golden finger of the circuit board extends from the electrical port and is inserted into the electrical connector of the host computer 100; the circuit board is inserted into the cage 106, and the golden finger 301 is in electrical connection with the electrical connector in the cage 106. The golden finger 301 is configured to establish electrical connection with the host computer, and can realize functions such as power supply, grounding, two-wire synchronous serial (Inter-Integrated Circuit, I2C) signal transmission, data signal transmission, etc. Exemplarily, the golden finger 301 includes a reset pin, which can be used to transmit a reset signal issued by the host computer.

[0098] In some embodiments, the optical module 200 further includes an unlocking component 600 located outside the shell thereof. The unlocking component 600 is configured to realize the fixed connection between the optical module 200 and the host computer, or to release the fixed connection between the optical module 200 and the host computer.

[0099] For example, the unlocking component 600 is located outside the two lower side plates 2022 of the lower shell 202 and includes a clamping component matched with the cage 106 of the host computer 100. When the optical module 200 is inserted into the cage 106, the optical module 200 is fixed in the cage 106 by the clamping component of the unlocking component 600; when the unlocking component 600 is pulled, the clamping component of the unlocking component 600 moves, thereby changing the connection relationship between the clamping component and the host computer, to release the fixation of the optical module 200 to the host computer, so that the optical module 200 can be pulled out of the cage 106.

[0100] In some embodiments, the light emitting component 400 and the light receiving component 500 are physically separated from the circuit board 300, and the light emitting component 400 and the light receiving component 500 are electrically connected to the circuit board 300 through corresponding flexible circuit boards or electrical connectors. The light emitting component is used to generate a light emitting signal, and the light receiving component 500 is used to receive a light receiving signal.

[0101] In some embodiments, at least one of the light emitting component 400 and the light receiving component 500 can be directly arranged on the circuit board 300. For example, at least one of the light emitting component 400 and the light receiving component 500 can be arranged on the surface of the circuit board 300 or the side edge of the circuit board 300.

[0102] In some embodiments, the optical module 200 can include a round square tube body 205, which can connect the light emitting component 400 and the light receiving component 500. The round square tube body 205 can be provided with optical devices such as lenses, optical filters, etc. The optical devices are used to change the transmission direction of the light receiving signal and the light emitting signal.

[0103] In some embodiments, the optical module 200 can include a fiber adapter 700, which is located in the optical port of the optical module 200. The fiber adapter 700 is used to connect the optical fiber 101 to transmit the optical receiving signal inputted through the optical fiber 101 into the optical module 200 and transmit the optical emitting signal to the optical fiber 101.

[0104] Figure 5 A structural schematic diagram of an optical receiving component according to some embodiments, Figure 6 A partial structural schematic diagram of an optical receiving component according to some embodiments. As shown in Figure 5 and Figure 6 In some embodiments, the optical receiving component 500 includes a tube base 510 and a tube cap 520. The tube cap 520 covers the top of the tube base 510 and is fixedly connected with the tube base 510. The tube cap 520 and the tube base 510 can form a relatively closed space, in which a photodetector 530 and a TIA 540 can be arranged. The photodetector 530 is electrically connected with the TIA 540. Of course, other devices such as resistors or capacitors can also be arranged in the relatively closed space. When the optical receiving signal is transmitted to the photodetector 530, the photodetector 530 converts the optical receiving signal into a current signal, and the TIA 540 amplifies the current signal and outputs a voltage signal.

[0105] In some embodiments, the photodetector 530 can be arranged on the top surface of the tube base 510, and the TIA 540 is located on the side of the photodetector 530. The photodetector 530 is wire-connected with the TIA 540.

[0106] In some embodiments, the TIA 540 can be arranged on the top surface of the tube base 510, and the photodetector 530 is arranged on the top surface of the TIA 540. The photodetector 530 is wire-connected with the TIA 540.

[0107] In some embodiments, the tube base 510 is provided with a pin 550, which penetrates the tube base 510 so that the top of the pin 550 protrudes from the top surface of the tube base 510. The TIA 540 can be wire-connected with the pin 550 to electrically connect the circuit board 300 through the pin 550.

[0108] Figure 7 A structural diagram of a circuit board according to some embodiments, Figure 8 A circuit diagram of a TIA and a LA according to some embodiments. As shown in Figure 7 and Figure 8As shown, in some embodiments, the LA 310 is disposed on the circuit board 300, and the TIA 540 is electrically connected to the LA 310. The LA 310 limits the amplitude of the voltage signal output by the TIA 540 and outputs an electrical signal through an output terminal. Exemplarily, the voltage signal limited and amplified by the LA 310 can be transmitted to the host computer through the gold finger 301.

[0109] In some embodiments, when the optical module 200 is used for XGS-PON OLT, the optical module 200 needs to complete the burst reception of the optical receiving signal in the uplink. The XGS-PON OLT connects multiple ONUs through an optical network, and the amplitudes of the optical receiving signals transmitted to the optical module 200 at different times can be different. In order to enable the optical module 200 to quickly recover the optical receiving signal in the uplink, a reset signal needs to be added to the TIA 540 and the LA 310, so that when the optical receiving signal arrives, the TIA 540 can automatically adjust the gain, and the AC capacitor of the LA 310 is discharged to recover to the common mode level state, so that the optical receiving signal can be quickly recovered into a digital signal.

[0110] In some embodiments, the reset input terminal of the TIA 540 can be connected to a reset pin to reset based on the reset signal (RST) transmitted by the reset pin. When there is no light in the uplink or the light in the uplink is small, the gain of the TIA 540 will be locked at the maximum value; when the light in the uplink is large, the TIA 540 will automatically adjust the gain. Exemplarily, the TIA 540 starts automatic gain adjustment based on the reset signal, that is, the TIA 540 starts to start gain adjustment only after receiving the reset signal. In the burst reception mode, some host computer board cards will issue a reset signal when the optical module 200 has no light, so that the TIA 540 will lock the gain at the maximum value. When large light arrives, if there is no reset signal, the large light + large gain will cause the electrical signal output by the TIA 540 to be abnormal, thereby causing the electrical signal recovered and output by the LA 310 to be abnormal. Moreover, if the reset signal arrives relatively late, the optical receiving signal before the reset signal arrives will be recovered into an abnormal electrical signal.

[0111] In some embodiments, the host computer board card can trigger the CDR on the host computer board card to extract the clock of the uplink optical signal based on the rising edge of the output level of the SD detection circuit 320.

[0112] In some embodiments, the reset input terminal of the LA 310 is connected to the reset pin in the gold finger 301, so that the LA 310 performs a reset operation based on the reset signal RST issued by the host computer through the reset pin.

[0113] In some embodiments, the LA 310 internally includes an AC coupling capacitor 311. In normal operation, the reset signal RST is low, the switch is open, and a large resistance (Kohm level) is used to pull the AC coupling capacitor 311 to a common mode state, ensuring normal signal transmission. In the reset mode, the reset signal RST is high, the switch is closed, and a small resistance (<10 ohm) is used to pull the AC coupling capacitor 311 to a common mode state. When the uplink light is large, the signal amplitude input to the LA 310 is large, the AC coupling capacitor 311 has a large charge, and a relatively long time is needed to pull the AC coupling capacitor 311 to a common mode state. If the discharge time is too short, the AC coupling capacitor 311 will not be fully discharged, which will cause the LA 310 output signal to be abnormal. When the uplink light is small, the signal amplitude input to the LA 310 is small, the AC coupling capacitor 311 has a small charge, and a relatively short time is needed to pull the AC coupling capacitor 311 to a common mode state. If the discharge time is too long, the AC coupling capacitor 311 will have a small signal amplitude after discharge, and the LA 310 will need a longer time to recover the complete electrical signal. In this way, if the LA 310 reset time is short, the AC coupling capacitor 311 will not be fully discharged when the light is large; if the LA 310 reset time is long, the AC coupling capacitor 311 will be reset for a long time when the light is small, which will make the LA 310 output signal for a long time.

[0114] In some embodiments, an SD (Signal Detect) detection circuit 320 can be provided on the circuit board 300, and the SD detection circuit 320 detects the signal amplitude on the AC coupling capacitor 311 to output an SD detection signal. For example, when the signal amplitude exceeds a set threshold, the SD detection circuit 320 outputs a high level; when the signal amplitude is less than the set threshold, the SD detection circuit 320 outputs a low level. If the LA 310 reset time is too long, the SD detection circuit 320 will increase the response time.

[0115] In some embodiments, the SD detection circuit 320 can be packaged in the LA 310, and the LA 310 is provided with a detection signal output pin to output the SD detection signal through the detection signal output pin.

[0116] Figure 9 A system timing diagram according to some embodiments. As shown in FIG. 3, the system includes a laser driver 301, a laser amplifier 310, a laser 330, and a circuit board 300. The laser driver 301 is connected to the laser amplifier 310 through a signal line 311, and the laser amplifier 310 is connected to the laser 330 through a signal line 312. The circuit board 300 is connected to the laser driver 301 through a reset signal line 313, and the circuit board 300 is connected to the laser amplifier 310 through a detection signal line 314. Figure 9As shown in some embodiments, the light receiving signal is transmitted to the light receiving component at time t1, the SD detection signal is output at time t2, t2 is later than t1, the host board card outputs the reset signal at time t3, t3 is later than t1, the TIA 540 is reset based on the reset signal output by the host board card, and the LA 310 is reset based on the SD detection signal. Before the optical module receives the reset signal output by the host board card, the signal output by the LA 310 is abnormal due to the abnormal output signal of the TIA 540. Moreover, the clock of the uplink optical signal extracted by the CDR on the host board card is triggered by the SD signal before the reset signal output by the host board card, which causes the CDR to extract the clock of abnormal data, resulting in data packet loss.

[0117] Figure 10 A circuit diagram of another TIA and LA according to some embodiments, Figure 11 A circuit diagram of a reset signal generation circuit according to some embodiments. As Figure 10 and Figure 11 As shown in some embodiments, the circuit board 300 can be provided with a reset signal generation circuit 330, the input end of the reset signal generation circuit 330 is connected to the output end of the SD detection circuit 320, and the output end of the reset signal generation circuit 330 is connected to the reset input end of the TIA 540. The reset signal generation circuit 330 can generate a first reset signal based on the SD signal output by the SD detection circuit 320, and the first reset signal can be used for resetting the TIA 540. The time of the first reset signal reaching the TIA 540 is earlier than the time of the reset signal input through the reset pin in the gold finger 301 reaching the TIA 540, which facilitates the TIA 540 to be reset as early as possible based on the first reset signal.

[0118] In some embodiments, the reset signal generation circuit 330 includes an XOR gate 331 and a delay sub-circuit 332. The first input end of the XOR gate 331 is connected to the output end of the SD detection circuit 320, the input end of the delay sub-circuit 332 is connected to the output end of the SD detection circuit 320, the second input end of the XOR gate 331 is connected to the output end of the delay sub-circuit 332, and the output end of the XOR gate 331 is connected to the reset input end of the TIA 540. The SD detection signal output by the SD detection circuit 320 and the SD detection signal delayed by the delay sub-circuit 332 are operated by the XOR gate 331 to output the first reset signal.

[0119] Figure 12 A timing diagram of the generation of a first reset signal according to some embodiments. As Figure 12As shown, in some embodiments, the SD detection signal output by the SD detection circuit 320 at time t2 is transmitted to the XOR gate 331, and the rising edge of the SD detection signal triggers the generation of the first reset signal; the delay sub-circuit 332 delays the SD detection signal output by the SD detection circuit 320, and the delayed SD detection signal is transmitted to the XOR gate 331 at time t2', which is later than t2; the XOR gate 331 XORs the SD detection signal and the delayed SD detection signal, so that the rising edge of the delayed SD detection signal triggers the end of the first reset signal, thereby forming the first reset signal with a preset high level width of (t2'-t2). In this way, based on the XOR gate 331 and the delay sub-circuit 332, the reset signal generation circuit 330 generates the first reset signal with a preset high level width.

[0120] In some embodiments, the delay sub-circuit 332 can include a buffer 3321, and the input end of the buffer 3321 is connected to the output end of the SD detection circuit 320. The buffer 3321 is used to temporarily store the SD detection signal output by the SD detection circuit 320. The buffer 3321 can delay the time when the SD detection signal reaches the second input end of the XOR gate 331.

[0121] In some embodiments, the delay sub-circuit 332 can include a delay device 3322, and the input end of the delay device 3322 is connected to the output end of the buffer 3321, and the output end of the delay device 3322 is connected to the second input end of the XOR gate 331. The delay device 3322 can delay the time when the SD detection signal reaches the second input end of the XOR gate 331. The delay device 3322 can include a capacitor.

[0122] In some embodiments, the delay device 3322 can include a resistor and a capacitor. One end of the resistor can be connected to the output end of the buffer 3321, the other end of the resistor can be connected to one end of the capacitor, and the other end of the capacitor is connected to the second input end of the XOR gate 331. The delay device 3322 is equivalent to charging the capacitor through the resistor with the input voltage, and the corresponding relationship between the output voltage and the charging time is as follows: t=-R*C*ln((E-V) / E), where t is the charging time, R is the resistance value, C is the capacitance value, E is the input voltage, V is the voltage across the capacitor, and E-V is the output voltage. According to the corresponding relationship between the output voltage and the charging time, it can be seen that the charging time t is proportional to R*C, that is, the greater R*C, the longer the charging time t. The width of the first reset signal is adjusted by the product of the resistance value of the resistor and the capacitance value of the capacitor.

[0123] In some embodiments, an OR gate 340 can be provided on the circuit board 300, a first input end of the OR gate 340 is connected to the output end of the reset signal generation circuit 330, a second input end of the OR gate 340 is connected to the reset pin, and an output end of the OR gate 340 is connected to the reset input end of the TIA 540. The OR gate 340 can OR the first reset signal generated by the reset signal generation circuit 330 and the reset signal input through the reset pin, and output a second reset signal to the reset input end of the TIA 540, so that the TIA 540 can reset the TIA 540 based on the second reset signal.

[0124] Figure 13 is a timing diagram of another system according to some embodiments. As shown in Figure 13 some embodiments, when the optical receiving signal arrives, the SD detection signal output by the SD detection circuit 320 changes from low to high at time t2, so that the reset signal generation circuit 330 generates a first reset signal at time t2 and transmits the first reset signal to the OR gate 340, and the OR gate 340 transmits the first reset signal to the reset input end of the TIA 540, so that the TIA 540 is quickly reset at time t2, and the LA 310 can output normal data at time t2. At time t3, the reset signal issued by the host board card is transmitted to the OR gate 340 through the reset pin, and the OR gate 340 transmits the reset signal to the reset input end of the TIA 540, so that the TIA 540 is reset again at time t3 based on the reset signal issued by the host board card. When the reset signal issued by the host board card is gone, the SD detection signal output by the SD detection circuit 320 changes from low to high again, so that the reset signal generation circuit 330 generates a first reset signal at time t4 and transmits the first reset signal to the OR gate 340, and the OR gate 340 transmits the first reset signal to the reset input end of the TIA 540, so that the TIA 540 is quickly reset again. In this way, before the reset signal issued by the host board card arrives, the TIA 540 can be quickly reset, so that the TIA 540 can output normal data to the LA 310, so that the LA 310 can output normal data. Moreover, the CDR can extract the correct clock, and the problem of packet loss caused by the error of the CDR clock is avoided.

[0125] Figure 14 is a circuit schematic diagram of an optical module according to some embodiments, Figure 15 is a circuit diagram of a size light judgment circuit according to some embodiments, Figure 16 is a circuit diagram of a reset signal expansion circuit according to some embodiments. As shown in Figure 14- Figure 16As shown, in some embodiments, the circuit board 300 can be provided with a light power judgment circuit 350, which is configured to judge the light power intensity of the optical receiving signal. For example, the light power judgment circuit 350 is configured to compare the light power intensity of the optical receiving signal with a light power threshold value, and output a corresponding indication signal based on different comparison results. For example, when the light power intensity of the optical receiving signal is greater than or equal to the light power threshold value, the output end of the light power judgment circuit 350 outputs a first indication signal; when the light power intensity of the optical receiving signal is less than the light power threshold value, the output end of the light power judgment circuit 350 outputs a second indication signal.

[0126] In some embodiments, the circuit board 300 can be provided with a reset signal spreading circuit 360, which is connected to the output end of the light power judgment circuit 350, the reset pin in the gold finger 301, and the reset input end of the LA 310. The reset signal spreading circuit 360 adjusts the spreading of the reset signal based on the indication signal output by the light power judgment circuit 350, so as to adjust the width of the reset signal transmitted to the LA 310, so that the discharging time of the AC coupling capacitor 311 in the LA 310 is more appropriate.

[0127] In some embodiments, the light power judgment circuit 350 can include a mirror current source 351 connected in series between the positive electrode of the photodetector 530 and a reverse high-voltage input end. The reverse high-voltage input end is configured to provide a working voltage to the photodetector 530. When the optical receiving signal is transmitted to the photodetector 530, the photodetector 530 receives the optical receiving signal to generate a photoelectric current, and the photoelectric current is transmitted to the TIA 540; the mirror current source 351 is configured to mirror the photoelectric current generated by the photodetector 530.

[0128] In some embodiments, the light power judgment circuit 350 can include a sampling sub-circuit 352, one end of which is connected to the mirror current source 351, and the other end of which is grounded. The photoelectric current mirrored by the mirror current source 351 is converted into a voltage signal by the sampling sub-circuit 352, so as to obtain a sampling voltage, which can indicate the light power intensity of the optical receiving signal.

[0129] In some embodiments, the light power judgment circuit 350 can include an operational amplifier 353, an input end of which is connected to one end of the sampling sub-circuit 352. The operational amplifier 353 is configured to amplify the sampling voltage by a preset ratio, so as to facilitate the use of the sampling voltage in the light power judgment circuit 350.

[0130] In some embodiments, the large-small light judging circuit 350 can include a comparator 354 configured to compare the sampling voltage with a threshold voltage to output an indication signal based on a comparison result of the sampling voltage and the threshold voltage, thereby realizing comparison of the optical power intensity of the optical receiving signal with the optical power threshold. For example, when the sampling voltage is greater than or equal to the threshold voltage, the comparator 354 can output a first indication signal; and when the sampling voltage is less than the threshold voltage, the comparator 354 can output a second indication signal. The first indication signal can be 1, and the second indication signal can be 0.

[0131] In some embodiments, a first input terminal of the comparator 354 is connected to an output terminal of the operational amplifier 353, and a second input terminal of the comparator 354 is connected to a threshold voltage input terminal. The threshold voltage input terminal is configured to input a threshold voltage, and the voltage value of the threshold voltage corresponds to the optical power threshold and is used to identify the optical power threshold. The operational amplifier 353 amplifies the sampling voltage, thereby facilitating selection of the threshold voltage and comparison of the sampling voltage and the threshold voltage.

[0132] In some embodiments, the sampling sub-circuit 352 can include a sampling resistor 3521, one end of the sampling resistor 3521 being connected to the mirror current source 351, and the other end of the sampling resistor 3521 being grounded.

[0133] In some embodiments, the sampling sub-circuit 352 can include a first capacitor 3522, one end of the first capacitor 3522 being connected to one end of the sampling resistor 3521, and the other end of the first capacitor 3522 being connected to the other end of the sampling resistor 3521. When the optical receiving signal is in a burst mode, the first capacitor 3522 can store electric charges and discharge when the photodetector 530 does not receive the optical receiving signal, thereby buffering instability of the comparator 354 in the absence of light.

[0134] In some embodiments, the reset signal spreading circuit 360 can include a logic switch 361, a control terminal of the logic switch 361 being connected to an output terminal of the large-small light judging circuit 350. The logic switch 361 includes an output terminal, a first voltage input terminal, or a second voltage input terminal, etc. The first voltage input terminal is configured to input a first reference voltage, and the second voltage input terminal is configured to input a second reference voltage. The first reference voltage and the second reference voltage can be constant values, and the first reference voltage or the second reference voltage can also be non-constant values. The logic switch 361 selects the output terminal and the first voltage input terminal to be turned on, or selects the output terminal and the second voltage input terminal to be turned on, based on the indication signal output by the large-small light judging circuit 350. For example, the first reference voltage can be less than the second reference voltage.

[0135] In some embodiments, the reset signal spreading circuit 360 can include a first MOS transistor 362. The gate of the first MOS transistor 362 is connected to the output of the logic switch 361, the source of the first MOS transistor 362 is connected to the power input, and the drain of the first MOS transistor 362 is used to output the conduction current. Illustratively, when the logic switch 361 is turned on by the first voltage input, the logic switch 361 outputs a first reference voltage, the voltage at the gate of the first MOS transistor 362 is equal to the first reference voltage, and the voltage difference V SG between the source and the gate of the first MOS transistor 362 is relatively large, and the conduction current of the first MOS transistor 362 is relatively large; when the logic switch 361 is turned on by the second voltage input, the logic switch 361 outputs a second reference voltage, the voltage at the gate of the first MOS transistor 362 is equal to the second reference voltage, and the voltage difference V sg between the source and the gate of the first MOS transistor 362 is relatively small, and the conduction current of the first MOS transistor 362 is relatively small. The first MOS transistor 362 can be a P-MOS transistor.

[0136] In some embodiments, the reset signal spreading circuit 360 can include a second capacitor 363. One end of the second capacitor 363 is connected to the drain of the first MOS transistor 362, and the other end of the second capacitor 363 is grounded. The conduction current of the first MOS transistor 362 can charge the second capacitor 363, the greater the conduction current of the first MOS transistor 362, the shorter the charging time of the second capacitor 363; the smaller the conduction current of the first MOS transistor 362, the longer the charging time of the second capacitor 363.

[0137] In some embodiments, the reset signal spreading circuit 360 can include a second MOS transistor 364. The drain of the second MOS transistor 364 is connected to the drain of the first MOS transistor 362, the source of the second MOS transistor 364 is grounded, and the gate of the second MOS transistor 364 is connected to the reset pin in the gold finger 301. When a reset signal is input through the reset pin, the input at the gate of the second MOS transistor 364 is high, the second MOS transistor 364 is turned on, and the drain of the first MOS transistor 362 is turned on. When the reset signal input through the reset pin changes from high to low, the input at the gate of the second MOS transistor 364 is low, the second MOS transistor 364 is turned off, and the first MOS transistor 362 charges the second capacitor 363. The second MOS transistor 364 can be an N-MOS transistor.

[0138] In some embodiments, the reset signal broadening circuit 360 may include an inverter 365 and an OR gate 366. The input of inverter 365 is connected to the drain of the first MOSFET 362, and the output of inverter 365 is connected to the first input of OR gate 366. The second input of OR gate 366 is connected to the reset pin in the gold finger 301. When a reset signal is input through the reset pin, the second MOSFET 364 is grounded, the input of inverter 365 is low, the output of inverter 365 is high, and the output of OR gate 366 is high. As the reset signal input through the reset pin changes from high to low, the first MOSFET 362 charges the second capacitor 363. When the voltage of the second capacitor 363 rises to the level at which inverter 365 determines the input to be high, the output of inverter 365 switches to low, the first input of OR gate 366 is low, the second input of OR gate 366 is low, and the output of OR gate 366 is low. For example, when the voltage of the second capacitor 363 rises above the input threshold of the inverter, the input of the inverter 365 is high, and the output of the inverter 365 is low.

[0139] In some embodiments, the reset signal broadening circuit 360 may include a buffer 367. The input of the buffer 367 is connected to the reset pin in the gold finger 301, and the output of the buffer 367 is connected to the second input of the OR gate 366. The buffer 367 may increase the strength of the reset signal input through the reset pin, and protect the OR gate 366 and reduce the OR gate 366 from other electrical interference.

[0140] Figure 17 This is a stretched timing diagram of a reset signal according to some embodiments. Figure 18 This is a stretched timing diagram of another reset signal according to some embodiments; wherein, Figure 17 This paper presents a timing sequence for stretching a reset signal when the optical power intensity of the received optical signal is less than an optical power threshold. Figure 18 The timing diagram illustrates a reset signal stretching sequence when the optical power intensity of the received optical signal is greater than or equal to an optical power threshold. For example... Figure 17 and Figure 18 As shown, in some embodiments, when the size light determination circuit 350 inputs a second indication signal to the reset signal broadening circuit 360, the broadening time of the reset signal broadening circuit 360 is T1; when the size light determination circuit 350 inputs a first indication signal to the reset signal broadening circuit 360, the broadening time of the reset signal broadening circuit 360 is T2, where T1 < T2. Thus, when the optical power intensity of the received optical signal is greater than or equal to the optical power threshold, the reset time of LA 310 is relatively long, resulting in a relatively long discharge time for the AC coupling capacitor 311 in LA 310; when the optical power intensity of the received optical signal is less than the optical power threshold, the reset time of LA 310 is relatively short, resulting in a relatively short discharge time for the AC coupling capacitor 311 in LA 310.

[0141] Figure 19 This is a circuit schematic diagram of another optical module according to some embodiments. For example... Figure 19 As shown, in some embodiments, a first reference voltage is input to the first voltage input terminal of logic switch 361, and the second voltage input terminal of logic switch 361 is connected to the output terminal of operational amplifier 353. When the optical power intensity of the received optical signal is less than the optical power threshold, logic switch 361 conducts its first voltage input terminal and its output terminal based on a second indication signal, making the voltage at the gate of the first MOS transistor 362 equal to the first reference voltage. When the optical power intensity of the received optical signal is greater than or equal to the optical power threshold, logic switch 361 conducts its second voltage input terminal and its output terminal based on the second indication signal, making the voltage at the gate of the first MOS transistor 362 equal to the voltage output by operational amplifier 353.

[0142] Figure 20 This is an extended timing diagram of another reset signal according to some embodiments. Figure 20 The timing diagram illustrates a reset signal broadening sequence when the optical power intensity of the received optical signal exceeds an optical power threshold. For example... Figure 20 As shown, in some embodiments, if the optical power of the received optical signal changes, the voltage input to the second voltage input terminal of the logic switch 361 can change based on the change in the optical power of the received optical signal. This allows the reset signal broadening circuit 360 to adjust the broadening time T of the reset signal based on the optical power of the received optical signal, thereby enabling the adjustment of the discharge time of the AC coupling capacitor 311 in LA 310 based on the optical power of the received optical signal, making the broadening time T variable.

[0143] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. An optical module characterized by comprising: The application relates to an optical module. The circuit board is provided with a limiting amplifier and a reset signal generating circuit; The optical receiving component comprises a photodetector and a transimpedance amplifier, the photodetector is used for receiving a burst optical receiving signal, the input end of the transimpedance amplifier is electrically connected to the photodetector, and the output end of the transimpedance amplifier is electrically connected to the limiting amplifier; The reset signal generating circuit comprises: A delay sub-circuit, which is used for inputting a detection signal and performing delay processing on the detection signal; An XOR gate, which comprises a first input end and a second input end; the first input end is used for inputting the detection signal, the second input end is connected to the output end of the delay sub-circuit, the output end of the XOR gate is connected to the reset input end of the transimpedance amplifier, and the XOR gate outputs a first reset signal based on the detection signal and the delay-processed detection signal, so that the transimpedance amplifier is reset based on the first reset signal.

2. The optical module according to claim 1, characterized by The end of the circuit board is formed with a gold finger, the gold finger comprises a reset pin, and an OR gate is further arranged on the circuit board; The first input end of the OR gate is connected to the output end of the XOR gate, the second input end of the OR gate is connected to the reset pin, and the output end of the OR gate is connected to the reset input end of the transimpedance amplifier.

3. The optical module according to claim 1, characterized by The delay sub-circuit comprises a buffer and a delay device, the input end of the buffer is used for inputting the detection signal, the output end of the buffer is connected to the input end of the delay device, and the output end of the delay device is connected to the second input end of the XOR gate.

4. The optical module according to claim 1, characterized by An SD detection circuit is packaged in the limiting amplifier, and a detection signal output pin is formed on the limiting amplifier, the detection signal output pin is connected to the input end of the delay sub-circuit and the first input end of the XOR gate respectively.

5. The optical module of claim 1, wherein, An SD detection circuit is arranged on the circuit board, the input end of the SD detection circuit is connected to the limiting amplifier, and the output end of the SD detection circuit is connected to the input end of the delay sub-circuit and the first input end of the XOR gate respectively.

6. The optical module of claim 1, wherein, The optical receiving component further comprises a tube base and a tube cap, the tube base is provided with a pin, the photodetector and the transimpedance amplifier are arranged on the tube base, the photodetector is wire-bonded to the transimpedance amplifier, and the transimpedance amplifier is connected to the circuit board through the pin.

7. The optical module according to claim 2, wherein the circuit board is further provided with a large-small light judgment circuit and a reset signal broadening circuit; The input end of the large-small light judgment circuit is connected to the photodetector, so as to compare the intensity of the optical power of the optical receiving signal received by the photodetector with the size of an optical power threshold value; the output end of the large-small light judgment circuit outputs a first indication signal or a second indication signal, the first indication signal is used for indicating that the intensity of the optical power of the optical receiving signal is greater than or equal to the optical power threshold value, and the second indication signal is used for indicating that the intensity of the optical power of the optical receiving signal is less than the optical power threshold value; The reset signal broadening circuit comprises: a logic switch, a control terminal of which is connected to an output terminal of the size light judging circuit, a first input terminal of which inputs a first reference voltage, and a second input terminal of which inputs a second reference voltage, the first reference voltage being smaller than the second reference voltage; the logic switch being turned on at its second input terminal and output terminal based on the first indication signal, and the logic switch being turned on at its first input terminal and output terminal based on the second indication signal; a first MOS transistor, a gate of which is electrically connected to the output terminal of the logic switch, and a source of which is electrically connected to a power input terminal; a second capacitor, one end of which is electrically connected to a drain of the first MOS transistor, and the other end of which is grounded; an inverter, an input terminal of which is electrically connected to the drain of the first MOS transistor; a second MOS transistor, a drain of which is electrically connected to the drain of the first MOS transistor, a source of which is electrically connected to the ground, and a gate of which inputs a reset signal; an OR gate, a first input terminal of which is electrically connected to an output terminal of the inverter, and a second input terminal of which inputs the reset signal.

8. The optical module according to claim 7, the size light judging circuit comprising: a mirror current source, which is connected in series to the photodetector and a reverse high voltage input terminal; a sampling sub-circuit, one end of which is connected to the mirror current source, and the other end of which is grounded; an operational amplifier, input terminals of which are connected to one end of the sampling sub-circuit; a comparator, a first input terminal of which is connected to an output terminal of the operational amplifier, a second input terminal of which is used for inputting a threshold voltage, and an output terminal of which is connected to a control terminal of the logic switch, so as to output the first indication signal or the second indication signal.

9. The optical module according to claim 8, the sampling sub-circuit comprising a sampling resistor and a first capacitor; one end of the sampling resistor being connected to the mirror current source, the other end of the sampling resistor being grounded; one end of the first capacitor being connected to one end of the sampling resistor, and the other end of the first capacitor being connected to the other end of the sampling resistor.

10. The optical module according to claim 8, the second input terminal of the logic switch being connected to the output terminal of the operational amplifier.

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